CN114823383A

CN114823383A - Wafer level packaging method

Info

Publication number: CN114823383A
Application number: CN202110129193.0A
Authority: CN
Inventors: 黄河; 刘孟彬; 向阳辉
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2021-01-29
Filing date: 2021-01-29
Publication date: 2022-07-29

Abstract

The invention discloses a wafer level packaging method, which comprises the following steps: providing an electric adapter plate, wherein the upper surface of the electric adapter plate is provided with a naked first welding pad; forming a conductive bump on the first pad by an electroplating process; after the conductive bump is formed, providing at least one chip, wherein the lower surface of the chip is provided with a second welding pad; forming an adhesive layer on the lower surface of the chip or the upper surface of the electrical interposer; and forming an opening in the adhesive layer; bonding the chip on the electric adapter plate through the bonding layer, wherein the chip covers the opening to form a cavity which is used as a working cavity of the chip; and electrically connecting the first welding pad of the chip with the conductive bump; and the second welding pad of the chip realizes the rearrangement through the electric adapter plate.

Description

Wafer level packaging method

Technical Field

The invention relates to the field of semiconductor device manufacturing, in particular to a wafer level packaging method.

Background

At present, in order to meet the objectives of lower cost, more reliability, faster and higher density of integrated circuit packaging, the advanced packaging method mainly adopts wafer level system packaging, and compared with the traditional system packaging, the wafer level system packaging completes the packaging integration process on the wafer, so that the wafer level system packaging has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.

Silicon Interposer in Interposer is a device similar to a circuit board made of Silicon wafer, but its line width, node pitch, etc. are smaller than those of the circuit board. Chips with different functions, such as a CPU, a DRAM and the like can be connected to the same siliconinterperser, and a plurality of operations and data communication are completed through the siliconinterperser, so that electricity is saved, and the bandwidth is increased. Like a PCB, the silicon interposer generally has through holes (through silicon vias) filled with copper, and the result of the joint operation between different chips is transmitted to a package substrate connected to the silicon vias, and the package substrate is connected to a circuit board. The silicon interposer and the package substrate correspond to a bridge connecting a plurality of chips and the same circuit board. The silicon through hole of the silicon interposer is manufactured, the traditional process is complex, the diameter of the silicon through hole is limited and is generally controlled within 30 micrometers; if the silicon hole is made larger, the metal filled in the silicon hole is thermally expanded at a later stage of use, resulting in breakage of the silicon hole or the insulating layer. Therefore, the silicon pores can only be made smaller; however, the deposition of insulating materials, the deposition of barrier/seed layers, and the filling of metals in the small silicon holes become difficult, so that the process control is difficult, the yield is low, and the miniaturization of the package is not facilitated due to the fact that a multi-layer structure is longitudinally stacked on the circuit board.

Therefore, a new wafer level package structure and a method for manufacturing the same are desired. The yield can be improved, and the requirement of miniaturization can be met.

Disclosure of Invention

The invention aims to provide a wafer level packaging method which can solve the problems of low yield and longitudinal multi-layer stacking.

In order to solve the above technical problem, the present invention provides a wafer level packaging method, including:

providing an electric adapter plate, wherein the upper surface of the electric adapter plate is provided with a naked first welding pad;

forming a conductive bump on the first pad by an electroplating process;

after the conductive bump is formed, providing at least one chip, wherein the lower surface of the chip is provided with a second welding pad;

forming an adhesive layer on the lower surface of the chip or the upper surface of the electrical interposer; and forming an opening in the adhesive layer;

bonding the chip on the electric adapter plate through the bonding layer, wherein the chip covers the opening to form a cavity which is used as a working cavity of the chip; and electrically connecting the first pad of the chip with the conductive bump.

The invention has the beneficial effects that:

different chips are electrically connected with the circuit board through the electric adapter plate, and the conductive bump is formed between the chip and the electric adapter plate through an electroplating process, so that the problem of longitudinal multilayer stacking is solved, and the miniaturization of packaging is facilitated.

Furthermore, the chip and the electric adapter plate are bonded through the dry film, on one hand, the dry film is a photoetching material, a required pattern can be formed through a semiconductor process, the process is simple, the process is compatible with the semiconductor process, and batch production can be realized. And the elastic modulus of the dry film is relatively small, so that the dry film can be easily deformed and cannot be damaged when being subjected to thermal stress, and the bonding stress of the chip and the device wafer is reduced. When the dry film is photoetched, the dry film of the fence structure can be reserved on the periphery of the area where the conductive bump is preformed, so that when the conductive bump is formed, the conductive bump with a desired shape can be formed due to the blocking of the dry film, and the conductive bump is prevented from transversely overflowing. By forming the cavity in the adhesive layer, process steps (which would otherwise be required to form the cavity when the chip is manufactured) can be saved when a cavity needs to be formed underneath the chip.

Furthermore, when the bonding layer is formed, the projection of the bonding layer takes the center of the chip as the center, the coverage area is larger than 10% of the area of the chip, and the whole lower surface (except the area where the second welding pad is located) of the chip is preferably covered, so that when a plastic packaging layer is formed in a subsequent process, no gap is formed below the chip, the bonding strength is improved, and the yield is improved.

Furthermore, the chips are bonded on the electric adapter plate in advance, and the chips are pre-aligned, so that the chips and the conductive bumps can be subjected to hot-press bonding simultaneously, and the manufacturing efficiency is greatly improved compared with the mode that each chip and each conductive bump are sequentially bonded. Furthermore, the area of the overlapping area of the second welding pad and the conductive bump in the direction vertical to the surface of the electric adapter plate is larger than half of the area of the second welding pad, so that the bonding strength of the second welding pad and the conductive bump is improved.

Furthermore, the electric adapter plate can be a dielectric layer, the solder balls are located on the lower surface of the dielectric layer, the substrate can also be arranged below the dielectric layer, a silicon through hole structure is formed in the substrate, and the solder balls are located on the lower surface of the substrate. The through silicon via structure can be formed at different process stages according to actual conditions.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to 9 are schematic structural diagrams illustrating different steps in a wafer level packaging method according to embodiment 1 of the present invention.

Fig. 10 to 13 are schematic structural diagrams illustrating different steps in a wafer level packaging method according to embodiment 2 of the present invention.

Description of reference numerals:

10-a substrate; an 11-through silicon via structure; 200-a layer of dielectric material; 201-a first dielectric material; 202-a second dielectric material; 203-a third dielectric material; 21-an interconnect pad; 210-an interconnect line; 22-a conductive plug; 23-a first pad; 24-a conductive bump; 30-chip; 31-a second pad; 32-an adhesive layer; 33-opening; 40-plastic packaging layer; 50-solder balls; 60-capping the substrate.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

If the method herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.

Example 1

Embodiment 1 of the present invention provides a wafer level packaging method, including the following steps:

s01: providing an electric adapter plate, wherein the upper surface of the electric adapter plate is provided with a naked first welding pad;

s02: forming a conductive bump on the first pad by an electroplating process;

s03: after the conductive bump is formed, providing at least one chip, wherein the lower surface of the chip is provided with a second welding pad;

s04: forming an adhesive layer on the lower surface of the chip or the upper surface of the electrical interposer; and forming an opening in the adhesive layer; bonding the chip on the electric adapter plate through the bonding layer, wherein the chip covers the opening to form a cavity which is used as a working cavity of the chip; and electrically connecting the first pad of the chip with the conductive bump.

The first welding pads of the chip realize rearrangement through the electric adapter plate.

It should be noted that S0N in this specification does not represent the sequence of the manufacturing process.

Fig. 1 to 9 show corresponding structural schematic diagrams of different steps of the wafer level packaging method of the present embodiment, please refer to fig. 1 to 9 for detailed description of the steps.

The electrical interposer can be formed by a variety of methods, and this embodiment is described with one method as an example.

Referring to fig. 1 and 2, a substrate 10 is provided, and a through-silicon via structure 11 is formed inside an upper surface of the substrate 10. The material of the substrate 10 includes a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon carbon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and the like. The through-silicon via structure 11 is formed only inside the upper surface of the substrate 10, and does not penetrate through the lower surface of the substrate 10. The tsv structure 11 is a structure known in the art, and is formed by first forming a via, forming an insulating layer on an inner wall of the via, and forming a conductive material inside the insulating layer, where the conductive material may fill the via or only form the conductive material on a sidewall of the via, and in this embodiment, the conductive material fills the via, and the insulating layer also covers the upper surface of the substrate 10.

Referring to fig. 3 and 4, a dielectric material layer 200 and an interconnection structure penetrating the dielectric material layer 200 and connecting the through-silicon via structures 11 are formed on the substrate 10. In this embodiment, the dielectric material layer 200 is a multi-layer structure, and the forming method includes: sequentially forming each layer of dielectric material; and forming the conductive plug 22 through a single or multiple layers of the dielectric material; interconnect lines 210 are formed between the dielectric materials connecting the conductive plugs 22. In this embodiment, 3 layers of dielectric materials are shown, which are, from bottom to top, a first dielectric material 201, a second dielectric material 202, and a third dielectric material 203 in sequence, a conductive plug 22 penetrating through the dielectric materials is formed in the dielectric materials, the conductive plug 22 may penetrate through one layer of dielectric materials or two or more layers of dielectric materials, the layout of the conductive plug is set according to the specific requirements of circuit connection, interconnection lines 210 are formed at two ends of the conductive plug 22, and an interconnection pad 21 is formed above the tsv structure 11. The conductive plug 22 and the interconnection pad 21 are both of a conductive material such as aluminum, copper, gold, titanium, or tungsten. In the present embodiment, the interconnect structure includes the conductive plug 22, the interconnect line 210, and the interconnect pad 21. The materials of the first dielectric material 201, the second dielectric material 202 and the third dielectric material 203 include silicon oxide, silicon nitride and the like, and may be formed by a deposition process.

With continued reference to fig. 4, in the present embodiment, a recess is formed on the upper surface of the third dielectric material 203 to expose a portion of the surface of the uppermost interconnection pad, and the recess can provide a space for the subsequent conductive bump forming step. The uppermost interconnect pad is defined herein as the first pad 23. In other embodiments, the surface of the first pad 23 may be flush with or protrude from the upper surface of the dielectric layer.

Referring to fig. 5, an adhesive layer 32 is formed on the upper surface of the electrical interposer, and the adhesive layer 32 is used to adhere the chip to the upper surface of the electrical interposer in a later process. In this embodiment, the adhesive layer 32 includes a film-like dry film or a liquid dry film, and in other embodiments, other photosensitive adhesive materials may be selected. The film-shaped dry film is formed by coating a solvent-free photoresist on a polyester film base and then coating a polyethylene film; when in use, the polyethylene film is removed, the solvent-free photoresist is pressed on the base plate, and a pattern can be formed in the dry film through exposure and development treatment. The liquid dry film means that the components in the film-like dry film exist in a liquid state. The dry film is a permanent bonding film and has high bonding strength. The film-shaped dry film can be formed on the electric adapter plate in a film pasting mode, the liquid dry film is coated on the electric adapter plate through a spin coating process, and then the liquid dry film is cured. Through the dry film bonding chip and the electric adapter plate, on one hand, the dry film is a photoetching material, a required pattern can be formed through a semiconductor process, the process is simple, the process is compatible with the semiconductor process, and batch production can be realized. And the elastic modulus of the dry film is smaller, so that the dry film can be easily deformed and cannot be damaged when being subjected to thermal stress, and the bonding stress of the chip and the electric adapter plate is reduced.

In this embodiment, after the formation of the adhesive layer 32, the method further includes: patterning adhesive layer 32 forms an opening 33 in adhesive layer 32, where the depth of opening 33 is equal to or less than the thickness of adhesive layer 32. The area where the opening 33 is formed corresponds to the working area of the chip 30, and after the first chip is bonded by the post-process, a cavity is formed, and the cavity is used as a working cavity (e.g., a thermal isolation cavity) of the first chip. By forming the opening in the adhesive layer, process steps (which would otherwise be required to form the cavity when the chip is manufactured) can be saved when a cavity needs to be formed underneath the chip 30. In this embodiment, the opening 33 is used for thermal insulation, and therefore the depth of the opening 33 is not limited, and the opening may penetrate through the adhesive layer 32 (the opening depth is the same as the thickness of the adhesive layer 32) or may penetrate through only a part of the thickness of the adhesive layer 32 (the opening depth is smaller than the thickness of the adhesive layer 32). In other embodiments, if the depth of the opening needs to be defined, a suitable thickness is formed when forming the lithographically-bondable material. For the cavity type bulk acoustic resonator (fbar) and the surface acoustic resonator (SAW), a lower cavity is arranged below the main body resonance area, a sealing cover is formed above the main body resonance area, and an upper cavity is formed between the sealing cover and the main body resonance area. For firmly installed bulk acoustic wave resonators (SMRs), an upper cavity is also formed between the covers above the bulk acoustic wave resonators, and the cavity in this embodiment may be used as the upper cavity. For the infrared thermopile sensor, a heat insulation cavity for heat insulation is arranged below the functional region of the infrared thermopile sensor, and the cavity formed in the embodiment can be used as the heat insulation cavity. For the ultrasonic sensor, the membrane-shaped vibrating part is arranged in a suspended manner, the upper surface is used for receiving ultrasonic waves, the lower surface covers the cavity, and the cavity of the embodiment can be used as the lower cavity of the ultrasonic sensor.

In this embodiment, adhesive layer 32 is formed on the surface of the electrical interposer, and in another embodiment, adhesive layer 32 may also be formed on the surface of chip 30. The adhesive layer 32 is formed on the lower surface of the chip 30 without affecting the formation of the opening 33.

In an alternative embodiment, after the forming the adhesive layer, the method further includes: and patterning the bonding layer to form a fence structure at the periphery of the area where the conductive bump is preformed. The inner part enclosed by the enclosing wall structure is an area for forming the conductive bump, the enclosing wall structure is preferably a closed annular structure, and the enclosed space is cylindrical. When the adhesive layer is photoetched, the adhesive layer of the fence structure is reserved on the periphery of the area where the conductive bump is preformed, so that when the conductive bump is formed, the conductive bump with the expected shape can be formed due to the blocking of the fence, and the lateral overflow of the conductive bump is prevented.

In this embodiment, adhesive layer 32 is formed on the surface of the electrical interposer, and in another embodiment, adhesive layer 32 may also be formed on the surface of the chip.

In the present embodiment, the adhesive layer 32 is formed to have a thickness of 5 to 200 μm, such as 15 μm, 30 μm, 80 μm, 150 μm, or the like. And the projection of the adhesive layer 32 in the direction of the surface of the electrical interposer is centered on the center of the chip and covers at least 10% of the area of the chip. Specifically, the thickness of adhesive layer 32 is related to the height of the conductive bumps formed in the later processes. The correlation between the two is described in detail later when forming the conductive bump. In this embodiment, adhesive layer 32 covers at least 10% of the area of the chip, which covers the center of the chip. Because the plastic package layer is not easy to fill to the middle position of the chip (because the plastic package layer is far away from the edge of the chip) when the plastic package layer is formed in the subsequent process, the adhesive layer 32 of the scheme not only plays a role in adhesion, but also plays a role in sealing in advance, and the adhesive layer 32 and the plastic package layer in the subsequent process play a role in sealing the chip together. In an alternative scheme, the adhesive layer 32 covers the whole lower surface of the chip (except for the area where the second welding pad is located), so that when a plastic packaging layer is formed in a subsequent process, no gap is formed below the chip, the bonding strength is improved, and the yield is improved.

With continued reference to fig. 5, conductive bumps 24 are formed on the first pads 11 by an electroplating process. The material of the conductive bump comprises: any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium. The height of the conductive bump 24 is formed in relation to the height of the dry film and the structure of the chip, and when the second pad of the chip is flush with the lower surface of the chip, the height of the conductive bump 24 is approximately equal to the height of the dry film, so that the second pad 31 is in direct contact with the conductive bump 24 while the chip is attached to the dry film. When the second pad 31 is recessed downward with respect to the lower surface of the chip 20, the height of the conductive bump 24 is equal to the depth of the recess + the dry film thickness + the depth of the lower surface of the chip 20 recessed downward. In an alternative embodiment, the height of the conductive bump is 5-200 μm. Such as 10 μm, 50 μm, 100 μm.

The electroplating process includes electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), wherein the process parameters of ENEPIG or ENIG may be as described in table 1.

TABLE 1

Different chips are electrically connected with the circuit board through the electric adapter plate in the later process, and the conductive bump is formed between the chip and the electric adapter plate through the electroplating process, so that the problem of longitudinal multilayer stacking is solved, and the miniaturization of packaging is facilitated.

Before chemical plating, in order to better finish an electroplating process, the surface of the welding pad can be cleaned firstly to remove a natural oxidation layer on the surface of the welding pad and improve the surface wettability (wettabilities) of the welding pad; an activation process may then be performed to promote nucleation growth of the plating metal on the metal to be plated.

In order to better implement electroplating and form a relatively perfect conductive bump, the arrangement of the first bonding pad and the second bonding pad also needs to satisfy certain requirements, such as: the exposed area of the first welding pad is 5-200 square microns, and the welding pad can be in sufficient contact with the electroplating solution within the range, so that the contact between the conductive bump and the welding pad is prevented from being influenced due to insufficient contact between the welding pad and the electroplating solution, for example, the contact area is too small to influence the resistance, or the electric contact is not caused due to incapability of contacting; moreover, the electroplating efficiency can be ensured not to be reduced and the excessive surface can not be occupied because the contact area is not too large.

The cross section area of the formed conductive bump is larger than 10 square microns, so that the area occupied by the conductive bump is not too large, and the bonding strength between the conductive bump and the bonding pad can be ensured.

In an alternative, the material of the conductive bump is the same as that of the first pad, so that the conductive bump is more easily formed. Of course, the material of the first bonding pad may be different from that of the conductive bump, and in order to make it easier to form the conductive bump subsequently, a material layer may be formed on the first bonding pad first, and the material of the material layer is the same as that of the conductive bump, and the method of forming the material layer may be a deposition process.

Referring to fig. 6, at least one chip 30 is provided, and the lower surface of the chip 30 has a second pad 31. The chip 30 may be a chip made of a silicon wafer, or may be a chip made of another material. The chip 30 is fabricated using integrated circuit fabrication techniques, and may be a memory chip, a communication chip, a processor, or a logic chip. The second bonding pad 31 is located on the lower surface of the chip 30, and is used for electrically connecting the chip 30 with other devices. Specifically, the second Pad 31 may be a Pad (Pad). In this embodiment, the material of the second pad 31 includes any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium, and preferably, the material combination of the second pad and the conductive bump includes gold-gold, copper-copper, copper-tin, or gold-tin.

The plurality of first chips are same-function chips; the plurality of first chips at least comprise chips with two different functions; the first chip is a passive device or an active device.

The first chip may be a sensor module chip, an MEMS chip, a filter chip, a logic chip, a memory chip, a capacitor, an inductor, etc., and the capacitor may be an MLCC capacitor. The sensor module chip comprises a module chip for sensing at least one of a radio frequency signal, an infrared radiation signal, a visible light signal, a sound wave signal and an electromagnetic wave signal; the filter chip includes: at least one of the surface acoustic wave resonator and the bulk acoustic wave resonator. The first chip can be a packaged chip, and a plastic packaging process is not needed subsequently. The first chip may also be a through-die chip, or the first chip may also be a chip with a shielding layer on top.

In this embodiment, the second pad 31 and the conductive bump 24 are made of metal, and the second pad 31 and the conductive bump 24 are electrically connected through a thermal compression bonding process. Each second pad 31 and each conductive bump 24 are thermally and pressure bonded one by one; or a plurality of the second pads 31 and a plurality of the conductive bumps 24 are thermally and pressure bonded at the same time. By bonding the plurality of chips 30 to the electrical interposer first, the plurality of chips 30 are pre-aligned, so that the plurality of chips 30 and the conductive bumps 24 can be thermally compression bonded at the same time, which greatly improves the manufacturing efficiency compared with the sequential bonding of each chip 30 and each conductive bump 24.

In this embodiment, the area of the first pad 23 or the second pad 31 is 5 to 200 μm; the area of the overlapping region of the second pad 31 and the conductive bump 24 in the direction perpendicular to the surface of the electrical interposer is greater than half of the area of the second pad 31 to improve the bonding strength of the two, and in the alternative, the conductive bump 24 and the second pad 31 are opposite to each other, that is, in the direction perpendicular to the surface of the electrical interposer, the two are overlapped with each other to the greatest extent. In the alternative, the cross-sectional area of the conductive bump is greater than 10 square microns to ensure structural strength.

In this embodiment, a plurality of chips 30 are bonded one by one on the surface of the electrical interposer, in another embodiment, the surface of the chip 30 having the second pads 31 is a front surface, and the surface opposite to the front surface is a back surface, and before the chip 30 is bonded to the electrical interposer, the back surface of the chip 30 is temporarily bonded to the substrate; and bonding the chip on the electric adapter plate, and then debonding the substrate. The substrate may be a carrier wafer for temporarily fixing the plurality of chips 30, and the substrate is further used for supporting the chips 30 during the bonding process of the chips 30 and the electrical interposer, so as to improve the reliability of the bonding. The chip 30 is temporarily bonded to the substrate by an adhesive layer or electrostatic bonding. Electrostatic bonding technology is a method of achieving bonding without any adhesive. In the bonding process, the chip to be bonded and the substrate are respectively connected with different electrodes, electric charges are formed on the surfaces of the chip and the substrate under the action of voltage, and the electric charges on the surfaces of the chip and the substrate are different, so that a larger electrostatic attraction is generated in the bonding process of the chip and the substrate, and the physical connection of the chip and the substrate is realized. Accordingly, during the debonding process, the substrate may be separated from the chip by chemical or mechanical peeling.

Referring to fig. 7, in this embodiment, after bonding the chip 20, the method further includes: and forming a plastic packaging layer 40, wherein the plastic packaging layer 40 is at least filled between the adjacent chips. In other embodiments, the molding layer may not be formed. In this embodiment, the package layer 40 covers the surface of the electrical interposer and the chips 30, that is, the package layer 40 fills the gaps between the chips 30 and covers the chips 30, and the plastic package layer seals the chips, thereby better isolating air and moisture and further improving the package effect. Specifically, the encapsulation layer 40 may be formed through an injection molding process. The filling performance of the injection molding process is good, and the injection molding agent can be well filled among the plurality of chips 30, so that the chips 30 have a good packaging effect. In other embodiments, other processes may be used to form the encapsulation layer. In addition, the upper surface of the chip can be exposed outside the plastic package layer according to different performances of the chip.

Referring to fig. 7, in this embodiment, after the molding layer 40 is formed, the method further includes: thinning the lower surface of the substrate 10 to expose the through silicon via structure 11, and forming a solder ball 50 connected to the through silicon via structure 11. The lower surface of the substrate 10 may be thinned by a grinding process to expose the lower end of the tsv structure 11, and since the lower end of the tsv structure 11 has an insulating layer, the insulating layer also needs to be removed, and then the solder ball 50 may be formed by an electroplating process or a deposition process.

In this embodiment, the electrical interposer includes a substrate 10, a through silicon via structure 11 disposed in the substrate 10, a plurality of dielectric materials over the substrate 10, and a conductive plug 22, an interconnection pad 21, a first pad 23, and a solder ball 50 disposed in the dielectric materials. The overall thickness of the electrical interposer is 5-200 microns, such as 10 microns, 20 microns, 50 microns, 100 microns, and the like. After the above steps are completed, the above structure needs to be electrically connected to the PCB, and the PCB is provided with a plurality of electrical connection ends (such as pads) with fixed positions.

The thickness of the electric adapter plate is reduced by thinning the back surface of the substrate 10, so that the heat dissipation effect of the electric adapter plate is improved; in addition, the thickness of the electric adapter plate is reduced, so that the whole thickness of the packaged structure is reduced, and the performance of the packaged structure is improved. In this embodiment, the thinning process may be one or more of a back grinding process, a Chemical Mechanical Polishing (CMP) process, and a wet etching process.

In order to effectively control the stop position of the thinning process, a deep trench isolation structure is typically formed in the substrate to define the stop position, such that the thinning process stops at the bottom of the deep trench isolation structure. In another embodiment, a stop region may be formed in the substrate by using neutral dopant ions (e.g., one or both of oxygen ions and nitrogen ions) during the process of manufacturing the electrical interposer, so that the thinning process is stopped at the bottom of the stop region. In other embodiments, when the base is a silicon-on-insulator substrate or a germanium-on-insulator substrate, the bottom substrate layer of the semiconductor substrate may be thinned, so that the bottom substrate layer can be stopped at the bottom of the insulator layer.

Referring to fig. 8 and 9, in one embodiment, after bonding the chip 30 (after fig. 6), the method further includes: providing a cover substrate 60, wherein the first surface of the cover substrate 60 comprises a cavity, bonding the first surface of the cover substrate 60 and the electrical interposer, and enabling the cavity to cover at least a part of the chip. The material of the capping substrate 60 may be: the material may be a semiconductor material such as silicon, germanium, silicon carbide, gallium arsenide, or indium gallium, or may be a dielectric material. Referring to fig. 8, the cavity may be large, and one cavity may cover a plurality of chips 30 at the same time. Referring to fig. 9, the cover substrate includes a plurality of sub-cavities, each of which accommodates one or more chips 30. In an alternative embodiment, one cavity of the cover substrate may also accommodate only a portion of one chip, for example, for a bulk acoustic wave resonator or a surface acoustic wave resonator or an infrared thermopile sensor, the chip needs to be formed with a cavity structure, and the cavity structure corresponds to a functional region of the chip structure, and the whole chip is not included in the cavity. For example, for a bulk acoustic wave resonator or a surface acoustic wave resonator or an infrared thermopile sensor, the chip needs to be formed with a cavity structure, and the cavity structure corresponds to a functional region of the chip structure, and the entire chip is not included in the cavity. For example, for a bulk acoustic wave resonator (BAW), a surface acoustic wave resonator (SAW) and a firmly-arranged bulk acoustic wave resonator (SMR), an upper cavity is arranged above a main body resonance area, the cavity in the present embodiment can be used as the upper cavity, for an infrared thermopile sensor, a heat insulation cavity for heat insulation is arranged below a functional area of the infrared thermopile sensor, the cavity formed in the present embodiment can be used as the heat insulation cavity, for an ultrasonic sensor, a film-shaped vibration portion is arranged in a suspended manner, the upper surface is used for receiving ultrasonic waves, and the lower surface covers the cavity, and the cavity in the present embodiment can be used as a lower cavity of the ultrasonic sensor.

In an optional embodiment, after the cover substrate is bonded to the electrical interposer, the formed cavity is a sealed cavity, which can prevent the external environment from contaminating devices (moisture, dust, grease, etc.) in the cavity. In one embodiment, an electrical connection structure is formed on the cover substrate to electrically connect the chip.

Example 2

This embodiment is different from embodiment 1 in the method of forming the electrical interposer. Fig. 10 to 13 are schematic structural diagrams illustrating different steps of the method for manufacturing a wafer level package structure according to the present embodiment, and please refer to fig. 10 to 13 for briefly explaining the steps.

Referring to fig. 10, a substrate 10 is provided, a dielectric material layer 200 and a conductive plug 22 penetrating through the dielectric material layer 200 are formed on the substrate 10, and the first pad 23 connected to the conductive plug 22 and exposed on the top surface of the dielectric material layer 200 is provided. In this embodiment, the dielectric material layer 200, the structure, the material and the forming method of the conductive plug 22 and the first pad 23 penetrating through the dielectric material layer 200 refer to embodiment 1, which is not described herein again, and it is to be noted that although the formation of the through-silicon via structure is not required in this embodiment, a solder ball needs to be formed at a later stage of the process, so that the interconnection pad 21 is formed on the upper surface of the substrate 10 for connecting the solder ball.

Referring to fig. 11, the conductive bumps 24 are formed by the method of embodiment 1, the chips 30 are bonded to the upper surface of the electrical interposer, and a molding layer 40 is formed on the upper surface of the electrical interposer, and the molding layer 40 seals the conductive bumps 24 and fills the gaps between the chips 30. The details of the above steps are referred to in example 1.

Referring to fig. 12, the lower surface of the substrate is thinned, and a through-silicon via structure 11 is formed from the thinned lower surface, the upper end of the through-silicon via structure 11 is connected to the interconnection pad 21, and the lower end is formed with a solder ball 50. Instead of forming the through-silicon via structure, referring to fig. 13, the substrate may be removed to expose the lower surface of the underlying interconnection pad 21, and the solder ball 50 may be formed on the lower surface of the interconnection pad 21.

In another embodiment, the structure of the electrical interposer is the same as that in embodiment 1, but the formation method is different, the electrical interposer includes a substrate and a dielectric material layer located on an upper surface of the substrate, an interconnection structure is formed in the dielectric material layer, the interconnection structure is electrically connected to the first pad, after the chip is bonded, a through silicon via structure is formed from a lower surface of the substrate, a solder ball connected to the through silicon via structure is formed on the lower surface of the substrate, and the other end of the through silicon via structure is electrically connected to the interconnection structure.

Each layer of dielectric material of the electrical interposer of the above embodiments comprises an insulating material such as silicon dioxide, silicon nitride, or silicon oxynitride, which is formed by a semiconductor deposition process. The interconnection structure, such as an interconnection line and a conductive plug, in the dielectric material layer are also formed by semiconductor deposition and etching processes, and the interconnection structure is made of a conductive material, such as copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium. For an optional electrical interposer comprising a substrate, the substrate material is typically a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors.

It should be noted that the electrical interposer of the present invention is formed on a substrate, the substrate is a wafer, and the electrical interposer is wafer level.

According to the invention, different chips are electrically connected with the circuit board through the electric adapter plate, and the conductive bump is formed between the chip and the electric adapter plate through an electroplating process, so that the problem of longitudinal multilayer stacking is solved, and the miniaturization of packaging is facilitated.

Furthermore, the electric adapter plate can be a dielectric layer, the solder balls are positioned on the lower surface of the dielectric layer, the lower part of the dielectric layer can also comprise a substrate, a silicon through hole structure is formed in the substrate, and the solder balls are positioned on the lower surface of the substrate. The through silicon via structure can be formed at different process stages according to actual conditions.

It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, in the case of embodiment 2, since it is substantially similar to embodiment 1, the description is relatively simple, and for the relevant points, reference may be made to the partial description of embodiment 1.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A wafer level packaging method, comprising:

forming a conductive bump on the first pad by an electroplating process;

2. The wafer level packaging method of claim 1, wherein the method of bonding the chip to the electrical interposer comprises:

forming a photoetching bonding material on the lower surface of the chip or the upper surface of the electric adapter plate, wherein the photoetching bonding material avoids the second welding pad and the area where the conductive bump is located; patterning the lithographically-bondable material to form the opening, wherein the depth of the opening is equal to or less than the thickness of the lithographically-bondable material; bonding the chip on the electrical interposer by the lithographically-operable bonding material.

3. The wafer level packaging method of claim 2, wherein the lithographically bondable material comprises: film-like dry film or liquid dry film.

4. The wafer-level packaging method according to claim 1, wherein the electroplating process comprises: chemical plating palladium and gold leaching, wherein the chemical nickel time is 30-50 minutes, the chemical gold time is 4-40 minutes, and the chemical palladium time is 7-32 minutes; or the like, or, alternatively,

the electroplating process comprises chemical nickel and gold, wherein the chemical nickel time is 30-50 minutes, and the chemical gold time is 4-40 minutes.

5. The wafer level packaging method of claim 1, wherein the area of the first pad or the second pad is 5-200 μm; and/or the cross-sectional area of the conductive bump is greater than 10 square microns.

6. The wafer level packaging method as claimed in claim 1, wherein the material of the second pad and the conductive bump is metal, and the second pad and the conductive bump are electrically connected by a thermocompression bonding process.

7. The wafer level packaging method as claimed in claim 6, wherein each of the second pads is thermocompression bonded with each of the conductive bumps one by one; or the plurality of second welding pads and the plurality of conductive bumps are subjected to hot-press bonding at the same time.

8. The wafer level packaging method as claimed in claim 1, wherein the material combination of the second bonding pad and the conductive bump comprises gold-gold, copper-copper, copper-tin or gold-tin.

9. The wafer level packaging method as claimed in claim 1, wherein the thickness of the adhesive layer is formed to be 5-200 μm, and the projection of the adhesive layer in the direction of the surface of the electrical interposer is centered on the center of the chip and covers at least 10% of the area of the chip.

10. The wafer level packaging method as claimed in claim 1, wherein the area of the overlapping region of the second pad and the conductive bump in the direction perpendicular to the surface of the electrical interposer is greater than half of the area of the second pad.

11. The wafer level packaging method of claim 1, wherein forming the electrical interposer comprises:

providing a substrate, forming a dielectric material layer and an interconnection structure in the dielectric material layer on the substrate, and forming a first welding pad which is connected with the interconnection structure and exposed to the top surface of the dielectric material layer; after the chip is bonded, removing the substrate, and forming a solder ball connected with the interconnection structure on the lower surface of the dielectric material layer;

or the like, or, alternatively,

providing a substrate, forming a through silicon via structure in the inner part of the upper surface of the substrate, and forming a dielectric material layer and an interconnection structure which is positioned in the dielectric material layer and is connected with the through silicon via structure on the substrate; thinning the lower surface of the substrate after bonding the chip to expose the through silicon via structure and form a solder ball connected with the through silicon via structure;

or the like, or, alternatively,

the electric adapter plate comprises a substrate and a medium material layer positioned on the upper surface of the substrate, an interconnection structure is formed in the medium material layer and electrically connected with the first welding pad, a silicon through hole structure is formed on the lower surface of the substrate after the chip is bonded, a welding ball connected with the silicon through hole structure is formed on the lower surface of the substrate, and the other end of the silicon through hole structure is electrically connected with the interconnection structure.

12. The wafer level packaging method according to claim 1, wherein the dielectric material layer is a multilayer structure, the method comprising:

sequentially forming each layer of dielectric material; and forming the conductive plug through a single layer or multiple layers of the dielectric material; and forming an interconnection line positioned at two ends of the conductive plug, wherein the interconnection structure comprises the conductive plug and the interconnection line.

13. The wafer level packaging method according to claim 1, wherein the side of the chip having the second bonding pad is a front side, and the side opposite to the front side is a back side, and the back side of the chip is temporarily bonded to the substrate before the chip is bonded to the electrical interposer;

and bonding the chip on the electric adapter plate, and then debonding the substrate.

14. The wafer level packaging method as claimed in claim 13, wherein the chip is temporarily bonded on the substrate by an adhesive layer or electrostatic bonding.

15. The wafer-level packaging method of claim 1, wherein after bonding the chips, providing a cover substrate, the first surface of the cover substrate comprising a cavity, bonding the first surface of the cover substrate to the device wafer such that the cavity covers at least a portion of the chips.

16. The wafer level packaging method of claim 15, further comprising: and forming an electric connection structure on the cover substrate to lead out the electrical property of the chip.

17. The wafer level packaging method of claim 1, wherein after forming the adhesive layer, the method further comprises:

and patterning the bonding layer to form a fence structure at the periphery of the area where the conductive bump is preformed.