CN114787990A - Chip package and manufacturing method thereof - Google Patents

Chip package and manufacturing method thereof Download PDF

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Publication number
CN114787990A
CN114787990A CN201980102809.6A CN201980102809A CN114787990A CN 114787990 A CN114787990 A CN 114787990A CN 201980102809 A CN201980102809 A CN 201980102809A CN 114787990 A CN114787990 A CN 114787990A
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CN
China
Prior art keywords
layer
chip
substrate
thermal interface
interface material
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Pending
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CN201980102809.6A
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Chinese (zh)
Inventor
胡骁
张弛
蒋尚轩
郑见涛
赵南
任亦纬
蔡树杰
吴维哲
邹坤
黄文濬
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN114787990A publication Critical patent/CN114787990A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Abstract

A chip package and a manufacturing method thereof relate to the technical field of chip package, and are used for reducing deformation of a radiating fin (40) caused by deformation of a substrate (10) and further preventing a thermal interface material layer (30) from cracking. The chip package comprises a substrate (10), a chip (20), a thermal interface material layer (30) and a heat sink (40) which are sequentially stacked and arranged on a first surface of the substrate (10), and a reinforcing ring (50) arranged on the first surface; the stiffener ring (50) surrounds the chip (20) with a space between the chip (20), the thermal interface material layer (30), and the heat sink (40). The manufacturing method of the chip package comprises the following steps: packaging a chip (20) on a substrate (10), forming a thermal interface material layer (30) on the chip (20); forming a heat sink (40) on the layer of thermal interface material (30); a reinforcing ring (50) is formed on a substrate (10), the reinforcing ring (50) surrounds a chip (20), and a space is provided between the reinforcing ring (50) and the chip (20), between the thermal interface material layer (30), and between the reinforcing ring (50) and a heat sink (40).

Description

Chip package and manufacturing method thereof Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip package and a method for manufacturing the same.
Background
With the increase of the demand of artificial intelligence and high-speed data communication, the power consumption of the chip adopted by the system is increased sharply, so that a great deal of heat can be generated when the chip works, and the performance and the service life of the chip can be influenced if the heat cannot be discharged outside the chip in time.
At present, a heat sink arranged on a chip is generally used for discharging heat generated during the operation of the chip to the outside of the chip; in addition, in order to further improve the heat dissipation performance of the chip, a thermal interface material layer is arranged between the heat sink and the chip, and the thermal interface material layer is used for reducing the contact thermal resistance between the chip and the heat sink.
However, the substrate for carrying the chip is prone to warp deformation, the deformation of the substrate may cause deformation of the heat sink, which may cause cracks in the thermal interface material layer, and after the cracks occur, the heat conduction path of the thermal interface material layer is interrupted, which may further increase the thermal contact resistance between the chip and the heat sink, and decrease the heat dissipation performance of the chip.
Disclosure of Invention
The embodiment of the application provides a chip package and a manufacturing method thereof, which are used for reducing deformation of a radiating fin caused by deformation of a substrate and further preventing a thermal interface material layer from cracking.
In a first aspect, an embodiment of the present application provides a chip package, where the chip package includes a substrate, a chip, a thermal interface material layer, a heat sink, and a reinforcement ring, where the chip, the thermal interface material layer, and the heat sink are sequentially stacked and disposed on a first surface of the substrate, and the chip is located on a bottom layer and is in contact with the first surface of the substrate; the reinforcing ring is arranged on the first surface of the substrate and surrounds the chip, and intervals are arranged among the reinforcing ring, the chip, the thermal interface material layer and the radiating fin.
In the chip package with the structure, the strength of the substrate can be enhanced by utilizing the reinforcing ring, the deformation resistance of the substrate is improved, and if the substrate deforms, the reinforcing ring is independently arranged on the periphery of the chip and is not in contact with the chip, the thermal interface material layer and the radiating fin, so that the deformation of the substrate cannot be transmitted to the thermal interface material layer through the radiating fin, cracks are prevented from occurring in the thermal interface material layer or on the upper interface and the lower interface of the thermal interface material layer, the heat conduction performance of the thermal interface material layer is ensured, and the heat radiation performance of the low chip can be further ensured. In addition, due to the stress generated by expansion with heat and contraction with cold during and after the operation of the chip, the stress can be transmitted to the substrate, and the influence of the stress on the substrate can be reduced by utilizing the reinforcing ring, so that the risk of deformation of the substrate due to the stress is reduced.
In one possible implementation, the stiffening ring is an annular protrusion. By adopting the design, the strength of the substrate can be enhanced by utilizing the reinforcing ring, and the deformation resistance of the substrate is improved.
In one possible implementation, the heat sink is a flexible heat sink.
The flexible radiating fin is adopted, so that the radiating fin has the deformability, and therefore, the deformation of the radiating fin can be used for absorbing stress, protecting the integrity of the thermal interface material layer and ensuring the heat conducting performance of the thermal interface material layer. In addition, the deformation of the radiating fin is utilized, so that the radiating fin can deform along with the chip and the thermal interface material layer, the tearing force of the radiating fin and the chip on the thermal interface material layer is reduced, the thermal interface material layer is prevented from cracking, and the heat conducting performance of the thermal interface material layer is ensured.
In one possible implementation, the chip includes a bare chip disposed on the substrate, and a packaging layer covering a side surface of the bare chip, where a surface of the packaging layer facing the thermal interface material layer is flush with a surface of the bare chip facing the thermal interface material layer.
By the design, the packaging layer wraps around the chip, so that the bearing capacity of the chip can be improved, and the risk of chip fracture caused by falling in the packaging and transporting process is reduced.
In a further possible implementation manner, the packaging layer comprises a box dam plastic packaging layer and a filling plastic packaging layer embedded in the box dam plastic packaging layer.
In another possible implementation, the thermal interface material layer includes a first metal layer bonded to the chip, a second metal layer bonded to the heat sink, and a heat conducting layer located between the first metal layer and the second metal layer, and the heat conducting layers are bonded to the first metal layer and the second metal layer, respectively.
By the design, the bonding strength between the top surface of the chip and the metal particles in the heat conduction layer can be improved by the first metal layer, the bonding strength between the bottom surface of the radiating fin and the metal particles in the heat conduction layer can be improved by the second metal layer, and in addition, air gaps in the surface of the chip facing the radiating fin and the surface of the radiating fin facing the chip can be filled by the first metal layer and the second metal layer, so that the thermal contact resistance between the two surfaces is reduced, and the radiating performance of the chip is improved.
In one possible implementation, the heat conductive layer includes a substrate layer and nanoscale metal particles uniformly filled in the substrate layer.
In a further possible implementation manner, the substrate layer is a resin layer, and the metal particles include one or more of silver powder, tin powder, aluminum powder, zinc oxide powder, and aluminum oxide powder.
In a possible implementation manner, the chip package further includes an annular bonding layer, the annular bonding layer is annularly disposed on the circumferential edge of the thermal interface material layer, the first surface of the annular bonding layer is bonded to the surface of the chip far away from the substrate, and the second surface of the annular bonding layer is bonded to the surface of the heat sink close to the substrate.
The chip package with the structure can connect the chip and the radiating fin by utilizing the annular bonding layer, and the annular bonding layer can share the connecting force between the chip and the radiating fin for the thermal interface material layer, so that the connecting force borne by the thermal interface material layer is reduced, namely, the tensile crack force borne by the thermal interface material layer, which is pulled and cracked, is reduced, and the heat conducting performance of the thermal interface material layer can be ensured.
In another possible implementation manner, the chip package further includes an annular bonding layer, the annular bonding layer is annularly disposed on a circumferential edge of the heat conductive layer, a first surface of the annular bonding layer is bonded to the first metal layer, and a second surface of the annular bonding layer is bonded to the second metal layer.
The annular bonding layer is arranged between the first metal layer and the second metal layer, and the first metal layer and the second metal layer can be connected by the annular bonding layer, so that the tensile crack force of the heat conduction layer is reduced, and the heat conduction performance of the heat conduction layer is ensured.
In a further possible implementation, the material of the annular bonding layer comprises epoxy, silicone or acrylic.
In a further possible implementation manner, the first metal layer includes a first adhesion layer and a first sintering layer, the first adhesion layer is connected with the chip, and the first sintering layer is connected with the heat conduction layer; the second metal layer comprises a second bonding layer and a second sintering layer, the second bonding layer is connected with the radiating fin, and the second sintering layer is connected with the heat conducting layer.
In a further possible implementation, the first metal layer further includes a first buffer layer between the first adhesion layer and the first sintering layer; the second metal layer further includes a second buffer layer between the second adhesion layer and the second sintering layer.
In a further possible implementation manner, the material of the first adhesion layer is titanium, chromium, nickel or nickel-vanadium alloy, the material of the first buffer layer is aluminum, copper, nickel or nickel-vanadium alloy, and the material of the first sintering layer is gold, silver or copper; the second adhesion layer is made of titanium, chromium, nickel or nickel-vanadium alloy, the second buffer layer is made of aluminum, copper, nickel or nickel-vanadium alloy, and the second sintering layer is made of gold, silver or copper.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a chip package, where the method includes: mounting a chip on a first surface of a substrate; forming a layer of thermal interface material on a surface of the chip remote from the substrate; forming a heat sink on a surface of the thermal interface material layer away from the chip; forming a stiffener ring on the first surface of the substrate, the stiffener ring surrounding the chip with a space between the stiffener ring and the chip, the thermal interface material layer, and the heat sink.
In the chip package manufactured by the manufacturing method, the strength of the substrate can be enhanced by the reinforcing ring, the deformation resistance of the substrate is improved, and if the substrate deforms, the reinforcing ring is independently arranged on the periphery of the chip and is not in contact with the chip, the thermal interface material layer and the radiating fin, so that the deformation of the substrate is not transmitted to the thermal interface material layer through the radiating fin, cracks are prevented from occurring in the thermal interface material layer or on the upper interface and the lower interface of the thermal interface material layer, and the heat conducting performance of the thermal interface material layer is ensured. In addition, due to the stress generated by expansion with heat and contraction with cold during and after the operation of the chip, the stress can be transmitted to the substrate, and the influence of the stress on the substrate can be reduced by utilizing the reinforcing ring, so that the risk of deformation of the substrate due to the stress is reduced.
In one possible implementation, the step of mounting the chip on the first surface of the substrate includes: bonding a bare chip on the first surface of the substrate by means of underfill; form the packaging layer on the first surface of base plate, the packaging layer covers the side of naked chip, just the packaging layer is kept away from the surface of base plate with the naked chip is kept away from the surface parallel and level of base plate.
In a further possible implementation, the step of forming an encapsulation layer on the first surface of the substrate includes: forming a dam plastic packaging material on the first surface of the substrate, wherein the dam plastic packaging material surrounds the bare chip, and a gap is formed between the dam plastic packaging material and the bare chip; filling plastic packaging materials are arranged in the interval, and the filling plastic packaging materials cover the side face of the bare chip and the surface far away from the substrate; solidifying the box dam plastic package material and the filling plastic package material to respectively form a box dam plastic package layer and a filling plastic package layer; grind box dam plastic-sealed layer and packing plastic-sealed layer make box dam plastic-sealed layer keeps away from the surface of base plate and packing plastic-sealed layer keep away from the surface of base plate with the bare chip is kept away from the surface parallel and level of base plate.
In one possible implementation, the step of forming the thermal interface material layer on the surface of the chip away from the substrate includes: forming a first metal layer on the surface of the chip far away from the substrate; forming a heat conduction layer on the surface of the first metal layer far away from the chip, wherein the heat conduction layer comprises a base material layer and nanoscale metal particles uniformly filled in the base material layer; a second metal layer is formed on a surface of the thermally conductive layer remote from the first metal layer.
In a further possible implementation manner, after the step of forming the heat conduction layer on the surface of the first metal layer far away from the chip and before the step of forming the second metal layer on the surface of the heat conduction layer far away from the first metal layer, an annular bonding layer is further formed on the surface of the first metal layer far away from the chip, and the annular bonding layer wraps the side face of the heat conduction layer.
Drawings
Fig. 1 is a cross-sectional view of a chip package provided in an embodiment of the present application;
fig. 2 is a cross-sectional view of another chip package provided by an embodiment of the present application;
fig. 3 is a cross-sectional view of another chip package provided by an embodiment of the present application;
fig. 4 is a flowchart illustrating a manufacturing process of a chip package according to an embodiment of the present disclosure;
fig. 5 is a cross-sectional view of a bare chip disposed on a substrate;
FIG. 6 is a cross-sectional view of a dam molding layer formed on a substrate;
FIG. 7 is a top view of a dam molding layer formed on a substrate;
FIG. 8 is a cross-sectional view of a filled plastic encapsulation layer formed on a substrate;
FIG. 9 is a top view of a filled molding layer formed on a substrate;
FIG. 10 is a cross-sectional view of the dam and the filler mold layer after grinding;
FIG. 11 is a top view of the dam and the underfill encapsulant layer after grinding;
FIG. 12 is a cross-sectional view of an encapsulation layer formed on a substrate;
fig. 13 is a cross-sectional view of a first metal layer formed on a chip;
FIG. 14 is a cross-sectional view of a layer of thermal interface material and a second metal layer formed on a first metal layer;
fig. 15 is a cross-sectional view of a heat sink formed on the second metal layer.
Description of the reference numerals:
10: a substrate; 20: a chip; 21: a bare chip;
22: a dam plastic packaging layer; 23: filling a plastic packaging layer; 30: a layer of thermal interface material;
31: a first metal layer; 32: a heat conductive layer; 33: a second metal layer;
40: a heat sink; 50: a reinforcement ring; 60: an annular bonding layer.
Detailed Description
In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
In order to alleviate the problem that the heat sink deforms due to the deformation of the substrate and further causes cracks in the thermal interface material layer, in the chip package provided in the embodiment of the present application, the substrate is separately provided with the stiffener ring, and the stiffener ring is spaced from the chip on the substrate and the thermal interface material layer and the heat sink on the chip. The reinforcing ring can be used for enhancing the deformation resistance of the substrate, the influence of the deformation of the substrate on the chip in the reinforcing ring is reduced, and meanwhile, the reinforcing ring is not in contact with the radiating fins and the thermal interface material layer, so that the deformation of the substrate or the stress in the substrate cannot be transmitted to the thermal interface material layer through the radiating fins, cracks are prevented from occurring in the thermal interface material layer or on the upper interface and the lower interface of the thermal interface material layer, and the heat conduction performance of the thermal interface material layer and the heat radiation performance of the chip are ensured.
Referring to fig. 1, a chip package according to an embodiment of the present disclosure includes a substrate 10, a chip 20, a Thermal Interface Material (TIM) layer 30, a heat spreader 40, and a stiffener ring 50, where the chip 20 is attached to a first surface of the substrate 10, the heat spreader 40 is disposed above the chip 20, the Thermal Interface material layer 30 is located between the chip 20 and the heat spreader 40, a lower Interface of the Thermal Interface material layer 30 is bonded to a top surface of the chip 20, and an upper Interface of the Thermal Interface material layer 30 is bonded to a bottom surface of the heat spreader 40; the stiffener ring 50 is disposed on the substrate 10, and the stiffener ring 50 surrounds the chip 20 with a space between the chip 20, the thermal interface material layer 30, and the heat sink 40.
It is understood that the first surface of the substrate 10 is the upper surface of the substrate 10 in fig. 1; the upper interface of the thermal interface material layer 30 is the upper surface of the thermal interface material layer, and the lower interface is the lower surface of the thermal interface material layer; the top surface of the chip 20 refers to the surface of the chip 20 facing the heat sink 40, and is the upper surface of the chip 20 shown in fig. 1; the bottom surface of the heat sink 40 is the surface of the heat sink 4-0 facing the chip 20, and is the lower surface of the heat sink 40 as shown in fig. 1.
In the embodiment of the present application, the heat generated by the chip 20 can be transferred to the heat sink 40 through the thermal interface material layer 30, so that the heat is dissipated out of the chip 20 through the heat sink 40, thereby completing the heat dissipation of the chip 20. The thermal interface material layer 30 can fill an air gap in the junction surface between the chip 20 and the heat sink 40, reduce the contact thermal resistance between the chip 20 and the heat sink 40, and improve the heat dissipation performance of the chip 20. The reinforcing ring 50 can reinforce the strength of the substrate 10, improve the deformation resistance of the substrate 10, and if the substrate 10 deforms, since the reinforcing ring 50 is separately disposed at the periphery of the chip 20 and does not contact with the chip 20, the thermal interface material layer 30 and the heat sink 40, the substrate 10 does not deform and is not transferred to the thermal interface material layer 30 through the heat sink 40, cracks are prevented from occurring in the thermal interface material layer 30 or in the upper and lower interfaces thereof, and the heat conductivity of the thermal interface material layer 30 is ensured. In addition, the influence of the deformation of the substrate 10 on the mounting of the chip 20 can be reduced.
The substrate 10 may be a ceramic substrate, an organic substrate or a silicon substrate, the substrate 10 is a bridge connecting the chip 20 with an external circuit, and the substrate 10 has functions including but not limited to: signal transmission between the chip 20 and the outside is realized, and the chip 20 is protected, supported and radiated.
The number of the chips 20 is not limited, one chip 20 may be packaged on the substrate 10, or two or more chips 20 may be packaged on the substrate, when at least two chips 20 are packaged on the substrate 10, the chips 20 are located on the substrate 10 in the space surrounded by the reinforcement ring 50, and one heat sink 40 may be separately disposed above each chip 20, or the same heat sink 40 may be shared.
There are various ways of mounting the Chip 20 on the substrate 10, for example, mounting is performed by a Flip Chip Ball Grid Array (FCBGA). The chip 20 includes a bare chip (die) 21 and a package layer coated on an outer side surface of the bare chip 21, wherein the bare chip 21 is connected to the substrate 10 through a solder ball, and an adhesive is filled between the bare chip 21 and the substrate 10, which may be referred to as an Underfill (underwile). The top surface of the bare chip 21 in fig. 1 is the upper surface of the bare chip 21, that is, the surface of the bare chip 20 away from the substrate 10, and the top surface of the die 20 is the surface of the die 20 away from the substrate 10, and includes the top surface of the bare chip 21 and the top surface of the package layer.
The packaging layer is formed on the substrate 10 and wraps the side surface of the bare chip 21, and the packaging layer is used for preventing external moisture, solvent, liquid and the like from entering the chip 20, performing thermal diffusion on heat generated by the chip 20 and increasing the heat dissipation area of the chip 20; in addition, the heat sink 40 and the packaging layer wrapped on the side surface of the chip 20 can improve the pressure bearing capacity of the chip 20 and reduce the risk of the chip 20 breaking caused by falling in the packaging and transporting process.
The material of the encapsulation layer can be epoxy molding compound, silicon rubber molding compound or polyimide molding compound, in this embodiment, the encapsulation layer is epoxy molding compound, and the epoxy molding compound is thermosetting material, generally including epoxy resin, hardener, filling machine and additive. The encapsulation layer can be formed by dispensing or injection molding. When a packaging layer is formed by adopting a dispensing manner, a circle of dam plastic packaging material is usually formed on the substrate 10 along the periphery of the bare chip 21, a gap is formed between the dam plastic packaging material and the bare chip 21, then a filling plastic packaging material is added into the gap between the dam plastic packaging material and the bare chip 21, then the dam plastic packaging material and the filling plastic packaging material are cured, a dam plastic packaging layer 22 and a filling plastic packaging layer 23 embedded in the dam packaging layer 22 are respectively formed after curing, and the filling plastic packaging layer 23 wraps the side surface of the bare chip 21; the dam plastic package layer 22 and the filling plastic package layer 23 constitute a package layer.
The layer of thermal interface material 30 is disposed between the chip 20 and the heat spreader 40 and is then sinter bonded to the chip 20 and the heat spreader 40, respectively. The lower interface of the thermal interface material layer 30 is bonded to the top surface of the chip 20 to exhaust air from the air gap on the top surface of the chip 20; the upper interface of the layer of thermal interface material 30 engages the bottom surface of the heat sink 40 to expel air from the air gap at the bottom surface of the heat sink 40. The thermal interface material layer 30 may fill the air gaps at the top surface of the chip 20 and the bottom surface of the heat sink 40 under a lower pressure condition, reducing air thermal resistance, and thus may reduce contact thermal resistance between the top surface of the chip 20 and the bottom surface of the heat sink 40.
The thermal interface material layer 30 includes a first metal layer 31, a second metal layer 33, and a heat conducting layer 32 located between the first metal layer 31 and the second metal layer 33, wherein the heat conducting layer 32 generally includes a substrate layer and micron-sized or nano-sized metal particles uniformly filled in the substrate layer, the substrate layer may be a resin layer, and the metal particles include one or more of silver powder, tin powder, aluminum powder, zinc oxide powder, and aluminum oxide powder, for example, in this embodiment, the metal particles are nano-sized silver powder, and the nano-sized silver powder has a very large surface energy, can be melted and sintered at a relatively low temperature, and has a low thermal resistance and a relatively good heat conducting property, so that a relatively good heat conducting path can be formed in the thermal interface material layer 30.
The first metal layer 31 is bonded to the chip 20, that is, the first metal layer 31 is located on the top surface of the bare chip 21 and the top surface of the package layer, for enabling the chip 20 to be sintered with the metal particles in the heat conduction layer 32, and in more detail, the first metal layer 31 may be contact-diffused into the air gaps on the top surface and the top surface of the chip 20 and into the heat conduction layer 32, so that the first metal layer 31 can form a sintering structure with the top surface of the chip 20 and a sintering structure with the metal particles in the heat conduction layer 32, thereby ensuring the bonding strength between the first metal layer 31 and the chip 20 and reducing the contact thermal resistance between the first metal layer 31 and the chip 20.
Illustratively, the first metal layer 31 includes a first adhesion layer and a first sintering layer, the first adhesion layer is sintered with the top surface of the bare chip 21 and the top surface of the encapsulation layer, and the material of the first adhesion layer may be titanium, chromium, nickel or nickel-vanadium alloy; the first sintered layer, which may be gold, silver or copper, and the metal particles in the heat conductive layer 32 are then sintered. The first metal layer 31 further includes a first buffer layer located between the first adhesion layer and the first sintering layer, and the first buffer layer can provide a stress buffering function, reduce the risk of cracks occurring between the chip 20 and the thermal interface material layer 30 or inside the thermal interface material layer 30, and increase the reliability of the thermal interface material layer 30. The first buffer layer can be made of aluminum, copper, nickel or nickel-vanadium alloy.
The second metal layer 33 is bonded to the heat sink 40, and the second metal layer is used for sintering the heat sink 40 and the metal particles in the heat conducting layer 32, in more detail, the second metal layer 33 can contact and diffuse into the air gaps at the bottom surface and the bottom surface of the heat sink 40 and into the heat conducting layer 32, so that the second metal layer 33 can form a sintering structure with the bottom surface of the heat sink 40 and a sintering structure with the metal particles in the heat conducting layer 32, thereby ensuring the bonding strength between the second metal layer 33 and the heat sink 40 and reducing the contact thermal resistance between the second metal layer 33 and the heat sink 40.
The second metal layer 33 includes a second adhesion layer and a second sintering layer, the second adhesion layer is sintered with the bottom surface of the heat sink 40, and the material of the second adhesion layer may be titanium, chromium, nickel or nickel-vanadium alloy; the second sintered layer, which may be made of gold, silver or copper, is then sintered with the metal particles in the heat conductive layer 32. The second metal layer 33 further includes a second buffer layer between the second adhesion layer and the second sintering layer, and the second buffer layer can provide a stress buffering function, reduce the risk of cracks between the heat sink 40 and the thermal interface material layer 30 or inside the thermal interface material layer 30, and increase the reliability of the thermal interface material layer 30. The second buffer layer can be made of aluminum, copper, nickel or nickel-vanadium alloy.
The heat sink 40 has a flexible and deformable ability, and the heat sink 40 may be an ultra-thin heat sink made of copper or copper alloy, and the thickness thereof is generally less than 0.5 mm. Due to the design, on one hand, the deformation of the heat sink 40 can be utilized to absorb stress, so that the integrity of the thermal interface material layer 30 and the upper and lower interfaces of the thermal interface material layer 30 is protected, the contact thermal resistance between the chip 20 and the heat sink 40 is reduced, and the heat dissipation performance of the chip 20 is improved; on the other hand, the heat sink can deform together with the chip 20 along with the expansion and contraction of the chip 20, so that the tearing force of the heat sink 40 and the chip 20 to the thermal interface material layer is reduced, the thermal interface material layer 30 is prevented from cracking, and the thermal conductivity of the thermal interface material layer 30 is ensured.
The reinforcing ring 50 is disposed on the substrate 10, and the chip 20, the thermal interface material layer 30, and the heat sink 40 are located on the region of the substrate 10 corresponding to the inner ring of the reinforcing ring, so that the strength of the substrate 10 can be enhanced by the reinforcing ring 50, and the deformation or warpage of the substrate 10 can be reduced. The stiffener ring 50 may be disposed on the same side as the die 20, or may be disposed on the opposite side of the die 20, that is, the stiffener ring 50 and the die 20 may be disposed on the same side of the substrate 1, or may be disposed on both sides of the substrate 10.
The reinforcement ring 50 may be a protrusion formed on the substrate, and the protrusion may be a metal protrusion or a non-metal protrusion, such as a silicon protrusion. Because the reinforcing ring 50 is spaced from the chip 20, the thermal interface material layer 30, and the heat sink 40, that is, the reinforcing ring 50 is not in contact with the chip 20, the thermal interface material layer 30, and the heat sink 40, if the substrate 10 deforms, the deformation of the substrate 10 is not transmitted to the thermal interface material layer 30 through the heat sink 40, so as to prevent cracks from occurring in the thermal interface material layer 30 or in the upper and lower interfaces thereof, and ensure the thermal conductivity of the thermal interface material layer 30.
The chip 20, the thermal interface material layer 30, and the heat sink 40 may be formed on the substrate 10, and then the reinforcing ring 50 may be formed on the substrate; the stiffener ring 50 may be formed on the substrate 10, and then the chip 20, the thermal interface material layer 30, and the heat sink 40 may be formed in the stiffener ring 50.
Referring to fig. 2, another chip package is provided in another embodiment of the present application, in which the substrate 10, the chip 20, the thermal interface material layer 30, the heat spreader 40 and the stiffener ring 50 are substantially the same as those of the above embodiment, and therefore, the same portions can be referred to the related description of the above embodiment and are not repeated herein. The embodiment shown in fig. 2 differs from the embodiment shown in fig. 1 in that: the chip package further includes a ring-shaped adhesive layer 60, the ring-shaped adhesive layer 60 being formed in a ring shape around the outer edge of the thermal interface material layer 30, and the materials include, but are not limited to, epoxy, silicone, and acrylic.
In one possible implementation, as shown in fig. 2, the annular adhesive layer 60 is located on the outer periphery of the heat conductive layer 32, a first surface (a lower surface shown in fig. 2) of the annular adhesive layer 60 is bonded to the first metal layer 31, a second surface (an upper surface shown in fig. 2) of the annular adhesive layer 60 is bonded to the second metal layer 33, and an inner ring of the annular adhesive layer 60 is in contact with an outer side surface of the heat conductive layer 32. By adopting the design, the annular bonding layer 60 is arranged between the first metal layer 31 and the second metal layer 33, the first metal layer 31 and the second metal layer 33 can be connected by the annular bonding layer 60, the tensile fracture force of the first metal layer 31 and the second metal layer 33 to the heat conduction layer 32 is reduced, and the heat conduction performance of the heat conduction layer 32 is ensured.
In another possible implementation, as shown in fig. 3, the annular adhesive layer 60 is located in a peripheral region of the thermal interface material layer 30, or the thermal interface material layer 30 is formed in an annular space surrounded by the annular adhesive layer 60, a first surface (a lower surface shown in fig. 3) of the annular adhesive layer 60 is adhered to a surface of the chip 20 away from the substrate 10, and a second surface (an upper surface shown in fig. 3) of the annular adhesive layer 60 is adhered to a surface of the heat sink 40 close to the substrate 10. With such a design, the chip 20 and the heat sink 40 can be connected by the ring-shaped adhesive layer 60, and the connection force of the thermal interface material layer 30 connecting the chip 20 and the heat sink 40 is shared, so that the connection force borne by the thermal interface material layer 30 is reduced, the tensile crack force of the thermal interface material layer 30 being pulled apart is reduced, and the thermal conductivity of the thermal interface material layer 30 can be ensured.
It should be noted that in the above embodiments, bonding can be understood as adhesively connecting, or sticking together; bonding is understood to mean the connection which is formed following sintering.
Referring to fig. 4, an embodiment of the present application further provides a method for manufacturing a chip package, where the method includes:
step 100, mounting a chip on a substrate.
Exemplarily, a substrate 10 is provided, and the substrate 10 is cleaned and dried; then, the bare chip 21 is mounted on the substrate 10, specifically, a flip chip ball grid array may be used for mounting. The mounting process comprises the following steps: firstly, welding the bottom solder ball of the bare chip 21 on the substrate 10; next, an adhesive is filled at the bottom of the bare chip 21, the adhesive wraps the solder balls to package the solder balls, and a structure diagram of the bare chip 21 attached to the substrate 10 is shown in fig. 5.
Next, a dam molding layer 22 surrounding the bare chip 21 is formed on the substrate 10, for example, a dam molding compound is formed on the periphery of the bare chip 21 by dispensing, and the dam molding compound is cured to form the dam molding layer 22, as shown in fig. 6 and 7, the dam molding layer 22 surrounds an annular space in which the bare chip 21 is located.
Then, filling plastic packaging material is added into the gap between the dam plastic packaging layer 22 and the bare chip 21, and the filling plastic packaging material coats the side surface and the top surface of the bare chip 21; the filling molding compound can then be cured by heating and curing, and a filling molding layer 23 embedded in the dam molding layer 22 is formed after curing, as shown in fig. 8 and 9, and the filling molding layer 23 is formed after curing to cover the bare chip 21, so that the bare chip 21 covered by the filling molding layer 23 is not visible when viewed from the top.
In the above implementation, the dam molding compound and the filling molding compound are cured in the second curing, but not limited thereto, and may also be cured in the first curing, for example, first, the dam molding compound surrounding the bare chip 21 is formed on the substrate 10 with a space between the dam molding compound and the bare chip 21; and then, adding a filling plastic package material into the gap, and finally, curing the dam plastic package material filling plastic package material. The curing method includes, but is not limited to, heating curing, UV curing or microwave curing, and the suitable curing method can be selected according to the material characteristics of the dam molding compound 22 and the filling molding compound 23.
Next, the top surface of the dam plastic-sealed layer 22 and the top surface of the filling plastic-sealed layer 23 are ground, for example, mechanically ground, so as to expose the top surface of the bare chip 21, as shown in fig. 10 and 11, the top surface of the bare chip 21 is flush with the top surface of the dam plastic-sealed layer 22 and the top surface of the filling plastic-sealed layer 23, so that, on one hand, the thickness of the bare chip 21 can be the same as the thickness of the package layer; on the other hand, when the thermal interface material layer 30 is formed between the chip 20 and the heat sink 40, since the top surface of the bare chip 21 is flush with the top surface of the dam molding layer 22 and the top surface of the filling molding layer 23, the internal shear force of the thermal interface material layer 30 is prevented, so that the cracks in the thermal interface material layer 30 can be avoided, and the thermal interface material layer 30 is ensured to have better thermal conductivity.
It should be noted that the dam molding layer 22 and the filling molding layer 23 are formed by dispensing and curing in the above embodiments, but the invention is not limited thereto, and the dam molding layer 22 and the filling molding layer 23 may also be formed by other methods. For example: after the chip 20 is attached to the substrate 10, a dam plastic-sealed layer 22 is formed on the side surface of the bare chip 21 by using a transfer injection molding machine or a compression injection molding machine and a corresponding molding die, the dam plastic-sealed layer 22 is formed on the substrate 10 and arranged around the side surface of the bare chip 21, and the dam plastic-sealed layer 22 is wrapped on the circumferential side surface of the bare chip 21, as shown in fig. 12, the package layer formed in this way is formed by the dam plastic-sealed layer 22. In addition, the encapsulation layer formed in the way can directly enable the top surface of the bare chip 21 to be flush with the top surface of the dam plastic-package layer 22 and the top surface of the filling plastic-package layer 23, so that a subsequent grinding process is not needed, and the chip mounting process flow is simplified.
At step 110, a thermal interface material layer is formed on the top surface of the chip.
Illustratively, first, the first metal layer 31 is formed on the top surface of the bare chip 21, the top surface of the dam molding layer 22 and the top surface of the filling molding layer 23, as shown in fig. 13, the first metal layer 31 can form a sintering-following structure with the top surface of the chip 20 and a sintering-following structure with the metal particles in the heat conductive layer 32, so as to fill the air gap on the top surface of the chip 20, and also ensure the bonding strength therebetween. The first metal layer 31 includes a first adhesion layer and a first sintering layer, the first adhesion layer is sintered with the top surface of the bare chip 21 and the top surface of the encapsulation layer, and the first adhesion layer may be made of titanium, chromium, nickel or nickel-vanadium alloy; the first sintered layer, which may be gold, silver or copper, and the metal particles in the heat conductive layer 32 are then sintered. The first metal layer 31 further includes a first buffer layer between the first adhesion layer and the first sintering layer, and the first buffer layer can provide a stress buffering function, reduce the risk of cracks between the chip 20 and the thermal interface material layer 30 or inside the thermal interface material layer 30, and increase the reliability of the thermal interface material layer 30. The first buffer layer can be made of aluminum, copper, nickel or nickel-vanadium alloy.
Next, a heat conductive layer 32 is formed on the first metal layer 31, and the structure of the heat conductive layer 32 is as shown in fig. 14, where the heat conductive layer 32 generally includes a substrate layer and micron-sized or nanometer-sized metal particles uniformly filled in the substrate layer, where the substrate layer may be a resin layer, and the metal particles include one or more of silver powder, tin powder, aluminum powder, zinc oxide powder, and aluminum oxide powder, for example, in this embodiment, the metal particles are silver powder. The metal particles can adopt micron-scale or nano-scale metal particles, and the nano-scale metal particles have low thermal resistance and can form a better heat conduction path.
Thereafter, a second metal layer 33 is formed on the heat conductive layer 32, and the structure in which the second metal layer is formed is shown in fig. 14. The second metal layer 33 is bonded to the heat sink 40, and the second metal layer 33 can form a sintering-bonded structure with the bottom surface of the heat sink 40 and with the metal particles in the heat conductive layer 32, so as to fill the air gap on the bottom surface of the heat sink 40 and ensure the bonding strength therebetween. The second metal layer 33 includes a second adhesion layer and a second sintering layer, the second adhesion layer is connected with the bottom surface of the heat sink 40, and the second adhesion layer may be made of titanium, chromium, nickel or nickel-vanadium alloy; the second sintered layer, which may be gold, silver or copper, and the metal particles in the heat conductive layer 32 are then sintered. The second metal layer 33 further comprises a second buffer layer between the second adhesion layer and the second sintering layer, which may provide a stress buffering function, reduce the risk of cracks between the heat spreader 40 and the thermal interface material layer 30 or inside the thermal interface material layer 30, and increase the reliability of the thermal interface material layer 30. The second buffer layer can be made of aluminum, copper, nickel or nickel-vanadium alloy.
At step 120, a heat sink is formed on the thermal interface material layer.
Illustratively, the heat sink 40 is bonded on the second metal layer 33, or a metal film is formed on the second metal layer 33, and then a part of the metal film is removed by masking and etching, and the metal film on the second metal layer 33 remains, i.e. the heat sink 40. The structure in which the heat sink 40 is formed is shown in fig. 15.
The heat sink 40 has better deformability, and the heat sink 41 may be an ultra-thin heat sink made of copper or copper alloy, and its thickness is generally less than 0.5 mm. By adopting the deformable heat sink 40, on one hand, the deformation of the heat sink 40 can be utilized to absorb stress, protect the integrity of the thermal interface material layer 30 and the upper and lower interfaces of the thermal interface material layer 30, reduce the contact thermal resistance between the chip 20 and the heat sink 40, and improve the heat dissipation performance of the chip 20; on the other hand, the heat sink can deform together with the chip 20 along with the expansion and contraction of the chip 20, so that the tearing force of the heat sink 40 and the chip 20 on the thermal interface material layer 30 is reduced, cracks in the thermal interface material layer 30 are prevented, and the heat conductivity of the thermal interface material layer 30 is ensured.
Step 130, forming a reinforcement ring on the substrate.
Illustratively, the reinforcement ring 50 is formed on the substrate 10 by bonding, and the structure in which the reinforcement ring 50 is formed is as shown in fig. 1, 2, or 3. The stiffener ring 50 may also be formed by deposition, masking, and etching, for example, the stiffener ring 50 is formed together with the heat spreader 40, and after removing a portion of the metal film during etching, the metal film on the second metal layer 33 and the metal film on the periphery of the chip 20 remain, and the two portions of the metal films are disconnected from each other and do not contact each other. Therefore, if the substrate 10 is deformed, the deformation of the substrate 10 is not transmitted to the thermal interface material layer 30 through the heat sink 40, so that cracks are prevented from occurring in the thermal interface material layer 30 or at the upper and lower interfaces thereof, and the thermal conductivity of the thermal interface material layer 30 is ensured.
In the chip package manufactured by the above manufacturing method, the strength of the substrate can be enhanced by the reinforcing ring 50, and the deformation resistance of the substrate 10 is improved, and if the substrate 10 deforms, because the reinforcing ring 50 is separately arranged on the periphery of the chip and does not contact with the chip 20, the thermal interface material layer 30 and the heat sink 40, the deformation of the substrate 10 is not transmitted to the thermal interface material layer 30 through the heat sink 40, cracks are prevented from occurring in the thermal interface material layer 30 or on the upper and lower interfaces thereof, and the heat conduction performance of the thermal interface material layer 30 is ensured. In addition, due to the stress generated by the expansion and contraction of the chip 20 during and after operation, the stress is transmitted to the substrate 10, and the existence of the reinforcement ring 50 can reduce the influence of the stress on the substrate 10, thereby reducing the risk of deformation of the substrate 10 due to the stress.
In addition, the heat sink 40 has better deformability, and the deformation of the heat sink 40 can absorb stress, protect the integrity of the thermal interface material layer 30 and the upper and lower interfaces of the thermal interface material layer 30, reduce the thermal contact resistance between the chip 20 and the heat sink 40, and improve the heat dissipation performance of the chip 20; on the other hand, by using the deformation of the heat sink 40, the heat sink can deform along with the chip 20 and the thermal interface material layer 30, so that the tearing force of the heat sink 40 and the chip 20 to the thermal interface material layer is reduced, the thermal interface material layer 30 is prevented from cracking, and the heat conduction performance of the thermal interface material layer 30 is ensured.
In addition, the heat sink 40 and the packaging layer wrapped on the side surface of the bare chip 21 can improve the bearing capacity of the chip 20 and reduce the risk of breaking the chip 20 caused by falling in the packaging and transportation process. Furthermore, the encapsulation layer is formed on the side surface of the bare chip 21, which increases the top surface area of the chip 20 compared with the case where no encapsulation layer is disposed on the side surface of the bare chip 21, thereby increasing the bonding area between the thermal interface material layer 30 and the chip 20, providing a larger heat dissipation range for the chip 20, and improving the heat dissipation performance of the chip 20.
In the above method for manufacturing a chip package, when it is required to manufacture a chip package including the annular bonding layer 60, a step of manufacturing the annular bonding layer 60 may be added between step 100 and step 110. Specifically, the top surface of the chip 20 may be coated with a ring-shaped adhesive layer 60 in a region near the edge, and the material of the ring-shaped adhesive layer 60 includes, but is not limited to, epoxy resin, silicone resin, and acrylic resin. Then, in step 110, a thermal interface material is filled in an annular space surrounded by the annular bonding layer 60 to form the thermal interface material layer 30, and then the heat sink 40 is bonded to the annular bonding layer 60 and the thermal interface material layer 30.
In the description herein, references to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (19)

  1. A chip package, comprising: the chip, the thermal interface material layer and the radiating fin are sequentially stacked on the first surface of the substrate, and the reinforcing ring is arranged on the first surface; the reinforcement ring surrounds the chip and has a space with the chip, the thermal interface material layer, and the heat sink.
  2. The chip package of claim 1, wherein the stiffening ring is an annular protrusion.
  3. The chip package according to claim 1 or 2, wherein the heat sink is a flexible heat sink.
  4. The chip package according to any one of claims 1-3, further comprising an annular bonding layer disposed around a circumferential edge of the thermal interface material layer, wherein a first surface of the annular bonding layer is bonded to a surface of the chip away from the substrate, and a second surface of the annular bonding layer is bonded to a surface of the heat sink close to the substrate.
  5. The chip package of any one of claims 1-3, wherein the thermal interface material layer comprises a first metal layer bonded to the chip, a second metal layer bonded to the heat sink, and a thermally conductive layer between the first and second metal layers, the thermally conductive layers being bonded to the first and second metal layers, respectively.
  6. The chip package of claim 5, further comprising an annular bonding layer disposed around a circumferential edge of the heat conductive layer, wherein a first surface of the annular bonding layer is bonded to the first metal layer and a second surface of the annular bonding layer is bonded to the second metal layer.
  7. The chip package according to claim 4 or 6, wherein the material of the ring-shaped adhesive layer comprises epoxy, silicone or acrylic.
  8. The chip package of claim 5, wherein the thermally conductive layer comprises a substrate layer and nanoscale metal particles uniformly filled in the substrate layer.
  9. The chip package according to claim 8, wherein the substrate layer is a resin layer, and the metal particles comprise one or more of silver powder, tin powder, aluminum powder, zinc oxide powder, and aluminum oxide powder.
  10. The chip package of claim 5,
    the first metal layer comprises a first bonding layer and a first sintering layer, the first bonding layer is connected with the chip, and the first sintering layer is connected with the heat conduction layer;
    the second metal layer comprises a second bonding layer and a second sintering layer, the second bonding layer is connected with the radiating fin, and the second sintering layer is connected with the heat conducting layer.
  11. The chip package of claim 10,
    the first metal layer further comprises a first buffer layer between the first adhesion layer and the first sintering layer;
    the second metal layer further includes a second buffer layer between the second adhesion layer and the second sintering layer.
  12. The chip package according to claim 11, wherein the first adhesion layer is made of ti, cr, ni, or ni-v alloy, the first buffer layer is made of al, cu, ni, or ni-v alloy, and the first sintering layer is made of au, ag, or cu;
    the second adhesion layer is made of titanium, chromium, nickel or nickel-vanadium alloy, the second buffer layer is made of aluminum, copper, nickel or nickel-vanadium alloy, and the second sintering layer is made of gold, silver or copper.
  13. The chip package according to claim 1, wherein the chip comprises a bare chip disposed on the substrate, and a packaging layer covering a side of the bare chip, a surface of the packaging layer facing the thermal interface material layer being flush with a surface of the bare chip facing the thermal interface material layer.
  14. The chip package according to claim 13, wherein the package layer comprises a dam plastic package layer and a filling plastic package layer embedded in the dam plastic package layer.
  15. A method of making a chip package, comprising:
    mounting a chip on a first surface of a substrate;
    forming a layer of thermal interface material on a surface of the chip remote from the substrate;
    forming a heat sink on a surface of the thermal interface material layer away from the chip;
    forming a stiffener ring on the first surface, the stiffener ring surrounding the chip with a space between the stiffener ring and the chip, the thermal interface material layer, and the heat sink.
  16. The method of claim 15, wherein the step of mounting the die on the first surface of the substrate comprises:
    bonding a bare chip on the first surface of the substrate by means of underfill;
    form the packaging layer on the first surface of base plate, the packaging layer covers the side of naked chip, just the packaging layer is kept away from the surface of base plate with the naked chip is kept away from the surface parallel and level of base plate.
  17. The method of claim 16, wherein the step of forming an encapsulation layer on the first surface of the substrate comprises:
    forming a dam plastic packaging material on the first surface of the substrate, wherein the dam plastic packaging material surrounds the bare chip, and a gap is formed between the dam plastic packaging material and the bare chip;
    filling plastic packaging materials are arranged in the interval, and the filling plastic packaging materials cover the side face of the bare chip and the surface far away from the substrate;
    solidifying the box dam plastic package material and the filling plastic package material to respectively form a box dam plastic package layer and a filling plastic package layer;
    and grinding the box dam plastic packaging layer and the filling plastic packaging layer to enable the box dam plastic packaging layer to be far away from the surface of the substrate and the filling plastic packaging layer to be far away from the surface of the substrate and the surface of the bare chip to be far away from the surface of the substrate to be flush.
  18. The method of claim 15, wherein the step of forming a layer of thermal interface material on the surface of the chip away from the substrate comprises:
    forming a first metal layer on the surface of the chip far away from the substrate;
    forming a heat conduction layer on the surface of the first metal layer far away from the chip, wherein the heat conduction layer comprises a base material layer and nanoscale metal particles which are uniformly filled in the base material layer;
    a second metal layer is formed on a surface of the thermally conductive layer remote from the first metal layer.
  19. The method of claim 18, further comprising forming an annular adhesive layer on the surface of the first metal layer away from the substrate after the step of forming the thermally conductive layer on the surface of the first metal layer away from the chip and before the step of forming the second metal layer on the surface of the thermally conductive layer away from the first metal layer, wherein the annular adhesive layer wraps the sides of the thermally conductive layer.
CN201980102809.6A 2019-12-16 2019-12-16 Chip package and manufacturing method thereof Pending CN114787990A (en)

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US8779582B2 (en) * 2010-10-20 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Compliant heat spreader for flip chip packaging having thermally-conductive element with different metal material areas
TWI563615B (en) * 2015-05-05 2016-12-21 Siliconware Precision Industries Co Ltd Electronic package structure and the manufacture thereof
CN105355610B (en) * 2015-08-27 2019-01-18 华为技术有限公司 A kind of circuit device and manufacturing method
US11329026B2 (en) * 2016-02-17 2022-05-10 Micron Technology, Inc. Apparatuses and methods for internal heat spreading for packaged semiconductor die
US10573579B2 (en) * 2017-03-08 2020-02-25 Mediatek Inc. Semiconductor package with improved heat dissipation
CN109103154A (en) * 2017-06-21 2018-12-28 华为技术有限公司 A kind of chip-packaging structure
US10515869B1 (en) * 2018-05-29 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure having a multi-thermal interface material structure

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