CN114779607B - Time measurement circuit, time measurement method, time measurement chip, time measurement module and electronic equipment - Google Patents
Time measurement circuit, time measurement method, time measurement chip, time measurement module and electronic equipment Download PDFInfo
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Abstract
The application discloses a time measuring circuit, a time measuring method, a time measuring chip, a time measuring module and electronic equipment, and relates to the technical field of time measurement and depth measurement. The time measurement circuit of the present application includes: the signal selection output module is used for receiving a first signal, a second signal and a reference clock signal and selecting an output measurement signal, wherein the measurement signal is one of the first signal, the second signal, the reference clock signal and the adjusted reference clock signal; and the time measurement module is used for calibrating time measurement precision and measuring the time interval between the first signal and the second signal. The application also provides a time measurement method, a time measurement chip, a time measurement module and electronic equipment based on the time measurement circuit. The application can rapidly realize high-precision time measurement within picosecond level under the condition of limited clock frequency lifting space.
Description
Technical Field
The application relates to the technical field of time measurement and depth measurement, in particular to a time measurement circuit, a time measurement method, a time measurement chip, a time measurement module and electronic equipment.
Background
TDC (Time-to-Digital Converter ) is a device for converting Time intervals into digital output, and is widely used in the field of distance measurement sensing where high-precision Time measurement is required, such as photographic focusing, object recognition, augmented Reality (AR), three-dimensional modeling, real-scene navigation and the like. The conventional TDC is composed of a multi-phase ring oscillator (multi-phase ring oscillator) and a D flip-flop, and is designed by an analog method.
However, when designing using the conventional analog method, a high-frequency clock PLL and a ring oscillator are generally used to generate clocks of various phases as precision measurement units of the TDC, when the precision requirement is higher, a higher PLL clock is required, so that the design difficulty increases, and the increase in clock frequency will cause an increase in circuit power consumption. The simulation method also has the technical problems of easy external interference, complex control, large area power consumption and the like, and is difficult to realize on an integrated circuit rapidly.
Disclosure of Invention
In view of this, the embodiments of the present application provide a time measurement circuit, a method, a chip, a module and a device, which are used to replace the conventional simulation method and realize high-precision time length measurement precision.
In a first aspect, an embodiment of the present application provides a time measurement circuit, the circuit including:
the signal selection output module is used for receiving a first signal, a second signal and a reference clock signal and selecting and outputting a measurement signal, wherein the measurement signal is one of the first signal, the second signal, the reference clock signal and the adjusted reference clock signal;
and the time measurement module is used for calibrating the time measurement precision and measuring the time interval between the first signal and the second signal.
In a second aspect, an embodiment of the present application further provides a time measurement method based on the foregoing time measurement circuit, where the method includes:
s1: acquiring the measurement precision of the time measurement circuit;
s2: according to the measurement precision, acquiring a first signal rising edge and a time interval between the first signal rising edge and a first reference clock rising edge after the first signal rising edge, and recording the time interval as a first time interval;
s3: according to the measurement precision, acquiring a second signal rising edge and a time interval between the first reference clock rising edge after the second signal rising edge, and recording the time interval as a second time interval;
s4: acquiring the number of reference clock cycles between a first reference clock rising edge after the first signal rising edge and a first reference clock rising edge after the second signal rising edge;
s5: and acquiring the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of the reference clock cycles.
In a third aspect, an embodiment of the present application provides a time measurement chip, including:
a time measurement circuit as claimed in any one of the first aspects; and
and the analog-to-digital conversion circuit is used for converting the analog signal into a digital signal and inputting the digital signal into the time measurement circuit.
In a fourth aspect, an embodiment of the present application provides a time measurement module, including:
a transmitter for transmitting a detection signal;
the receiver is used for receiving the reflected signal corresponding to the detection signal;
the time measurement chip of the third aspect, the time measurement chip is connected to the transmitter and the receiver, and is used for measuring a time interval between a detection signal transmitted by the transmitter and a reflected signal corresponding to the detection signal received by the receiver.
In a fifth aspect, an embodiment of the present application provides an electronic device, including the time measurement module according to the fourth aspect. The electronic device is any one, two or more of a smart phone, an unmanned aerial vehicle, a movable robot, a smart television, an AR/VR device and a 3D depth measurement device.
In summary, the beneficial effects of the application are as follows:
the time measurement circuit of the embodiment of the application realizes the calibration of time measurement precision and the time measurement of measurement signals through the signal selection output module and the time measurement module. Under the condition of limited clock frequency lifting space, high-precision time measurement below picoseconds can be rapidly realized, and under the current common process, measurement precision of about 30ps can be realized.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described, and it is within the scope of the present application to obtain other drawings according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a time measurement circuit according to an embodiment of the application.
Fig. 2 is a schematic diagram of a signal selection output module according to an embodiment of the application.
Fig. 3 is another schematic diagram of the signal selection output module according to an embodiment of the application.
Fig. 4 is a schematic diagram of a time measurement module according to an embodiment of the application.
Fig. 5 is a schematic diagram of another structure of the time measurement circuit according to the embodiment of the application.
FIG. 6 is a schematic diagram of a time measurement circuit according to an embodiment of the application.
FIG. 7 is another schematic diagram of a time measurement circuit according to an embodiment of the application.
Fig. 8 is a flowchart of a time measurement method according to an embodiment of the application.
Fig. 9 is a schematic waveform diagram of a time interval for acquiring a first signal and a second signal in a time measurement method according to an embodiment of the present application.
Fig. 10 is a schematic waveform diagram of obtaining time measurement accuracy in the time measurement method according to the embodiment of the present application.
FIG. 11 is a waveform diagram illustrating a time interval between the acquisition of the rising edge of the first signal and the latching of the rising edge of the first signal in the time measurement method according to the embodiment of the application.
Fig. 12 is a schematic diagram of a time measurement chip according to an embodiment of the present application.
Fig. 13 is a schematic structural diagram of a time measurement module according to an embodiment of the application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely configured to illustrate the application and are not configured to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of a time measurement circuit according to an embodiment of the application. As shown in fig. 1, an embodiment of the present application provides a time measurement circuit 10, the time measurement circuit 10 including: a signal selection output module 11 and a time measurement module 12.
The signal selection output module 11 is configured to receive the first signal, the second signal, and the reference clock signal, and select an output measurement signal, where the measurement signal is one of the first signal, the second signal, the reference clock signal, and the adjusted reference clock signal. The first signal and the second signal may be rising edge signals such as low-high level, or pulse signals such as low-high-low level. In some embodiments, the first signal is an analog-to-digital converted Start signal sent by a transmitting end Of a TOF (Time Of Flight) ranging module, and the second signal is an analog-to-digital converted Stop signal received by a receiving end Of the TOF ranging module. Alternatively, in other embodiments, the first signal may be the Stop signal, and the second signal may be the Start signal, which is not limited in detail in the present application. The reference clock signal may be a high-frequency pulse signal generated by a multiphase ring oscillator, or may be other signals, which is not limited in the present application. The receiving end of the signal selection output module 11 will receive the first signal, the second signal and the reference clock signal, and select any one of the first signal, the second signal, the reference clock signal or the adjusted reference clock signal to output to the time measurement module 12.
A time measurement module 12 for calibrating the time measurement accuracy and measuring the time interval between the first signal and the second signal. When the signal received by the time measurement module 12 is the reference clock signal or the adjusted reference clock signal, performing time measurement accuracy measurement or calibration; when the received signal is first the first signal and then the second signal, or is first the second signal and then the first signal, the time interval between the first signal and the second signal is measured. The application can calibrate the resolution (measurement accuracy) in real time in an idle state before measurement, and reduce the error influence caused by different environment temperatures and the like.
In one embodiment, as shown in fig. 2, the signal selection output module 11 includes: the first selection unit 111 and the second selection unit 112, where the first selection unit 111 is, for example, a two-input or gate in a logic circuit, and of course, other circuits having a signal selection input function may also be used, two input ends of the first selection unit 111 are respectively used to receive the first signal and the second signal, and an output end of the first selection unit 111 is used to connect an input end of the second selection unit 112.
The second selection unit 112 is, for example, a two-input or gate in a logic circuit, but may be any other circuit having a signal selection input function, where one input end of the second selection unit 112 is connected to the output end of the first selection unit 111, the other input end of the second selection unit 112 receives the reference clock signal, and the output end of the second selection unit 112 is connected to the input end of the first delay unit (I1) of the delay chain.
In some embodiments, as shown in fig. 3, the signal selection output module 11 includes: a first selection unit 111, a second selection unit 112, a positive and negative pulse generation unit 114, and a scheduling unit 113. The first selecting unit 111 and the second selecting unit 112 are described in fig. 2, and are not described herein. The difference is that the input terminal of the positive and negative pulse generating unit 114 receives the reference clock signal, and the output terminal of the positive and negative pulse generating unit 114 is connected to one of the input terminals of the second selecting unit 112. The positive and negative pulse generation unit 114 is used to adjust the reference clock signal to a positive single-period clock signal or a negative single-period clock signal. The application calibrates the inverter delay chain by simultaneously using the positive single-period clock signal (positive pulse signal) and the negative single-period clock signal (negative pulse signal) in real time so as to calculate the proportion of the delay value of a single inverter relative to the period of a single reference clock signal and reduce the influence of the response error accumulation of a single-use positive pulse or negative pulse circuit.
The scheduling unit 113 is configured to control the positive and negative pulse generating unit 114 to adjust the input reference clock signal to the positive single-period clock signal or the negative single-period clock signal. The positive single-period clock signal and the negative single-period clock signal are circularly input into the time measurement module 12 for a plurality of times, so that the time measurement precision can be calibrated, the more accurate time measurement precision is obtained, and the accuracy of the time measurement result of the measurement signal is improved.
In one embodiment, as shown in fig. 4, the time measurement module 12 includes a delay chain 121 and a latch module 122, wherein the delay chain 121 is configured to receive the measurement signal from the signal selection output module 11, and the delay chain 121 includes n delay units (I 1 In), the first delay unit I of the delay chain 121 1 The n-th delay unit In of the delay chain 121 is connected with the output end of the signal selection output module 11 and sequentially transmits the rising edge of the measurement signal from the first delay unit I1, wherein n is a positive integer greater than 2;
the latch module 122 is configured to latch the output signal of the delay chain 121, where the latch module 122 includes n latch units (D1-Dn), where the n latch units (D1-Dn) each include two input terminals, and one input terminal of each latch unit is connected to the output terminal of one delay unit, and the other input terminal is configured to receive the reference clock signal.
The principle of time measurement by adopting the delay chain 121 and the latch module 122 is that a detected signal (rising edge signal) is transmitted through the delay chain 121, the latch module 122 is triggered to latch the state value of the delay chain 121 at the rising edge of the first reference clock signal after the rising edge of the detected signal, the output signal of the delay chain 121 is obtained, and the time difference between the detected signal and the rising edge of the first reference clock signal after the rising edge of the detected signal can be obtained, wherein the signal delay time between each delay unit is the measured resolution.
In one embodiment, delay chain 121 includes a number of delay cells, which are preferably inverters. The current manufacturing process of the inverter can achieve the level of 40nm, and the minimum delay of the inverter can reach about 30ps under the manufacturing process, because the resolution (precision) of the whole time measuring circuit depends on the delay of the delay unit, the use of the inverter can enable the precision of time measurement to reach about 30 ps. In some embodiments, a Buffer unit may be used, but this problem may be avoided by using an inverter because the Buffer unit has different response delays to the rising or falling edges of the signal, thereby affecting the measurement result.
In one embodiment, the latch unit in the latch module 122 is a D flip-flop, one input end of the D flip-flop is connected to the output end of the delay unit, and the other input end of the D flip-flop receives the reference clock signal and is configured to latch the state value of the delay unit when a preset rising edge of the reference clock signal occurs, or to know the time delay between the measurement signal transmitted along the delay chain and the preset rising edge of the reference clock signal according to the state values of the delay units.
In one embodiment, as shown in fig. 5, the time measurement circuit 10 further includes a decoding module 13, where the decoding module 13 is connected to the latch module 122 in the time measurement module 12, and is configured to convert the output of the latch module 122 into binary data that is convenient to read.
Preferably, as shown in fig. 6, the time measurement circuit 10 has a schematic structure, in which two input terminals of a first selection unit 111 in the signal selection output module 11 respectively receive a first signal and a second signal, and an output terminal of the first selection unit 111 is connected to an input terminal of a second selection unit 112; one input end of the second selection unit 112 is connected with the output end of the first selection unit 111, the other input end of the second selection unit 112 receives the reference clock signal, and the output end of the second selection unit 112 is connected with the first delay unit I of the delay chain 121 1 Is provided. Delay chain 121 includes n delay cells (I 1 -I n ) Also, the latch module 122 includes n latch units (D 1 -D n ) The output of each delay cell in the delay chain 121 is connected to one input of one of the latch cells in the latch module 122, and the output of each latch cell in the latch module 122 is connected to the decoder module 13.
Preferably, as shown in fig. 7, the time measurement circuit 10 has a schematic structure, in which two input terminals of a first selection unit 111 in the signal selection output module 11 respectively receive a first signal and a second signal, and an output terminal of the first selection unit 111 is connected to one input terminal of a second selection unit 112; the input end of the positive and negative pulse generation unit 114 receives the reference clock signal, and the output end of the positive and negative pulse generation unit 114 is connected with the other input end of the second selection unit 112; an output terminal of the second selection unit 112 is connected to an input terminal of the first delay unit I1 of the delay chain 121. The delay chain 121 includes n delay units, and the latch module 122 includes n latch units, where an output terminal of each delay unit in the delay chain 121 is connected to an input terminal of a D flip-flop in the latch module 122, and an output terminal of each latch unit in the latch module 122 is connected to the decoding module 13.
In addition, it should be noted that, in the embodiment of the present application, the value of n may be determined according to the measurement accuracy requirement of the time measurement module 12, which is not specifically limited herein.
In addition, the time measurement circuit 10 may be an application specific integrated circuit, and the circuit 10 may be integrated in a Field Programmable Gate Array (FPGA) chip, for example, or may be integrated in an Application Specific Integrated Circuit (ASIC) chip, which is not particularly limited in the embodiment of the present application.
Embodiments of the time measurement circuit of the present application are described above in detail with reference to fig. 1 to 7, and embodiments of a time measurement method based on the above-described time measurement circuit are described below in detail with reference to fig. 8, 9 and 10. It will be appreciated that the description of the method embodiments of the application corresponds to the description of the device embodiments, and that parts not described in detail can therefore be seen in the previous embodiments of the time measurement circuit.
Example two
Referring to fig. 8, a flowchart of a time measurement method according to an embodiment of the application is shown, wherein the method is implemented based on the time measurement circuit, and includes the following steps:
s1: acquiring the measurement precision of a time measurement circuit;
s2: according to the measurement precision, acquiring a time interval between a rising edge of a first signal and a rising edge of a first reference clock signal after the rising edge of the first signal, and recording the time interval as a first time interval;
s3: according to the measurement precision, acquiring a time interval between a rising edge of a second signal and a rising edge of a first reference clock signal after the rising edge of the second signal, recording the time interval as a second time interval, and simultaneously acquiring the number of reference clock cycles between the rising edge of the first reference clock signal after the rising edge of the first signal and the rising edge of the first reference clock signal after the rising edge of the second signal;
s4: and acquiring the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of the reference clock cycles.
The principle of measuring the interval time between the first signal and the second signal according to the embodiment of the present application is shown in fig. 9, and the delay time between the first signal and the second signal may be calculated by the following formula (1):
△T＝N×Tclk+△Ta-△Tb (1)
in the above formula (1), Δt is a time difference between a first signal rising edge and a second signal rising edge, tclk is a clock period of a reference clock signal, N is a number of periods of the reference clock signal differing between the first signal and the second signal, Δta is a time difference between the first signal rising edge and a first reference clock signal rising edge subsequent to the first signal rising edge, and Δtb is a time difference between the second signal rising edge and a first reference clock rising edge subsequent to the second signal rising edge.
In one embodiment, the time measurement circuit as described in fig. 6 is used to measure the delay time between the first signal and the second signal. Since the measurement accuracy (i.e. measurement resolution) of the time measurement circuit depends on the delay size of the delay unit, the delay size of one delay unit is recorded as the unit delay Tinv, and the Tinv is calculated first before the Δt is calculated. The signal selection output module 11 selects to input the reference clock signal into the delay chain 121, and simultaneously inputs the reference clock signal into the latch module 122, as shown in fig. 10, a first clock rising edge of the reference clock signal is sequentially transferred from a first delay unit in the delay chain to an nth delay unit in the delay chain, and a unit delay is generated correspondingly for each transfer of the first clock rising edge of one delay unit. The latch module 122 latches the state value of the corresponding delay unit when the second clock rising edge of the input reference clock signal arrives, and obtains the unit delay number K generated by sequentially transmitting the first clock rising edge in one clock cycle through the delay chain through the decoding module 13, and records the unit delay number K as the clock cycle module value count, wherein K is an integer greater than 0, and then the following formula (2) is obtained
In some embodiments, an i-th rising edge of the reference clock signal is input into the delay chain, and the latch unit latches the state value of the delay unit when the j-th rising edge of the reference clock signal arrives, wherein i and j are natural numbers greater than or equal to 1. The decoding module 13 obtains the number K ' of unit delays generated correspondingly by the ith rising edge of the reference clock signal in one clock period, wherein K ' is an integer greater than 0, and then the following formula (2 ') is obtained:
after Tinv is obtained, the values of Δta and Δtb are obtained, respectively.
When Δta is measured, the signal selection output module 11 outputs a first signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, as shown in fig. 11, latches the state value of the delay chain 121 when the rising edge (latching rising edge) of the first reference clock signal after the rising edge of the first signal arrives, and obtains the unit delay number a from the rising edge of the first signal to the rising edge of the first reference clock signal after the rising edge of the first signal through the decoding module 13.
The following equation (3) can be obtained from equation (2):
similarly, when Δtb is measured, the signal selection output module 11 outputs a second signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, latches the state value of the delay chain 121 at the rising edge of the first reference clock signal after the rising edge of the second signal, and obtains the unit delay number B from the rising edge of the second signal to the rising edge of the first reference clock signal after the rising edge of the second signal through the decoding module 13.
The following equation (4) can be obtained from equation (2):
further, when Δtb is measured, an integer number of clock cycle counts N included in the interval time between the first signal and the second signal can be obtained, and the following equation (5) can be obtained according to equations (1) (2) (3) (4):
the reference clock signal may be a positive pulse signal or a negative pulse signal, and it should be noted that, due to the influence of the manufacturing process or environmental factors, each delay unit inevitably has a response error, so as to reduce the influence of response error accumulation when the same positive pulse signal or negative pulse signal is used alone, another embodiment of the present application shown in fig. 7 adjusts the reference clock signal to be a positive single period clock signal or a negative single period clock signal through the positive and negative pulse generating unit 114, and uses the positive single period clock signal and the negative positive period clock signal to calibrate the resolution of the time measurement circuit several times. The specific calibration process is as follows:
s101: inputting a positive single-period clock signal, and obtaining a first clock period modulus value count Np of the positive single-period clock signal;
s102: inputting a negative single-period clock signal, and obtaining a first clock period modulus value count (NN) of the negative single-period clock signal;
s103: inputting a positive single-period clock signal, and obtaining a second clock period modulus value count Np' of the positive single-period clock signal;
s104: inputting a negative single-period clock signal, and obtaining a second clock period modulus value count (Nn') of the negative single-period clock signal;
s105: when np=np 'and nn=nn', the calibration process ends;
when Np not equal to Np 'or Nn not equal to Nn', step S101-step S104 are executed again until np=np 'and nn=nn' the calibration process ends;
when Np not equal Np 'or Nn not equal Nn', and the number of times of executing steps S101-S104 is equal to the preset number of times, the calibration process is also ended, so that it takes too long to enter the calibration process. Preferably, the preset number of times is 8.
After the calibration process is finished, the value of K is calculated, namely:
because tinv=tclk/K, the measurement accuracy Tinv after calibration can be obtained as follows:
the signal selection output module 11 outputs a first signal to the input end of the delay chain 121 when Δta is measured, the latch module 122 accesses the reference clock signal, latches the state value of the delay chain 121 when the rising edge of the first reference clock after the rising edge of the first signal arrives, and obtains the unit delay number a between the rising edge of the first signal and the rising edge of the first reference clock after the rising edge of the first signal through the decoding module 13, as shown in fig. 10.
Equation (8) can be derived from equation (7):
similarly, when Δtb is measured, the signal selection output module 11 outputs a second signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, latches the state value of the delay chain 121 when the rising edge of the first reference clock after the rising edge of the second signal arrives, and obtains the unit delay number B from the rising edge of the second signal to the rising edge of the first reference clock after the rising edge of the second signal through the decoding module 13.
As can be obtained from the formula (2),
further, when Δtb is measured, an integral number of clock cycle counts N included in the interval time between the first signal and the second signal can be obtained, which is obtainable according to formulas (1) (6) (8) (9):
in summary, the time measurement circuit according to the embodiment of the present application realizes calibration of time measurement accuracy and time measurement of measurement signals through the signal selection output module 11 and the time measurement module 12. On the one hand, the embodiment of the application obtains the time measurement precision by inputting the reference clock signal into the delay chain 121, and further, the positive and negative pulse generating unit 114 generates the positive single-period clock signal and the negative single-period clock signal to calibrate the time measurement precision, thereby obtaining a more accurate time measurement result. The calibration of the time measurement accuracy can be performed in an idle state before the time measurement of the first signal and the second signal is measured, so that the measurement accuracy can be improved, and the error influence caused by different environment temperatures and the like can be reduced. On the other hand, the time measuring circuit 10 is configured to measure the time by selecting an appropriate amount of delay units (I 1 In) to avoid the problem of large errors caused by the inability to cover the measurement time range with the reference clock signal time period integer count. Furthermore, by selecting the inverter with small delay value as the delay unit and using a sufficient number of delay units, the frequency of the reference clock signal can be correspondingly reduced, thereby achieving the purpose of reducing the power consumption. The inverter is selected instead of the Buffer unit to reduce the influence of the Buffer unit on different response delays of the rising edge and the falling edge of the signal, so that picosecond-level high-precision time measurement is rapidly realized, and the measurement precision of about 30ps can be realized under the current manufacturing process.
Example III
The embodiment of the application also provides a time measuring chip 30. As shown in fig. 12, the time measuring chip 30 includes the time measuring circuit 10 described above and an analog-to-digital conversion circuit 31 for converting an analog signal received by the chip into a digital signal and inputting the digital signal into the time measuring circuit 10 for time measurement. For a detailed description of the time measurement circuit 10, please refer to the previous embodiments 1 and 2, and the detailed description thereof is omitted.
Example IV
The embodiment of the application also provides a time measurement module 40. As shown in fig. 13, the time measuring module 40 includes a transmitter 41, a receiver 42, and a time measuring chip 30 as shown in fig. 13. The transmitter 41 is arranged to transmit a detection signal, for example an infrared or near infrared light signal, or other visible light signal. The receiver 42 receives a reflected signal corresponding to the detected signal, and the reflected signal is an analog signal. The time measuring chip 30 is connected to the transmitter 41 and the receiver 42, receives analog signals from the transmitter 41 and the receiver 42, then the time measuring chip 30 converts them into digital signals, the time measuring circuit 10 measures the time interval between the detection signal transmitted from the transmitter 41 and the reflected signal corresponding to the detection signal received by the receiver 42, and then obtains the distance of the target object according to the time interval. For the description of the time measurement chip 30, please refer to the third embodiment, and the description thereof is omitted.
Example five
The embodiment of the application also provides an electronic device, which comprises the time measurement module 40 as described in the fourth embodiment. The electronic device can be a smart phone, an unmanned plane, a movable robot, a smart television, an AR/VR, a 3D depth measurement device and the like, and the accurate measurement of the depth information of the target object can be realized through the flight time measurement module 40.
In summary, the time measurement circuit, the time measurement method, the time measurement chip, the time measurement module and the electronic device provided by the embodiment of the application can realize high-precision time measurement below picoseconds under the prior art condition that the clock frequency lifting space is limited, and can realize measurement precision of about 30ps under the current common process.
It should be understood that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after appreciating the spirit of the present application.
The functional blocks shown in the above-described structural block diagrams may be implemented in hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave. A "machine-readable medium" may include any medium that can store or transfer information. Examples of machine-readable media include electronic circuitry, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and the like. The code segments may be downloaded via computer networks such as the internet, intranets, etc.
It should also be noted that the exemplary embodiments mentioned in this disclosure describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, or may be performed in a different order from the order in the embodiments, or several steps may be performed simultaneously.
In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present application, and they should be included in the scope of the present application.
Claims (13)
1. A time measurement circuit, the circuit comprising:
the signal selection output module is used for receiving a first signal, a second signal and a reference clock signal and selecting and outputting a measurement signal, wherein the measurement signal is one of the first signal, the second signal, the reference clock signal and the adjusted reference clock signal;
a time measurement module for calibrating a time measurement accuracy and measuring a time interval between the first signal and the second signal;
the time measurement module comprises a delay chain and a latch module, wherein the delay chain is used for receiving the measurement signals from the signal selection output module, the delay chain comprises n delay units which are sequentially connected, a first delay unit of the delay chain is connected with the output end of the signal selection output module, and the rising edge of the measurement signals is sequentially transmitted from the first delay unit to an nth delay unit of the delay chain, wherein n is a positive integer greater than 2; the latch module is used for latching output signals of the delay chain, wherein the latch module at least comprises n latch units, one input end of two input ends of each latch unit is connected with the output end of one delay unit, and the other input end is used for receiving the reference clock signal;
the signal selection output module includes: a first selection unit and a second selection unit; the two input ends of the first selection unit are respectively used for receiving the first signal and the second signal, and the output end of the first selection unit is connected with the input end of the second selection unit; one input end of the second selection unit is connected with the output end of the first selection unit, the other input end of the second selection unit is used for receiving the reference clock signal, and the output end of the second selection unit is connected with the input end of the first delay unit in the delay chain.
2. The time measurement circuit of claim 1, wherein the time measurement circuit further comprises:
and the decoding module is connected with the latch module and is used for converting the output signal of the latch module into binary data which is convenient to read.
3. The time measurement circuit of claim 1, wherein the delay element is an inverter.
4. A time measurement circuit according to claim 3, wherein the latch unit is a D flip-flop.
5. A time measurement circuit, the circuit comprising:
the signal selection output module is used for receiving a first signal, a second signal and a reference clock signal and selecting and outputting a measurement signal, wherein the measurement signal is one of the first signal, the second signal, the reference clock signal and the adjusted reference clock signal;
a time measurement module for calibrating a time measurement accuracy and measuring a time interval between the first signal and the second signal;
the time measurement module comprises a delay chain and a latch module, wherein the delay chain is used for receiving the measurement signals from the signal selection output module, the delay chain comprises n delay units which are sequentially connected, a first delay unit of the delay chain is connected with the output end of the signal selection output module, and the rising edge of the measurement signals is sequentially transmitted from the first delay unit to an nth delay unit of the delay chain, wherein n is a positive integer greater than 2; the latch module is used for latching output signals of the delay chain, wherein the latch module at least comprises n latch units, one input end of two input ends of each latch unit is connected with the output end of one delay unit, and the other input end is used for receiving the reference clock signal;
the signal selection output module includes: the device comprises a first selection unit, a second selection unit, a positive and negative pulse generation unit and a scheduling unit; the two input ends of the first selection unit respectively receive the first signal and the second signal, and the output end of the first selection unit is connected with the input end of the second selection unit; one input end of the second selection unit is connected with the output end of the first selection unit, the other input end of the second selection unit is connected with the output end of the positive and negative pulse generation unit, and the output end of the second selection unit is connected with the input end of the first delay unit of the delay chain; the input end of the positive and negative pulse generating unit receives the reference clock signal, and the output end of the positive and negative pulse generating unit is connected with one input end of the second selecting unit; the positive and negative pulse generating unit is used for generating a positive single-period clock signal or a negative single-period clock signal; the scheduling unit is used for controlling the positive and negative pulse generating unit to adjust the input reference clock signal to the positive single-period clock signal or the negative single-period clock signal.
6. The time measurement circuit of claim 5, wherein the time measurement circuit further comprises:
and the decoding module is connected with the latch module and is used for converting the output signal of the latch module into binary data which is convenient to read.
7. The time measurement circuit of claim 5, wherein the delay element is an inverter.
8. The time measurement circuit of claim 7, wherein the latch unit is a D flip-flop.
9. A time measurement method based on the time measurement circuit of any one of claims 1 to 8, the method comprising:
s1: acquiring the measurement precision of the time measurement circuit;
s2: according to the measurement precision, acquiring a first signal rising edge and a time interval between the first signal rising edge and a first reference clock rising edge after the first signal rising edge, and recording the time interval as a first time interval;
s3: according to the measurement precision, acquiring a second signal rising edge and a time interval between the first reference clock rising edge after the second signal rising edge, and recording the time interval as a second time interval;
s4: acquiring the number of reference clock cycles between a first reference clock rising edge after the first signal rising edge and a first reference clock rising edge after the second signal rising edge;
s5: and acquiring the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of the reference clock cycles.
10. A time measurement method based on the time measurement circuit of any one of claims 5 to 8, the method comprising:
s1: acquiring the measurement precision of the time measurement circuit;
s2: according to the measurement precision, acquiring a first signal rising edge and a time interval between the first signal rising edge and a first reference clock rising edge after the first signal rising edge, and recording the time interval as a first time interval;
s3: according to the measurement precision, acquiring a second signal rising edge and a time interval between the first reference clock rising edge after the second signal rising edge, and recording the time interval as a second time interval;
s4: acquiring the number of reference clock cycles between a first reference clock rising edge after the first signal rising edge and a first reference clock rising edge after the second signal rising edge;
s5: acquiring a time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of reference clock cycles;
the method further comprises, before the obtaining of the measurement accuracy of the time measurement circuit: calibrating the measurement accuracy, specifically including:
s101: inputting the positive single-period clock signal, and obtaining a first clock period modular value count Np of the positive single-period clock signal;
s102: inputting the negative single-period clock signal, and obtaining a first clock period modulus value count (NN) of the negative single-period clock signal;
s103: inputting the positive single-period clock signal, and obtaining a second clock period modular value count Np' of the positive single-period clock signal;
s104: inputting the negative single-period clock signal, and obtaining a second clock period modulus value count (Nn') of the negative single-period clock signal;
s105: calibration ends when np=np 'and nn=nn';
when Np not equal to Np 'or Nn not equal to Nn', steps S101 to S104 are performed until np=np 'and nn=nn', and the calibration ends;
when Np not equal Np 'or Nn not equal Nn', and the number of times of executing steps S101 to S104 is equal to the preset number of times, the calibration is ended.
11. A time measurement chip, the time measurement chip comprising:
the time measurement circuit of any one of claims 1-8; and
and the analog-to-digital conversion circuit is used for converting the analog signal into a digital signal and inputting the digital signal into the time measurement circuit.
12. A time measurement module, the module comprising:
a transmitter for transmitting a detection signal;
the receiver is used for receiving the reflected signal corresponding to the detection signal; the method comprises the steps of,
the time measurement chip of claim 11, coupled to the transmitter and the receiver, for measuring a time interval between a detection signal transmitted by the transmitter and a reflected signal corresponding to the detection signal received by the receiver.
13. An electronic device comprising the time measurement module of claim 12.
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