CN114779607A - Time measurement circuit, time measurement method, time measurement chip, time measurement module and electronic equipment - Google Patents
Time measurement circuit, time measurement method, time measurement chip, time measurement module and electronic equipment Download PDFInfo
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Abstract
The application discloses a time measuring circuit, a time measuring method, a time measuring chip, a time measuring module and electronic equipment, and relates to the technical field of time measurement and depth measurement. The time measurement circuit of the present application includes: the signal selection output module is used for receiving a first signal, a second signal and a reference clock signal and selecting an output measurement signal, wherein the measurement signal is one of the first signal, the second signal, the reference clock signal and an adjusted reference clock signal; and the time measurement module is used for calibrating the time measurement precision and measuring the time interval between the first signal and the second signal. The application also provides a time measuring method, a time measuring chip, a time measuring module and electronic equipment based on the time measuring circuit. According to the method and the device, under the condition that the clock frequency lifting space is limited, high-precision time measurement within the picosecond level can be rapidly realized.
Description
Technical Field
The present application relates to the field of time measurement and depth measurement technologies, and in particular, to a time measurement circuit, a time measurement method, a time measurement chip, a time measurement module, and an electronic device.
Background
A Time-to-Digital Converter (TDC) is a device that converts a Time interval into a Digital quantity for output, and is widely used in the field of distance measurement sensing requiring high-precision Time measurement, such as photographic focusing, object recognition, Augmented Reality (AR), three-dimensional modeling, live-action navigation, and the like. A conventional TDC is composed of a multi-phase ring oscillator (multi-phase ring oscillator) and a D flip-flop, and is designed by an analog method.
However, when the conventional analog method is adopted for design, a high-frequency clock PLL and a ring oscillator are generally used for generating clocks with various phases as a precision measurement unit of the TDC, and when the precision requirement is higher, the higher the PLL clock is required, so that the design difficulty is increased, and the increase of the clock frequency will cause the increase of the circuit power consumption. The simulation method also has the technical problems of easy external interference, complex control, large area power consumption and the like, and is difficult to realize on an integrated circuit quickly.
Disclosure of Invention
In view of this, embodiments of the present application provide a time measurement circuit, a time measurement method, a chip, a module and a device, so as to replace the conventional analog method and achieve high-precision time length measurement precision.
In a first aspect, an embodiment of the present application provides a time measurement circuit, where the circuit includes:
the signal selection output module is used for receiving a first signal, a second signal and a reference clock signal and selectively outputting a measurement signal, wherein the measurement signal is one of the first signal, the second signal, the reference clock signal and an adjusted reference clock signal;
and the time measuring module is used for calibrating the time measuring precision and measuring the time interval between the first signal and the second signal.
In a second aspect, an embodiment of the present application further provides a time measurement method based on the foregoing time measurement circuit, where the method includes:
s1: acquiring the measurement precision of the time measurement circuit;
s2: according to the measurement precision, acquiring a first signal rising edge and a time interval between the first signal rising edge and a first reference clock rising edge after the first signal rising edge, and recording the time interval as a first time interval;
s3: according to the measurement precision, acquiring a second signal rising edge and a time interval between the second signal rising edge and a first reference clock rising edge after the second signal rising edge, and recording as a second time interval;
s4: acquiring the number of reference clock periods between a first reference clock rising edge after the first signal rising edge and a first reference clock rising edge after the second signal rising edge;
s5: and acquiring the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of the reference clock cycles.
In a third aspect, an embodiment of the present application provides a time measurement chip, where the time measurement chip includes:
a time measurement circuit as claimed in any one of the first aspect; and
and the analog-to-digital conversion circuit is used for converting the analog signal into the digital signal and inputting the digital signal to the time measurement circuit.
In a fourth aspect, an embodiment of the present application provides a time measurement module, where the module includes:
a transmitter for transmitting a detection signal;
the receiver is used for receiving a reflected signal corresponding to the detection signal;
the time measurement chip according to the third aspect, the time measurement chip is connected to the transmitter and the receiver, and is configured to measure a time interval between a detection signal transmitted by the transmitter and a reflected signal corresponding to the detection signal received by the receiver.
In a fifth aspect, an embodiment of the present application provides an electronic device, which includes the time measurement module according to the fourth aspect. The electronic equipment is any one or two or more of a smart phone, an unmanned aerial vehicle, a movable robot, an intelligent television, an AR/VR device and a 3D depth measuring device.
To sum up, the beneficial effects of this application are as follows:
the time measurement circuit of the embodiment of the application realizes the calibration of time measurement precision and the time measurement of measurement signals through the signal selection output module and the time measurement module. Under the condition of limited clock frequency lifting space, high-precision time measurement below picoseconds can be quickly realized, and under the current common process, the measurement precision of about 30ps can be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, without any inventive work, other drawings can be obtained according to the drawings, and these drawings are all within the scope of the present application.
Fig. 1 is a schematic structural diagram of a time measurement circuit in an embodiment of the present application.
Fig. 2 is a schematic diagram of a signal selection output module in an embodiment of the present application.
Fig. 3 is another schematic diagram of the signal selection output module in the embodiment of the present application.
Fig. 4 is a schematic diagram of a time measurement module in an embodiment of the present application.
Fig. 5 is another schematic diagram of the time measurement circuit in the embodiment of the present application.
Fig. 6 is a schematic diagram of a time measurement circuit in an embodiment of the present application.
Fig. 7 is another schematic diagram of a time measurement circuit in an embodiment of the present application.
Fig. 8 is a flowchart illustrating a time measurement method in an embodiment of the present application.
Fig. 9 is a waveform diagram illustrating a time interval between the acquisition of the first signal and the acquisition of the second signal in the time measurement method according to the embodiment of the present application.
Fig. 10 is a waveform diagram illustrating obtaining of time measurement accuracy in the time measurement method according to the embodiment of the present application.
Fig. 11 is a waveform diagram illustrating a time interval between acquiring a rising edge of a first signal and latching the rising edge of the first signal in the time measurement method according to the embodiment of the present application.
Fig. 12 is a schematic structural diagram of a time measurement chip according to an embodiment of the present application.
Fig. 13 is a schematic structural diagram of a time measurement module according to an embodiment of the present application.
Detailed Description
Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a time measurement circuit according to an embodiment of the present disclosure. As shown in fig. 1, an embodiment of the present application provides a time measurement circuit 10, where the time measurement circuit 10 includes: a signal selection output module 11 and a time measurement module 12.
The signal selection output module 11 is configured to receive the first signal, the second signal and the reference clock signal, and select an output measurement signal, where the measurement signal is one of the first signal, the second signal, the reference clock signal and the adjusted reference clock signal. The first signal and the second signal may be, for example, a rising edge signal from low level to high level, or may be, for example, a pulse signal from low level to high level to low level. In some embodiments, the first signal is an analog-to-digital converted Start signal sent by a TOF (Time Of Flight) ranging module transmitting end, and the second signal is an analog-to-digital converted Stop signal received by a TOF ranging module receiving end. Optionally, in some other embodiments, the first signal may also be the Stop signal, and the second signal may also be the Start signal, which is not specifically limited in this application. The reference clock signal may be a high-frequency pulse signal generated by a multi-phase ring oscillator, or may be other signals, which is not limited in this application. The receiving end of the signal selection output module 11 receives the first signal, the second signal and the reference clock signal, and selects any one of the first signal, the second signal, the reference clock signal or the adjusted reference clock signal to output to the time measurement module 12.
A time measuring module 12, configured to calibrate the time measurement accuracy and measure a time interval between the first signal and the second signal. When the signal received by the time measurement module 12 is a reference clock signal or an adjusted reference clock signal, performing time measurement precision measurement or calibration; when the received signal is first the first signal and then the second signal, or first the second signal and then the first signal, the time interval between the first signal and the second signal is measured. According to the method and the device, the resolution ratio (measurement precision) can be calibrated in real time in an idle state before measurement, and the error influence caused by different environmental temperatures and the like is reduced.
In one embodiment, as shown in fig. 2, the signal selection output module 11 includes: the first selection unit 111 and the second selection unit 112, wherein the first selection unit 111 is, for example, a two-input or gate in a logic circuit, but may also be other circuits having a signal selection input function, two input terminals of the first selection unit 111 are respectively used for receiving the first signal and the second signal, and an output terminal of the first selection unit 111 is used for connecting an input terminal of the second selection unit 112.
The second selection unit 112 is, for example, a two-input or gate in a logic circuit, and may of course be other circuits having a signal selection input function, where one input terminal of the second selection unit 112 is connected to the output terminal of the first selection unit 111, another input terminal of the second selection unit 112 receives the reference clock signal, and an output terminal of the second selection unit 112 is connected to an input terminal of the first delay unit (I1) of the delay chain.
In some embodiments, as shown in fig. 3, the signal selection output module 11 includes: a first selection unit 111, a second selection unit 112, a positive-negative pulse generation unit 114, and a scheduling unit 113. For the first selecting unit 111 and the second selecting unit 112, please refer to the description of fig. 2, which is not described herein again. The difference is that the input terminal of the positive/negative pulse generating unit 114 receives the reference clock signal, and the output terminal of the positive/negative pulse generating unit 114 is connected to one of the input terminals of the second selecting unit 112. The positive and negative pulse generating unit 114 is used to adjust the reference clock signal to a positive monocycle clock signal or a negative monocycle clock signal. The method and the device have the advantages that the delay chain of the inverter is calibrated by simultaneously using a positive single-period clock signal (positive pulse signal) and a negative single-period clock signal (negative pulse signal) in real time, so that the proportion of the delay value of a single inverter relative to the period of a single reference clock signal is calculated, and the influence of response error accumulation of a circuit which independently uses a positive pulse or a negative pulse is reduced.
The scheduling unit 113 is configured to control the positive-negative pulse generating unit 114 to adjust the input reference clock signal to the positive monocycle clock signal or the negative monocycle clock signal. The positive monocycle clock signal and the negative monocycle clock signal are input to the time measuring module 12 in a circulating manner for several times, so that the time measuring precision can be calibrated, more accurate time measuring precision can be obtained, and the accuracy of the time measuring result of the measuring signal can be improved.
In one embodiment, as shown in fig. 4, the time measuring module 12 comprises a delay chain 121 and a latch module 122, wherein the delay chain 121 is used for receiving the measuring signal from the signal selection output module 11, and the delay chain 121 comprises n delay units (I)1In), the first delay unit I of the delay chain 1211Is connected with the output end of the signal selection output module 11 and sequentially transfers the rising edge of the measurement signal from the first delay unit I1 to the nth delay unit In of the delay chain 121, where n is a positive integer greater than 2;
the latch module 122 is configured to latch the output signal of the delay chain 121, and the latch module 122 includes n latch units (D1-Dn), where each of the n latch units (D1-Dn) includes two input terminals, one input terminal of each latch unit is connected to the output terminal of one delay unit, and the other input terminal is configured to receive a reference clock signal.
The principle of using the delay chain 121 and the latch module 122 to perform time measurement is that a signal to be measured (a rising edge signal) is transmitted through the delay chain 121, the latch module 122 is triggered to latch a state value of the delay chain 121 at a rising edge of a first reference clock signal after the rising edge of the signal to be measured, a time difference between the signal to be measured and the rising edge of the first reference clock signal after the rising edge of the signal to be measured can be obtained by obtaining an output signal of the delay chain 121, and a signal delay time between each delay unit is a measured resolution.
In one embodiment, delay chain 121 includes several delay cells, which are preferably inverters. The current manufacturing process of the inverter can be in the order of 40nm, the minimum delay of the inverter can reach about 30ps under the manufacturing process, and the resolution (precision) of the whole time measuring circuit depends on the delay of the delay unit, so the precision of time measurement can reach about 30ps by using the inverter. In some embodiments, a Buffer cell may be used, but this problem is avoided by using an inverter because the Buffer cell has a different response delay to the rising or falling edge of the signal, thereby affecting the measurement result.
In one embodiment, the latch units in the latch module 122 are D flip-flops, one input terminal of each D flip-flop is connected to the output terminal of the delay unit, and the other input terminal of each D flip-flop receives the reference clock signal and is configured to latch the state values of the delay units at the time of a preset rising edge of the reference clock signal, or to know the time delay between the measurement signal transmitted along the delay chain and the preset rising edge of the reference clock signal according to the state values of the delay units.
In one embodiment, as shown in fig. 5, the time measuring circuit 10 further comprises a decoding module 13, and the decoding module 13 is connected to the latch module 122 in the time measuring module 12 for converting the output of the latch module 122 into binary data for reading.
Preferably, as shown in fig. 6, the structural schematic diagram of the time measurement circuit 10 is that two input ends of a first selection unit 111 in the signal selection output module 11 respectively receive a first signal and a second signal, and an output end of the first selection unit 111 is connected to an input end of a second selection unit 112; one input terminal of the second selection unit 112 is connected to the output terminal of the first selection unit 111, another input terminal of the second selection unit 112 receives the reference clock signal, and an output terminal of the second selection unit 112 is connected to the first delay unit I of the delay chain 1211To the input terminal of (1). The delay chain 121 comprises n delay units (I)1-In) Similarly, the latch module 122 includes n latch units (D)1-Dn) The output terminal of each delay unit in the delay chain 121 is connected to an input terminal of one latch unit in the latch module 122, and the output terminal of each latch unit in the latch module 122 is connected to the decoding module 13.
Preferably, as shown in fig. 7, the structural schematic diagram of the time measurement circuit 10 is that two input ends of a first selection unit 111 in the signal selection output module 11 respectively receive a first signal and a second signal, and an output end of the first selection unit 111 is connected to one input end of a second selection unit 112; the input end of the positive-negative pulse generating unit 114 receives a reference clock signal, and the output end of the positive-negative pulse generating unit 114 is connected with the other input end of the second selecting unit 112; the output of the second selection unit 112 is connected to the input of the first delay unit I1 of the delay chain 121. The delay chain 121 includes n delay units, and similarly, the latch module 122 includes n latch units, an output terminal of each delay unit in the delay chain 121 is connected to an input terminal of a D flip-flop in the latch module 122, and an output terminal of each latch unit in the latch module 122 is connected to the decoding module 13.
It should be noted that, in the embodiment of the present application, a value of n may be determined according to a measurement precision requirement of the time measurement module 12, and is not specifically limited herein.
In addition, the time measurement circuit 10 may be a dedicated integrated circuit, and the time measurement circuit 10 may be integrated in a Field Programmable Gate Array (FPGA) chip or an Application Specific Integrated Circuit (ASIC) chip, for example, which is not specifically limited in this embodiment of the present invention.
The embodiments of the time measurement circuit of the present application are described in detail above with reference to fig. 1 to 7, and the embodiments of a time measurement method proposed based on the time measurement circuit are described in detail below with reference to fig. 8, 9 and 10. It is to be understood that the description of the method embodiments of the present application correspond to the description of the device embodiments, and therefore reference may be made to the previous embodiments of the time measurement circuit for parts not described in detail.
Example two
Please refer to fig. 8, which is a schematic flow chart of a time measurement method according to an embodiment of the present application, where the method is implemented based on the time measurement circuit, and includes the following steps:
s1: acquiring the measurement precision of a time measurement circuit;
s2: according to the measurement precision, acquiring a first signal rising edge and a time interval between rising edges of first reference clock signals after the first signal rising edge, and recording the time interval as a first time interval;
s3: according to the measurement precision, acquiring a time interval between a second signal rising edge and a rising edge of a first reference clock signal after the second signal rising edge, recording the time interval as a second time interval, and acquiring the number of reference clock cycles between the rising edge of the first reference clock signal after the first signal rising edge and the rising edge of the first reference clock signal after the second signal rising edge;
s4: and acquiring the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of the reference clock cycles.
The principle of measuring the interval time between the first signal and the second signal by using the embodiment of the present application is shown in fig. 9, and the delay time between the first signal and the second signal can be calculated by the following formula (1):
△T＝N×Tclk+△Ta-△Tb (1)
in the above formula (1), Δ T is a time difference between a rising edge of the first signal and a rising edge of the second signal, Tclk is a clock period of the reference clock signal, N is a number of periods of the reference clock signal that are different between the first signal and the second signal, Δ Ta is a time difference between the rising edge of the first signal and a rising edge of a first reference clock signal after the rising edge of the first signal, and Δ Tb is a time difference between the rising edge of the second signal and a rising edge of a first reference clock signal after the rising edge of the second signal.
In one embodiment, the measurement of the delay time between the first signal and the second signal is performed using a time measurement circuit as described in fig. 6. Because the measurement accuracy (i.e. the measurement resolution) of the time measurement circuit depends on the delay size of the delay unit, the delay size of one delay unit is recorded as unit delay Tinv, and before calculating Δ T, the size of Tinv is calculated first. As shown in fig. 6, the signal selection output module 11 selects to input the reference clock signal into the delay chain 121, and at the same time, inputs the reference clock signal into the latch module 122, as shown in fig. 10, the first clock rising edge of the reference clock signal is sequentially transmitted from the first delay cell in the delay chain to the nth delay cell of the delay chain, and a unit delay is generated correspondingly for each first clock rising edge transmitted by one delay cell. The latch module 122 latches the state value of the corresponding delay unit when the second clock rising edge of the input reference clock signal arrives, and the decode module 13 obtains the number K of unit delays correspondingly generated by the first clock rising edge in a clock cycle after sequentially transmitting through the delay chain, and records the number K as the module value count of the clock cycle, where K is an integer greater than 0, so as to obtain the following formula (2)
In some embodiments, the ith rising edge of the reference clock signal is input into the delay chain, and the latch unit latches the state value of the delay unit when the jth rising edge of the reference clock signal arrives, wherein i and j are both natural numbers greater than or equal to 1. Obtaining, by the decoding module 13, a unit delay number K ' generated corresponding to an ith rising edge of the reference clock signal in one clock cycle, where K ' is an integer greater than 0, so as to obtain a formula (2 ') as follows:
after Tinv is acquired, the values of Δ Ta and Δ Tb are acquired, respectively.
When Δ Ta is measured, the signal selection output module 11 outputs a first signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, as shown in fig. 11, when a first reference clock signal rising edge (latch rising edge) after the first signal rising edge arrives, the latch delay chain 121 state value is latched, and the decoding module 13 obtains the unit delay number a from the first signal rising edge to the first reference clock signal rising edge after the first signal rising edge.
From equation (2), the following equation (3) can be obtained:
similarly, when Δ Tb is measured, the signal selection output module 11 outputs a second signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, and latches the state value of the delay chain 121 at the rising edge of the first reference clock signal after the rising edge of the second signal, and the decoding module 13 obtains the unit delay number B from the rising edge of the second signal to the rising edge of the first reference clock signal after the rising edge of the second signal.
From equation (2), the following equation (4) can be obtained:
further, in measuring Δ Tb, an integer number of clock cycle counts N included in the interval time between the first signal and the second signal can be obtained, and the following formula (5) can be obtained from formulas (1) (2) (3) (4):
it should be noted that, since each delay unit inevitably has a response error due to the influence of the manufacturing process or environmental factors, in order to reduce the influence of the accumulation of response errors when the same positive pulse signal or negative pulse signal is used alone, another embodiment of the present application as shown in fig. 7 adjusts the reference clock signal to a positive single-period clock signal or a negative single-period clock signal through the positive and negative pulse generating unit 114, and uses the positive single-period clock signal and the negative positive single-period clock signal several times in a cycle to calibrate the resolution of the time measuring circuit. The specific calibration process is as follows:
s101: inputting a positive single-period clock signal, and acquiring a first clock period modulus value count Np of the positive single-period clock signal;
s102: inputting a negative monocycle clock signal, and acquiring a first clock cycle modulus value count Nn of the negative monocycle clock signal;
s103: inputting a positive single-period clock signal, and acquiring a second clock period module value count Np' of the positive single-period clock signal;
s104: inputting a negative monocycle clock signal, and acquiring a second clock cycle module value count Nn' of the negative monocycle clock signal;
s105: when Np equals Np 'and Nn equals Nn', the calibration process ends;
when Np ≠ Np 'or Nn ≠ Nn', the steps S101-S104 are executed again until Np ≠ Np 'and Nn ═ Nn' then the calibration procedure ends;
when Np ≠ Np 'or Nn ≠ Nn', and the number of times of executing steps S101-S104 equals to the preset number of times, the calibration procedure is also ended, so as not to take too long to enter the calibration procedure. Preferably, the preset sub-value is 8.
After the calibration process is finished, the value of K is calculated, namely:
since Tinv is Tclk/K, the calibrated measurement accuracy Tinv can be obtained as:
when Δ Ta is measured, the signal selection output module 11 outputs a first signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, and latches the state value of the delay chain 121 when the rising edge of the first reference clock after the rising edge of the first signal arrives, and the decoding module 13 obtains the unit delay number a from the rising edge of the first signal to the rising edge of the first reference clock after the rising edge of the first signal, as shown in fig. 10.
From equation (7), equation (8) can be derived:
similarly, when Δ Tb is measured, the signal selection output module 11 outputs a second signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, and latches the state value of the delay chain 121 when the rising edge of the first reference clock after the rising edge of the second signal arrives, and the decoding module 13 obtains the unit delay number B from the rising edge of the second signal to the rising edge of the first reference clock after the rising edge of the second signal.
As can be obtained from the equation (2),
further, in measuring Δ Tb, an integer number of clock cycle counts N included in the interval time between the first signal and the second signal can be obtained according to equations (1) (6) (8) (9):
to sum up, the time measurement circuit according to the embodiment of the present application realizes the calibration of the time measurement accuracy and the time measurement of the measurement signal through the signal selection output module 11 and the time measurement module 12. On one hand, in the embodiment of the present application, the reference clock signal is input into the delay chain 121 to obtain the time measurement precision, and further, the positive and negative pulse generating units 114 generate the positive monocycle clock signal and the negative monocycle clock signal to calibrate the time measurement precision, so as to obtain a more accurate time measurement result. The calibration of the time measurement accuracy may be performed in an idle state before the time measurement of the first signal and the second signal is measured, which may not only improve the measurement accuracy but also reduce the error influence caused by different environmental temperatures, etc. On the other hand, the time measuring circuit 10 selects an appropriate amount of delay cells (I)1In) to form the delay chain 121, so as to avoid the problem that the integer counting of the time period of the reference clock signal cannot cover the measurement time range, thereby causing large errors. Furthermore, the inverter with a small delay value is selected as the delay unit, and the frequency of the reference clock signal can be correspondingly reduced by using a sufficient number of delay units, so that the purpose of reducing power consumption is achieved. By using inverters instead of Buffer cells to reduce the sum of rising edges of signals due to Buffer cellsThe influence caused by different response delays of the falling edge can quickly realize picosecond-level high-precision time measurement, and the measurement precision of about 30ps can be realized under the current manufacturing process.
EXAMPLE III
The embodiment of the present application further provides a time measurement chip 30. As shown in fig. 12, the time measurement chip 30 includes the time measurement circuit 10 described above and an analog-to-digital conversion circuit 31 for converting the analog signal received by the chip into a digital signal and inputting the digital signal into the time measurement circuit 10 for time measurement. For a detailed description of the time measuring circuit 10, reference is made to the foregoing embodiments 1 and 2, which are not repeated herein.
Example four
The embodiment of the present application further provides a time measuring module 40. As shown in fig. 13, the time measuring module 40 includes a transmitter 41, a receiver 42, and the time measuring chip 30 shown in fig. 13. The emitter 41 is used to emit a detection signal, such as an infrared or near-infrared light signal, or other visible light signal. The receiver 42 receives a reflected signal corresponding to the detection signal, and the reflected signal is an analog signal. The time measurement chip 30 is connected to the transmitter 41 and the receiver 42, receives analog signals from the transmitter 41 and the receiver 42, then the time measurement chip 30 converts them into digital signals, the time interval between the detection signal transmitted by the transmitter 41 and the reflected signal corresponding to the detection signal received by the receiver 42 is measured by the time measurement circuit 10, and then the distance to the target object is obtained from the time interval. For a detailed description of the time measurement chip 30, refer to the third embodiment, which is not repeated herein.
EXAMPLE five
The embodiment of the present application further provides an electronic device, which includes the time measurement module 40 as described in the fourth embodiment. This electronic equipment can be smart mobile phone, unmanned aerial vehicle, mobile robot, smart television, AR/VR, 3D degree of depth measuring equipment etc. through the time of flight measurement module 40 of this application, can realize the accurate measurement to the degree of depth information of target object.
In summary, the time measurement circuit, the time measurement method, the time measurement chip, the time measurement module, and the electronic device provided in the embodiments of the present application can implement high-precision time measurement below picosecond under the existing technical condition of limited clock frequency promotion space, and can implement measurement precision of about 30ps under the currently common process.
It is to be understood that the present application is not limited to the particular arrangements and instrumentalities described above and shown in the attached drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions or change the order between the steps after comprehending the spirit of the present application.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranets, etc.
It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.
As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.
Claims (12)
1. A time measurement circuit, the circuit comprising:
the signal selection output module is used for receiving a first signal, a second signal and a reference clock signal and selecting and outputting a measurement signal, wherein the measurement signal is one of the first signal, the second signal, the reference clock signal and an adjusted reference clock signal;
and the time measuring module is used for calibrating the time measuring precision and measuring the time interval between the first signal and the second signal.
2. The time measurement circuit of claim 1, wherein the time measurement module comprises:
the delay chain is used for receiving the measurement signal from the signal selection output module, and comprises n delay units which are sequentially connected, wherein a first delay unit of the delay chain is connected with the output end of the signal selection output module, and the rising edge of the measurement signal is sequentially transmitted to an nth delay unit of the delay chain from the first delay unit, wherein n is a positive integer greater than 2;
and the latch module is used for latching the output signal of the delay chain, wherein the latch module at least comprises n latch units, one input end of two input ends of each latch unit is connected with the output end of one delay unit, and the other input end of each latch unit is used for receiving the reference clock signal.
3. The time measurement circuit of claim 2, wherein the signal selection output module comprises: a first selection unit, a second selection unit, wherein,
two input ends of the first selection unit are respectively used for receiving the first signal and the second signal, and an output end of the first selection unit is connected with an input end of the second selection unit;
one input end of the second selection unit is connected to the output end of the first selection unit, the other input end of the second selection unit is used for receiving the reference clock signal, and the output end of the second selection unit is connected to the input end of the first delay unit in the delay chain.
4. The time measurement circuit of claim 2, wherein the signal selection output module comprises: a first selection unit, a second selection unit, a positive and negative pulse generation unit, a scheduling unit,
two input ends of the first selection unit respectively receive the first signal and the second signal, and an output end of the first selection unit is connected with an input end of the second selection unit;
one input end of the second selection unit is connected with the output end of the first selection unit, the other input end of the second selection unit is connected with the output end of the positive and negative pulse generation unit, and the output end of the second selection unit is connected with the input end of the first delay unit of the delay chain;
the input end of the positive and negative pulse generating unit receives the reference clock signal, and the output end of the positive and negative pulse generating unit is connected with one input end of the second selecting unit; the positive and negative pulse generating unit is used for generating a positive monocycle clock signal or a negative monocycle clock signal;
and the scheduling unit is used for controlling the positive and negative pulse generating unit to adjust the input reference clock signal into the positive monocycle clock signal or the negative monocycle clock signal.
5. The time measurement circuit according to any one of claims 2-4, wherein the time measurement circuit further comprises:
and the decoding module is connected with the latch module and is used for converting the output signal of the latch module into binary data convenient for reading.
6. The time measurement circuit of any of claims 2-4, wherein the delay element is an inverter.
7. The time measurement circuit of claim 6, wherein the latch unit is a D flip-flop.
8. A time measurement method based on the time measurement circuit according to any one of claims 1 to 7, characterized in that the method comprises:
s1: acquiring the measurement precision of the time measurement circuit;
s2: according to the measurement precision, acquiring a first signal rising edge and a time interval between the first signal rising edge and a first reference clock rising edge after the first signal rising edge, and recording as a first time interval;
s3: according to the measurement precision, acquiring a second signal rising edge and a time interval between the second signal rising edge and a first reference clock rising edge after the second signal rising edge, and recording as a second time interval;
s4: acquiring the number of reference clock periods between a first reference clock rising edge after the first signal rising edge and a first reference clock rising edge after the second signal rising edge;
s5: and acquiring the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of the reference clock cycles.
9. The time measurement method according to claim 8, further comprising, before the obtaining the measurement accuracy of the time measurement circuit: calibrating the measurement accuracy, specifically comprising:
s101: inputting the positive single-period clock signal, and acquiring a first clock period modulus value count Np of the positive single-period clock signal;
s102: inputting the negative monocycle clock signal, and acquiring a first clock cycle modulus value count Nn of the negative monocycle clock signal;
s103: inputting the positive single-period clock signal, and acquiring a second clock period modulus value count Np' of the positive single-period clock signal;
s104: inputting the negative monocycle clock signal, and acquiring a second clock cycle modulus value count Nn' of the negative monocycle clock signal;
s105: when Np equals Np 'and Nn equals Nn', the calibration ends;
when Np ≠ Np 'or Nn ≠ Nn', executing steps S101-S104 until Np ≠ Np 'and Nn ≠ Nn', the calibration is finished;
when Np ≠ Np 'or Nn ≠ Nn' and the number of times of executing steps S101 to S104 equals to the preset number of times, the calibration ends.
10. A time measurement chip, characterized in that the time measurement chip comprises:
a time measurement circuit according to any one of claims 1-7; and
and the analog-to-digital conversion circuit is used for converting the analog signal into a digital signal and inputting the digital signal to the time measurement circuit.
11. A time measurement module, the module comprising:
a transmitter for transmitting a detection signal;
the receiver is used for receiving a reflected signal corresponding to the detection signal; and the number of the first and second groups,
the time measurement chip of claim 10, wherein the time measurement chip is coupled to the transmitter and the receiver, and is configured to measure a time interval between a detection signal transmitted by the transmitter and a reflected signal corresponding to the detection signal received by the receiver.
12. An electronic device, characterized in that it comprises a time measuring module according to claim 11.
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