CN114775063A - Process for improving single crystal RRV and resistivity - Google Patents
Process for improving single crystal RRV and resistivity Download PDFInfo
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- CN114775063A CN114775063A CN202210060824.2A CN202210060824A CN114775063A CN 114775063 A CN114775063 A CN 114775063A CN 202210060824 A CN202210060824 A CN 202210060824A CN 114775063 A CN114775063 A CN 114775063A
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- 239000013078 crystal Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 17
- 230000008569 process Effects 0.000 title claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 238000002474 experimental method Methods 0.000 claims abstract description 17
- 238000012360 testing method Methods 0.000 claims abstract description 13
- 238000012545 processing Methods 0.000 claims abstract description 10
- 238000007689 inspection Methods 0.000 claims abstract description 5
- 230000006872 improvement Effects 0.000 claims description 5
- 238000010835 comparative analysis Methods 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 abstract description 13
- 238000004857 zone melting Methods 0.000 abstract description 5
- 229940095676 wafer product Drugs 0.000 description 9
- 238000001035 drying Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
- C30B15/02—Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt
- C30B15/04—Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n-p-junction
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
- C30B15/20—Controlling or regulating
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention discloses a process for improving single crystal RRV and resistivity, which comprises the following steps: s1, firstly, selecting a furnace platform with better stability for testing, and adjusting the internal and external conditions and related parameters of the furnace platform in real time to ensure that the furnace platform can meet the specified conditions required by the test, selecting the semiconductor silicon chip products with corresponding dimensions in real time, and processing the selected semiconductor silicon chip products in real time through the fixed furnace platform; s2, processing the semiconductor silicon chip product to a certain thickness in real time, carrying out single crystal drawing by using a fixed furnace platform, and selecting an appropriate section for slice 4PP inspection; s3, the first set of experiments is set to adjust the position of the doped pipe. In terms of electrical parameters, the phenomena that the part with the clamping RRV less than or equal to 12 percent is larger than 85 percent and the resistivity is less than or equal to 33ohm-cm are improved in a 4PP test mode, the RRV and the resistivity of zone-melting single crystals can be effectively improved, and the market competitiveness of 200mm silicon wafers can be effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a process for improving single crystal RRV and resistivity.
Background
The global shipment volume and market scale of the semiconductor silicon wafer are greatly influenced by the downstream semiconductor industry, the market scale of the semiconductor silicon wafer industry is expected to recover and increase under the pulling of the semiconductor industry, from the current capacity construction situation of the global wafer factory, the 200mm wafer factory is still the main profit direction, products with high specification and high requirement are strong competitive objects of the market, the existing semiconductor silicon wafer products are poor in zone-melting single crystal RRV and resistivity, and an effective method is lacked for substantial improvement at present.
Disclosure of Invention
The invention aims to provide a process for improving single crystal RRV and resistivity, and aims to solve the problems that the existing semiconductor silicon wafer product provided by the background technology has very poor zone-melting single crystal RRV and resistivity, and an effective method is not available for substantial improvement at present.
In order to achieve the purpose, the invention provides the following technical scheme: a process for improving single crystal RRV and resistivity, the improvement process comprising the steps of:
s1, firstly, selecting a furnace platform with good stability for testing, and adjusting the internal and external conditions and related parameters of the furnace platform in real time, so that the furnace platform can meet the specified conditions required by the test, selecting semiconductor silicon chip products with corresponding dimensions in real time, and processing the selected semiconductor silicon chip products in real time through the fixed furnace platform; s2, processing the semiconductor silicon wafer product to a certain thickness in real time, carrying out single crystal drawing by using a fixed furnace platform, and selecting an appropriate section to carry out slice 4PP inspection; s3, setting the first group of experiments to adjust the position of the doping pipe, setting the second group of experiments to adjust the position of the doping pipe and additionally reduce the concentration of the central airflow, setting the third group of experiments to adjust the position of the doping pipe and additionally reduce the concentration of the central airflow and further reduce the pulling speed, and finally carrying out real-time comparative analysis on the experimental data.
Preferably, the thickness of the semiconductor silicon wafer product to be processed is 725 micrometers, and the diameter of the selected semiconductor silicon wafer product is 200 mm.
Preferably, the model of the single crystal pulling fixed furnace platform is TDR-70A/B, and the temperature and the time for pulling the single crystal can be set according to the actual experiment requirements.
Preferably, the drying temperature of the high-temperature drying 1 for the wafer box is 60-70 ℃, and the time for the wafer box to pass through high-speed forward rotation and reverse rotation is 240-360 seconds.
Preferably, the temperature for drying at the medium and high temperature is 55-65 ℃, and the wafer box is alternately rotated at high speed and low speed in the forward direction and the reverse direction for 90-150 s.
Preferably, the high-low temperature alternate drying wafer box is dried at the high-speed drying temperature and time of 55-65 ℃ and 50-70s respectively, and the wafer box is dried at the low-speed drying temperature and time of 10-30 ℃ and 90-150s respectively.
Compared with the prior art, the invention has the beneficial effects that: in terms of electrical parameters, the phenomena that the part with the clamping RRV less than or equal to 12 percent is larger than 85 percent and the resistivity is less than or equal to 33ohm-cm are improved in a 4PP test mode, the RRV and the resistivity of zone-melting single crystals can be effectively improved, and the market competitiveness of 200mm silicon wafers can be effectively improved.
Drawings
FIG. 1 is a diagram of adjusting the position of a doped tube according to the present invention
FIG. 2 is a graph of the doping tube position adjustment + center gas flow concentration reduction according to the present invention
FIG. 3 is a graph of adjusting the position of the doped pipe, decreasing the center gas flow concentration, and decreasing the pull rate according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1-3, the improved process of the present embodiment includes the following steps:
s1, firstly, selecting a furnace platform with good stability for testing, and adjusting the internal and external conditions and related parameters of the furnace platform in real time, so that the furnace platform can meet the specified conditions required by the test, selecting semiconductor silicon chip products with corresponding dimensions in real time, and processing the selected semiconductor silicon chip products in real time through the fixed furnace platform; s2, processing the semiconductor silicon wafer product to a certain thickness in real time, carrying out single crystal drawing by using a fixed furnace platform, and selecting an appropriate section to carry out slice 4PP inspection; s3, setting the first group of experiments to adjust the position of the doping pipe, setting the second group of experiments to adjust the position of the doping pipe and additionally reduce the concentration of the central airflow, setting the third group of experiments to adjust the position of the doping pipe and additionally reduce the concentration of the central airflow and further reduce the pulling speed, and finally carrying out real-time comparative analysis on the experimental data.
In this embodiment, the thickness of the semiconductor silicon wafer product to be processed is 725 μm, and the diameter of the selected semiconductor silicon wafer product is 200 mm.
In the embodiment, the model of the single crystal pulling fixed furnace platform is TDR-70A/B, and the temperature and time for pulling the single crystal can be set according to actual experiment needs.
The experimental result shows that the phenomena that the part with the card-controlled RRV less than or equal to 12 percent is more than 85 percent and the resistivity is less than or equal to 33ohm-cm are improved in the 4PP test mode in terms of electrical parameters.
Example two:
the difference characteristic from the first embodiment is that:
the improvement process of the embodiment comprises the following steps:
s1, firstly, selecting a furnace platform with good stability for testing, and adjusting the internal and external conditions and related parameters of the furnace platform in real time, so that the furnace platform can meet the specified conditions required by the test, selecting semiconductor silicon chip products with corresponding dimensions in real time, and processing the selected semiconductor silicon chip products in real time through the fixed furnace platform; s2, processing the semiconductor silicon chip product to a certain thickness in real time, carrying out single crystal drawing by using a fixed furnace platform, and selecting an appropriate section for slice 4PP inspection; s3, setting the first group of experiments as the position of the doping pipe, setting the second group of experiments as the position of the doping pipe and additionally reducing the central airflow concentration, setting the third group of experiments as the position of the doping pipe and additionally reducing the central airflow concentration and then reducing the pulling speed, and finally carrying out real-time comparative analysis on the experimental data.
In this embodiment, the thickness of the semiconductor silicon wafer product to be processed is 500 μm, and the diameter of the selected semiconductor silicon wafer product is 100 mm.
In the embodiment, the model of the single crystal pulling fixed furnace platform is JRDL-800, and the temperature and the time for pulling the single crystal can be set according to the actual experiment requirements.
To sum up: the experimental results of the invention in the first embodiment of the invention show that compared with the experimental results of the second embodiment of the invention, the invention can more effectively improve the RRV and the resistivity of the zone-melting single crystal and more effectively improve the market competitiveness of the 200mm silicon wafer.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (3)
1. A process for improving single crystal RRV and resistivity is characterized in that: the improvement process comprises the following steps:
s1, firstly, selecting a furnace platform with good stability for testing, and adjusting the internal and external conditions and related parameters of the furnace platform in real time, so that the furnace platform can meet the specified conditions required by the test, selecting semiconductor silicon chip products with corresponding dimensions in real time, and processing the selected semiconductor silicon chip products in real time through the fixed furnace platform; s2, processing the semiconductor silicon chip product to a certain thickness in real time, carrying out single crystal drawing by using a fixed furnace platform, and selecting an appropriate section for slice 4PP inspection; s3, setting the first group of experiments to adjust the position of the doping pipe, setting the second group of experiments to adjust the position of the doping pipe and additionally reduce the concentration of the central airflow, setting the third group of experiments to adjust the position of the doping pipe and additionally reduce the concentration of the central airflow and further reduce the pulling speed, and finally carrying out real-time comparative analysis on the experimental data.
2. The process of claim 1 for improving single crystal RRV and resistivity, wherein: the thickness of the semiconductor silicon chip product to be processed is 725 micrometers, and the diameter of the selected semiconductor silicon chip product is 200 mm.
3. The process of claim 1, wherein the RRV and resistivity of the single crystal are improved by: the model of the single crystal pulling fixed furnace platform is TDR-70A/B, and the temperature and time for pulling the single crystal can be set according to the actual experiment requirements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210060824.2A CN114775063A (en) | 2022-01-19 | 2022-01-19 | Process for improving single crystal RRV and resistivity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210060824.2A CN114775063A (en) | 2022-01-19 | 2022-01-19 | Process for improving single crystal RRV and resistivity |
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| Publication Number | Publication Date |
|---|---|
| CN114775063A true CN114775063A (en) | 2022-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210060824.2A Pending CN114775063A (en) | 2022-01-19 | 2022-01-19 | Process for improving single crystal RRV and resistivity |
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| Country | Link |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5862057A (en) * | 1996-09-06 | 1999-01-19 | Applied Materials, Inc. | Method and apparatus for tuning a process recipe to target dopant concentrations in a doped layer |
| CN108411357A (en) * | 2018-04-13 | 2018-08-17 | 天津市环欧半导体材料技术有限公司 | A kind of doper and method improving zone-melted vapor doping stability |
-
2022
- 2022-01-19 CN CN202210060824.2A patent/CN114775063A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5862057A (en) * | 1996-09-06 | 1999-01-19 | Applied Materials, Inc. | Method and apparatus for tuning a process recipe to target dopant concentrations in a doped layer |
| CN108411357A (en) * | 2018-04-13 | 2018-08-17 | 天津市环欧半导体材料技术有限公司 | A kind of doper and method improving zone-melted vapor doping stability |
Non-Patent Citations (1)
| Title |
|---|
| 郭丽华: "硅单晶汽相掺杂技术的研究", 《中国优秀硕士学位论文全文数据库 工程科技Ⅰ辑》 * |
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Application publication date: 20220722 |