CN114731112A

CN114731112A - Buck switching power supply, electronic equipment and control method

Info

Publication number: CN114731112A
Application number: CN202080043758.7A
Authority: CN
Inventors: 张均军
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2020-09-07
Filing date: 2020-09-07
Publication date: 2022-07-08
Also published as: WO2022047795A1

Abstract

A step-down switching power supply and electronic equipment relate to the technical field of switching power supplies, and can use a transistor under a new process as a power transistor and reduce the risk that the power transistor is broken down and damaged. The step-down switching power supply includes: a first power transistor (T1), the first power transistor (T1) being a P-type laterally double diffused transistor; a second power transistor (T2), the second power transistor (T2) being an N-type lateral double diffused transistor; the power transistor driving circuit (1) is used for outputting a first control signal (PDRV) to a grid electrode of a first power transistor (T1) and outputting a second control signal (NDRV) to a grid electrode of a second power transistor (T2), wherein the low voltage of the first control signal (PDRV) is a voltage larger than 0V, and the high voltage of the second control signal (NDRV) is smaller than the voltage of a power supply input end (VBAT).

Description

Buck switching power supply, electronic equipment and control method

Technical Field

The application relates to the technical field of switching power supplies, in particular to a step-down switching power supply applied to a lithium battery in an advanced process, electronic equipment and a control method.

Background

The BUCK (BUCK) switching power supply is a commonly used power conversion circuit, has high conversion efficiency, and is widely applied to chips powered by lithium batteries. However, the normal discharge range of the lithium battery is 2.7-4.4V, and the power supply chip of the lithium battery needs to bear higher voltage. As shown in fig. 1, fig. 1 is a partial structural schematic diagram of a BUCK switching power supply in the prior art, where the conventional BUCK switching power supply includes two 5V voltage-tolerant output power transistors, where a first power transistor T1 is a P-type Metal Oxide Semiconductor (MOS) transistor, referred to as PMOS for short, a second power transistor T2 is NMOS, a first power transistor T1 and a second power transistor T2 are connected in series between a power input terminal VBAT and a ground terminal, a first power transistor T1 and a second power transistor T2 are connected to a SW node, and the first power transistor T1 and the second power transistor T2 are sequentially turned on to change a potential of the SW node and a duty ratio of high and low levels, and are filtered by an inductor L and a capacitor C, so that a converted voltage is output at a power output terminal VBK.

The use of 5V devices with line widths of 40nm or more in advanced processes presents design challenges. On one hand, the threshold voltage of the 5V voltage-resistant transistor is high, and the performance is poor when the transistor is used for designing other analog circuits; if a 5V voltage-resistant device is added separately, the mask cost and the manufacturing cost are increased additionally. On the other hand, advanced technologies usually include a 3.3V withstand voltage IO transistor, but direct application to lithium battery power supply risks breakdown and damage.

Disclosure of Invention

The technical scheme of the application provides a step-down switching power supply, electronic equipment and a control method, a transistor under a new process can be applied as a power transistor, and the risk that the power transistor is broken down and damaged is reduced.

In a first aspect, the present application provides a buck switching power supply, including:

the first power transistor is connected between the power supply input end and the switching node in series, and the first power transistor is a P-type transverse double-diffusion transistor;

the second power transistor is connected between the switching node and a grounding end in series, and the second power transistor is an N-type transverse double-diffused transistor;

the output inductor is connected between the switching node and the power supply output end in series;

the output capacitor is connected between the power output end and the grounding end in series;

the power transistor driving circuit is electrically connected to the grid of the first power transistor and the grid of the second power transistor, and is used for outputting a first control signal to the grid of the first power transistor and outputting a second control signal to the grid of the second power transistor, wherein the low voltage of the first control signal is a voltage greater than 0V, and the high voltage of the second control signal is less than the voltage of the power supply input end.

In a second aspect, the present application further provides an electronic device, including the buck switching power supply.

In a third aspect, a technical solution of the present application further provides a control method for the buck switching power supply, where the buck switching power supply further includes: a precharge circuit, the control method comprising:

in a starting stage, the first power transistor is controlled to be turned off, and the pre-charging circuit is controlled to charge the power supply output end;

after the start-up phase is finished, the first power transistor is controlled to be switched between the on state and the off state in response to the first control signal, the second power transistor is controlled to be switched between the on state and the off state in response to the second control signal, and the pre-charging circuit is controlled to stop working.

In the buck switching power supply, the electronic device and the control method in the embodiment of the application, two power transistors are set as the LDMOS to improve the voltage bearing capacity between a source electrode and a drain electrode, in order to save the process cost, the LDMOS and other devices in a more advanced process have the same oxide layer thickness, so the gate withstand voltage of the LDMOS is lower, on the basis, the low level of a first control signal for controlling the conduction of the first power transistor is further set to be higher than 0V, the high level of a second control signal for controlling the conduction of the second power transistor is set to be lower than the voltage of a power input end to reduce the gate-source voltage difference of the power transistors, namely, the risk that the power transistors are broken down due to the higher gate-source voltage difference is reduced, namely, when the two power transistors are set as the LDMOS, the low level of the first control signal for controlling the conduction of the first power transistor is set to be higher than 0V, the high level of the second control signal for controlling the conduction of the second power transistor is lower than the voltage of the power input end, so that the lithium battery environment can be applied, and the cost is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a schematic diagram of a part of a BUCK switch power supply in the prior art;

fig. 2 is a schematic structural diagram of a buck switching power supply in an embodiment of the present application;

FIG. 3a is a schematic diagram of two power transistors shown in FIG. 2;

FIG. 3b is a timing diagram according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a power transistor driving circuit shown in FIG. 2;

FIG. 5 is a schematic diagram of a first level shifter circuit shown in FIG. 4;

FIG. 6 is a schematic diagram of a soft-start boost circuit of FIG. 4;

FIG. 7 is a schematic diagram of a second level shifter circuit shown in FIG. 4;

FIG. 8 is another timing diagram of an embodiment of the present application.

Detailed Description

The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.

As shown in fig. 2, fig. 2 is a schematic structural diagram of a buck switching power supply in an embodiment of the present application, and an embodiment of the present application provides a buck switching power supply, including: a first power transistor T1 connected in series between the power input terminal VBAT and the switching node SW, the first power transistor T1 being a P-type lateral-double-diffused transistor (LDMOS), abbreviated as LDPMOS; a second power transistor T2 connected in series between the switching node SW and the ground terminal, the second power transistor T2 being an N-type lateral double-diffused transistor, abbreviated as LDNMOS; the output inductor L is connected between the switching node SW and the power output end VBK in series; the output capacitor C is connected between the power output end VBK and the grounding end in series; a power transistor driving circuit 1 electrically connected to the gate of the first power transistor T1 and the gate of the second power transistor T2, wherein the power transistor driving circuit 1 is configured to output a first control signal PDRV to the gate of the first power transistor T1 and a second control signal NDRV to the gate of the second power transistor T2, the low voltage of the first control signal PDRV is Vbk, Vbk > 0V, i.e., the low voltage of PDRV is a voltage greater than 0V, the high voltage of the second control signal NDRV is Vbk, Vbk is smaller than the voltage of the power input terminal VBAT, i.e., the high voltage of NDRV is smaller than the voltage of the power input terminal VBAT, the high voltage of the first control signal PDRV may be, for example, the voltage of the power input terminal VBAT, the low voltage of the second control signal NDRV may be, for example, 0V, in this embodiment, the high voltage of the second control signal is not necessarily equal to the low voltage of the first control signal, the present embodiment is described by taking an example in which the high voltage of the second control signal is equal to the low voltage of the first control signal. The active level in the first control signal PDRV and the active level in the second control signal NDRV do not overlap in turn-on time even though the first power transistor T1 and the second power transistor T2 are not simultaneously turned on.

Specifically, as shown in fig. 2 and fig. 3a, fig. 3a is a schematic structural diagram of two power transistors in fig. 2, since both the two power transistors are LDMOS, and the second power transistor T2 is provided with an N-well (NW) on the side of the drain D, so that the second power transistor T2 can withstand a larger voltage (e.g., 5V voltage) between the drain D and the source S, that is, the second power transistor T2 can be manufactured by applying a newer process, and at the same time, the risk of being damaged by the breakdown voltage between the source S and the drain D is reduced; similarly, the first power transistor T1 is provided with a P-well (PW) on the side of the drain D so that it can withstand a large voltage between the drain D and the source S. The substrate electrode Sub and the source electrode S of the second power transistor T2 are grounded, the gate G of the second power transistor T2 is electrically connected to the power transistor driving circuit 1, the drain D of the second power transistor T2 is electrically connected to the source electrode S of the first power transistor T1, the drain D and the substrate electrode Sub of the first power transistor T1 are electrically connected to the power supply input terminal VBAT, the source S and the drain D of the first power transistor T1 are P + doped, the substrate electrode Sub is N + doped, the source S and the drain D of the second power transistor T2 are N + doped, and the substrate electrode Sub is P + doped, in addition, the first power transistor T1 has one more Deep N well (Deep NWell, DNW) compared with the prior art, otherwise it cannot be isolated from the substrate electrode Sub. Although the voltage that can be borne between the source and drain electrodes of the two power transistors is increased, the gate G of the power transistor has a low withstand voltage, so that the power transistor can still be broken down when the voltage difference between the gate and the source of a certain power transistor is high. Therefore, in the embodiment of the present application, the low voltage of the first control signal is higher than 0V, instead of 0V in the prior art, to reduce the gate-source voltage difference of the first power transistor T1, and similarly, the high voltage of the second control signal is lower than the voltage of the power input terminal VBAT to reduce the gate-source voltage difference of the second power transistor T2. The buck switching power supply further includes a regulator 2, where the regulator 2 is configured to generate a pulse signal through Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), Pulse Skip Modulation (PSM), constant on time modulation (COT), or hysteretic control, and output the pulse signal to the power transistor driving circuit 1, the power transistor driving circuit 1 is configured to generate the first control signal PDRV and the second control signal NDRV according to the pulse signal, and control an effective level in the first control signal PDRV and an effective level in the second control signal NDRV to be non-overlapped, where the effective level in the first control signal PDRV is a level that controls the first power transistor T1 to be turned on, for example, the first power transistor T1 is PMOS, that is, the effective level in the first control signal PDRV is a low level, the active level in the second control signal NDRV refers to a level for controlling the second power transistor T2 to be turned on, for example, the second power transistor T2 is NMOS, that is, the active level in the second control signal NDRV is high level, in order to ensure the normal operation of the buck-type switching power supply, it is required to ensure that the first power transistor T1 and the second power transistor T2 cannot be turned on simultaneously, that is, the active level in the first control signal PDRV and the active level in the second control signal NDRV are controlled by the power transistor driving circuit 1 to have no overlap, that is, the active level in the first control signal PDRV and the active level in the second control signal NDRV do not occur simultaneously, for example, the inactive level in the first control signal PDRV may be the voltage of the power supply input terminal VBAT, the active level in the first control signal PDRV may be the voltage of the auxiliary voltage terminal VDNW, as shown in fig. 3b, fig. 3b is a timing signal diagram in an embodiment of the present application, assuming that a high level 3.3V in the first control signal PDRV is an inactive level, a low level 1.8V in the first control signal PDRV is an active level, a high level 1.8V in the second control signal NDRV is an active level, and a low level 0V is an inactive level, where no overlap between the active level in the first control signal PDRV and the active level in the second control signal NDRV means that the 1.8V level in the first control signal PDRV and the 1.8V level in the second control signal NDRV do not occur simultaneously.

In the buck switching power supply in the embodiment of the application, two power transistors are set as the LDMOS to improve the voltage bearing capacity between the source and the drain, in order to save the process cost, the LDMOS and other devices in the advanced process have the same oxide layer thickness, therefore, the gate voltage endurance of the LDMOS is low, on this basis, the low level of the first control signal for controlling the conduction of the first power transistor is further set to be higher than 0V, the high level of the second control signal for controlling the conduction of the second power transistor is set to be lower than the voltage of the power input end to reduce the gate-source voltage difference of the power transistors, that is, the risk that the power transistors are broken down due to the higher gate-source voltage difference is reduced, that is, when the two power transistors are set as the LDMOS, the low level of the first control signal for controlling the conduction of the first power transistor is set to be higher than 0V, the high level of the second control signal for controlling the conduction of the second power transistor is lower than the voltage of the power input end, so that the lithium battery environment can be applied, and the cost is reduced.

Alternatively, as shown in fig. 4, fig. 4 is a schematic structural diagram of a power transistor driving circuit in fig. 2, and the power transistor driving circuit 1 includes: a control circuit 10, the control circuit 10 includes a signal input terminal In, a first signal output terminal U1, a signal feedback terminal B, and a second signal output terminal U2, the signal input terminal of the control circuit 10 is used for receiving the pulse signal generated by the regulator 2, the control circuit 10 outputs a first Pre-control signal Pre _ PDRV through a first signal output terminal U1, and outputs a second control signal NDRV through a second signal output terminal U2, as shown In fig. 3B, the pulse timing of the first Pre-control signal Pre _ PDRV is the same as the pulse timing of the first control signal PDRV, that is, the pulse period of the first Pre-control signal Pre _ PDRV is the same as the pulse period of the first control signal PDRV, the first control signal PDRV is slightly delayed with respect to the first Pre-control signal Pre _ PDRV, the delay is generated by the boost conversion process of the first level conversion circuit 11, the voltage of the first Pre-control signal Pre _ PDRV is smaller than the voltage of the first control signal PDRV, for example, the level states of the first Pre-control signal Pre _ PDRV are 1.8V (high), 0V (low), 1.8V (high), and 0V (low), the level states of the first control signal PDRV after a short delay are 3.3V (high), 1.8V (low), 3.3V (high), and 1.8V (low), and the first Pre-control signal Pre _ PDRV is a pulse signal composed of 1.8V and 0V, so 1.8V is a high level state, 0V is a low level state, and the first control signal PDRV is a pulse signal composed of 3.3V and 1.8V, so 3.3V is a high level state, 1.8V is a low level state, that is, the pulse timing of the two signals is the same, but the voltage amplitudes of the two signals are different; the input end of the first level shift circuit 11 is electrically connected to the first signal output end U1 of the control circuit 10, the output end of the first level shift circuit 11 is electrically connected to the gate of the first power transistor T1, and the first level shift circuit 11 is configured to perform voltage boosting conversion on the first Pre-control signal Pre _ PDRV and output the first control signal PDRV.

Specifically, in order to increase the low voltage of the first control signal PDRV, a first Pre-control signal Pre _ PDRV may be generated by the control circuit 10, for example, the voltage of the first Pre-control signal Pre _ PDRV is 0V to Vbk, then the first level shifter 11 boosts Pre _ PDRV and outputs the boosted first control signal PDRV, the voltage of PDRV is Vbk to Vbat, Vbat is the voltage of the power input terminal Vbat, Vbk is the active level for controlling the first power transistor T1 to be turned on, and Vbat is the inactive level for controlling the first power transistor T1 to be turned off.

Alternatively, as shown in fig. 4, the power transistor driving circuit 1 further includes a second level shifter circuit 12, an input terminal of the second level shifter circuit 12 is electrically connected to an output terminal of the first level shifter circuit 11, an output terminal of the second level shifter circuit 12 is electrically connected to the signal feedback terminal B of the control circuit 10, the second level shifter circuit 12 is configured to perform a step-down conversion on the first control signal PDRV and output a second pre-control signal Post _ PDRV to the signal feedback terminal B of the control circuit 10, as shown in fig. 3B, a pulse timing of the second pre-control signal Post _ PDRV is the same as a pulse timing of the first control signal PDRV, that is, a pulse period of the second pre-control signal Post _ PDRV is the same as a pulse period of the first control signal PDRV, the second pre-control signal Post _ PDRV has a slight delay with respect to the first control signal PDRV, the delay is generated by a step-down conversion process of the second level shifter circuit 12, the voltage of the second pre-control signal Post _ PDRV is less than the voltage of the first control signal PDRV.

Specifically, in order to reduce the high voltage of the second control signal NDRV, the first control signal PDRV output by the first level conversion circuit 11 may be reduced by the second level conversion circuit 12, for example, the PDRV signal of Vbk to Vbat is reduced and converted into the second pre-control signal Post _ PDRV of 0V to Vbk, so that the control circuit 10 obtains the second control signal NDRV according to the second pre-control signal Post _ PDRV.

Alternatively, as shown in fig. 4, the control circuit 10 includes: a first and gate a1, a first input terminal of which is electrically connected to the signal input terminal In of the control circuit 10; a first inverter N1, a second inverter N2 and a third inverter N3, wherein the first inverter N1, the second inverter N2 and the third inverter N3 are connected in series between the output end of the first and gate a1 and the first signal output end U1; a fourth inverter N4, an input terminal of which is electrically connected to the signal input terminal In of the control circuit 10; a second and gate a2, a first input terminal of which is electrically connected to the output terminal of the fourth inverter N4; the fifth inverter N5 and the sixth inverter N6, the fifth inverter N5 and the sixth inverter N6 are connected in series between the signal feedback terminal B and the second input terminal of the second and gate a 2; the seventh inverter N7 and the eighth inverter N8, the seventh inverter N7 and the eighth inverter N8 are connected in series between the output end of the second and gate a2 and the second signal output end U2; a ninth inverter N9, the ninth inverter N9 being connected in series between the second input terminal of the first and gate a1 and the second signal output terminal U2; the high-level end of the power supply of the control circuit 10 is electrically connected to the power output end VBK, that is, the working power supply voltage of the control circuit 10 is the voltage output by the power output end VBK. It should be noted that the specific structure of the control circuit 10 is only an example, and the specific structure of the control circuit 10 is not limited in the embodiment of the present application, for example, any two of the first inverter N1, the second inverter N2, and the third inverter N3 may be omitted from the control circuit 10, or the seventh inverter N7 and the eighth inverter N8 may be omitted, so that the function of the control circuit 10 may still be realized.

Alternatively, as shown in fig. 4, the third input terminal of the first and gate a1 and the third input terminal of the second and gate a2 are electrically connected to the soft start control signal terminal ST. The buck switching power supply may further include a soft start module 4, where the soft start module 4 is electrically connected to a soft start control signal terminal ST for providing a low level during a start phase and a high level after the start phase is finished. Since the voltage of the PDRV is Vbk-Vbat, the voltage Vbk of the power output terminal Vbk will gradually increase when the buck switching power supply starts to power up, and there is a lower voltage condition before Vbk reaches the required voltage, at this time, if the lower voltage is output to the gate of the first power transistor T1, the first power transistor T1 may still be damaged by breakdown, but in the embodiment of the present application, due to the setting of the soft-start control signal terminal ST, before Vbk reaches the required voltage (i.e., the start-up phase), the soft-start control signal terminal ST provides, for example, 0V low level as logic 0, that is, the first signal output terminal U1 of the control circuit 10 outputs the voltage Vbk (logic 1, i.e., high level), the first level conversion circuit 11 converts the voltage Vbk (logic 1) into the voltage Vbat (logic 1) to control the first power transistor T1 to be turned off, the voltage Vbat is the voltage provided by the power input end VBAT; the NDRV is similarly set to 0 level to control the second power transistor T2 to be turned off. By the control mode, the power transistor can be prevented from being broken down when the Vbk is low, and after the Vbk reaches the required voltage, the soft start control signal terminal ST is controlled to provide a high level, so that the power transistor driving circuit 1 can normally work.

Alternatively, as shown in fig. 4 and 5, fig. 5 is a schematic structural diagram of a first level shift circuit in fig. 4, and the first level shift circuit 11 includes: a tenth inverter N10, an input terminal of which is electrically connected to the input terminal I11 of the first level shifter circuit 11, the input terminal I11 of the first level shifter circuit 11 in fig. 5 is electrically connected to the first signal output terminal U1 of the control circuit 10 in fig. 4, and the output terminal O11 of the first level shifter circuit 11 in fig. 5 is electrically connected to the gate of the first power transistor T1 in fig. 4; an eleventh inverter N11, an input terminal of which is electrically connected to an output terminal of the tenth inverter N10, power high level terminals of the tenth inverter N10 and the eleventh inverter N11 are electrically connected to the power output terminal VBK, and power low level terminals of the tenth inverter N10 and the eleventh inverter N11 are grounded; the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are sequentially connected in series between the power input end VBAT and the ground end to form a first path; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are sequentially connected in series between the power input end VBAT and the ground end to form a second path; the first path and the second path are connected in parallel, a connection node between the first transistor M1 and the second transistor M2 is a first node O1, the first node O1 is electrically connected to the gate of the fifth transistor M5, a connection node between the fifth transistor M5 and the sixth transistor M6 is a second node O2, and the second node O2 is electrically connected to the gate of the first transistor M1; a gate of the fourth transistor M4 is electrically connected to the output terminal of the tenth inverter N10, and a gate of the eighth transistor M8 is electrically connected to the output terminal of the eleventh inverter N11; the output circuit 110, the output circuit 110 is connected in series between the second node O2 and the output end O11 of the first level shifter circuit, the power supply high level end of the output circuit 110 is electrically connected to the power supply input end VBAT, and the power supply low level end of the output circuit 110 is electrically connected to the auxiliary voltage end VDNW; the gates of the second transistor M2 and the sixth transistor M6 are electrically connected to the auxiliary voltage terminal VDNW, the gates of the third transistor M3 and the seventh transistor M7 are electrically connected to the power output terminal VBK, and the auxiliary voltage terminal VDNW is used for providing a voltage greater than 0.7V.

Specifically, in the first level shift circuit shown in fig. 5, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are P-type transistors, and the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are N-type transistors, and due to the voltage division function of the second transistor M2, the third transistor M3, the sixth transistor M6, and the seventh transistor M7, the voltage difference between the source and the drain of the other transistors is reduced, so that the risk of the other transistors being broken down by the source-drain voltage is reduced. During the operation of the first level shifter 11, the low voltage of the first control signal PDRV output therefrom is determined by the voltage provided by the auxiliary voltage terminal VDNW, and therefore, the auxiliary voltage terminal VDNW is required to provide a voltage greater than 0V.

In a possible implementation manner, since less voltage is available in the whole power circuit, the voltage required by the auxiliary voltage terminal VDNW can be provided through the power output terminal VBK in order to utilize the existing voltage, but in the start-up phase, the voltage of the power output terminal VBK is raised from 0V, so if the voltage of the auxiliary voltage terminal VDNW is always provided through the power output terminal VBK, there is still a problem that the gate withstand voltage of the first power transistor T1 is larger in the start-up phase, therefore, the voltage of the auxiliary voltage terminal VDNW can be provided through an external circuit other than the power output terminal VBK in the start-up phase, the auxiliary voltage provided by the external circuit is larger than 0.7V in the start-up phase, in order to avoid the output circuit 110 from being broken down, for example, the voltage of the auxiliary terminal provided by the external circuit can be 0.9V, the external circuit can be a transmission gate circuit, the transmission gate circuit can be implemented by two transmission tubes, and if the auxiliary terminal voltage is too small, for example equal to 0V, during the starting phase, overvoltage problems can occur during signal transmission. After the start-up phase is finished, the power supply output terminal VBK is charged to a certain voltage, and then the voltage of the auxiliary voltage terminal VDNW is provided through the power supply output terminal VBK, so that during the operation process including the start-up phase, the low voltage of the first control signal is greater than 0V, so as to reduce the probability that the first power transistor T1 is broken down, or after the start-up phase is finished, the voltage lower than the power supply output terminal VBK may be selected as the voltage of the auxiliary voltage terminal VDNW, for example, the operating voltage of the MCU may be, for example, 0.9V. Alternatively, as shown in fig. 4 and 5, the output circuit 110 includes: a nand gate AN, a first input end of which is electrically connected to the second node O2, and a second input end of which is electrically connected to the soft start control signal boosting terminal ST _ H; the twelfth inverter N12 and the thirteenth inverter N13 are connected in series between the output of the nand gate AN and the output O11 of the first level shifter circuit. The soft start control signal terminal ST is used to provide a low level (e.g., 0V) during the start-up phase and a high level (e.g., 1.8V) after the end of the start-up phase. The soft-start control signal boost terminal ST _ H is electrically connected to the soft-start control signal terminal ST through the soft-start boost circuit 13, the soft-start boost circuit 13 is configured to boost the voltage provided by the soft-start control signal terminal ST and then output the boosted voltage at the soft-start control signal boost terminal ST _ H, for example, a voltage of 0V to VDNW and a voltage of 1.8V to 3.3V, when the soft-start control signal terminal ST provides a low level (logic 0), the output terminal O11 of the first level shift circuit outputs Vbat without generating the first control signal PDRV and the Vbat is at a high level, and controls the first power transistor T1 to be turned off, at this time, the Vbat is prevented from generating a surge current due to the operation of the first power transistor T1, the VBK can be charged through another circuit (for example, a precharge circuit later), and when the voltage of the VBK is charged to a desired voltage, the start-up phase is over, the soft start control signal terminal ST provides a high level (logic 1), the first level shift circuit works normally, and the first control signal PDRV is generated.

Alternatively, as shown in fig. 6, fig. 6 is a schematic structural diagram of the soft-start boost circuit in fig. 4, and the soft-start boost circuit 13 includes: a seventeenth inverter N17, an input terminal of which is electrically connected to the input terminal of the soft-start voltage boost circuit 13, and an input terminal of the soft-start voltage boost circuit 13 in fig. 6 is electrically connected to the soft-start control signal terminal ST in fig. 4; an eighteenth inverter N18, an input terminal of which is electrically connected to an output terminal of the seventeenth inverter N17, power high level terminals of the seventeenth inverter N17 and the eighteenth inverter N18 are electrically connected to the auxiliary voltage terminal VDNW, and power low level terminals of the seventeenth inverter N17 and the eighteenth inverter N18 are grounded; the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19 and the twentieth transistor M20 are sequentially connected in series between the power input terminal VBAT and the ground terminal to form a third path; the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23 and the twenty-fourth transistor M24 are sequentially connected in series between the power input end VBAT and the ground end to form a fourth path; the third path and the fourth path are connected in parallel, a connection node between the seventeenth transistor M17 and the eighteenth transistor M18 is a fifth node O5, the fifth node O5 is electrically connected to the gate of the twenty-first transistor M21, a connection node between the twenty-first transistor M21 and the twenty-second transistor M22 is a sixth node O6, and the sixth node O6 is electrically connected to the gate of the seventeenth transistor M17; a gate of the twentieth transistor M20 is electrically connected to the output terminal of the eighteenth inverter N18, and a gate of the twenty-fourth transistor M24 is electrically connected to the output terminal of the seventeenth inverter N17; the sixth node O6 is electrically connected to the output terminal of the soft-start voltage boost circuit 13, and the output terminal of the soft-start voltage boost circuit 13 is the soft-start control signal boost terminal ST _ H. Among them, the seventeenth transistor M17, the eighteenth transistor M18, the twenty-first transistor M21, and the twenty-second transistor M22 are P-type transistors, and the nineteenth transistor M19, the twentieth transistor M20, the twenty-third transistor M23, and the twenty-fourth transistor M24 are N-type transistors.

Alternatively, as shown in fig. 4 and 7, fig. 7 is a schematic structural diagram of a second level shift circuit in fig. 4, and the second level shift circuit 12 includes: an input terminal of the thirteenth inverter N13 is electrically connected to the input terminal I12 of the second level shifter circuit 12, the input terminal I12 of the second level shifter circuit 12 in fig. 7 is electrically connected to the output terminal of the first level shifter circuit 11 in fig. 4, and the output terminal O12 of the second level shifter circuit 12 in fig. 7 is electrically connected to the signal feedback terminal B of the control circuit 10 in fig. 4; a fourteenth inverter N14, an input terminal of which is electrically connected to an output terminal of the thirteenth inverter N13, power high level terminals of the thirteenth inverter N13 and the fourteenth inverter N14 are electrically connected to the power input terminal VBAT, and power low level terminals of the thirteenth inverter N13 and the fourteenth inverter N14 are electrically connected to the auxiliary voltage terminal VDNW; the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are sequentially connected in series between the power input end VBAT and the ground end to form a third path; the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 are sequentially connected in series between the power input end VBAT and the ground end to form a fourth path; the third path and the fourth path are connected in parallel, a connection node between the eleventh transistor M11 and the twelfth transistor M12 is a third node O3, the third node O3 is electrically connected to the gate of the sixteenth transistor M16, a connection node between the fifteenth transistor M15 and the sixteenth transistor M16 is a fourth node O4, and the fourth node O4 is electrically connected to the gate of the twelfth transistor M12; a gate of the ninth transistor M9 is electrically connected to the output terminal of the fourteenth inverter N14, and a gate of the thirteenth transistor M13 is electrically connected to the output terminal of the thirteenth inverter N13; a fifteenth inverter N15 and a sixteenth inverter N16 connected in series between the fourth node O4 and the output terminal O12 of the second level shifter circuit, wherein the high power terminals of the fifteenth inverter N15 and the sixteenth inverter N16 are electrically connected to the power output terminal VBK, and the low power terminals of the fifteenth inverter N15 and the sixteenth inverter N16 are grounded; the gates of the tenth transistor M10 and the fourteenth transistor M14 are electrically connected to the auxiliary voltage terminal VDNW, and the gates of the eleventh transistor M11 and the fifteenth transistor M15 are electrically connected to the power output terminal VBK. In the structure shown in fig. 7, before Vbk reaches the required voltage, the auxiliary voltage terminal VDNW may be stepped down by the power input terminal VBAT through a diode or other means to provide the required voltage, so as to ensure that the second level shifter circuit operates normally; after Vbk reaches the required voltage, the auxiliary voltage terminal VDNW may be supplied with the voltage from the power supply output terminal Vbk; in other possible embodiments, the auxiliary voltage terminal VDNW may also be provided with a lower voltage from another power source terminal, for example, an operating voltage of a Micro Controller Unit (MCU), for example, a voltage of 0.9V, so as to further reduce the on-resistance of the first power transistor T1 and improve the power efficiency.

Optionally, as shown in fig. 2, the buck switching power supply further includes: the soft start module 4 is used for controlling the precharge circuit 3 to charge the power output end VBK during the start phase, controlling the first power transistor T1 to be turned off, and controlling the precharge circuit 3 to stop working after the start phase is finished.

Specifically, the starting stage is a stage when the buck switching power supply starts to be powered on, at this time, the power output end VBK is charged through the precharge circuit 3, the voltage VBK of the power output end VBK gradually rises, before the VBK reaches a required voltage, the first power transistor T1 is controlled to be turned off through the soft start module 4, for example, the soft start control signal end ST outputs 0; after a period of time, the voltage VBK of the power output end VBK reaches a preset value, or after the preset charging is met, the soft start control signal end ST outputs a high voltage, the power output end VBK is not charged through the pre-charging circuit 3 any more, and the buck switching power supply is started normally. The power voltage of the precharge circuit 3 may be provided by a soft-start power supply terminal VCC formed by connecting the power input terminal VBAT to a diode for voltage reduction, and the auxiliary voltage terminal VDNW may be further formed by connecting the soft-start power supply terminal VCC to a plurality of diodes for voltage reduction. Through pre-charge circuit 3 and soft start module 4, can close power transistor at switching power supply's the last power-on initial stage, reduce the risk that power transistor is broken down by voltage, and use less electric current to charge for power output end VBK through pre-charge circuit 3, pre-charge circuit 3's output current is less than 5mA, 10MA or 50mA, thereby it produces uncontrollable surge current to have avoided directly charging through the BUCK circuit that first power transistor T1 and second power transistor T2 formed at the start-up stage, the no surge current of circuit has been realized promptly. For example, as shown in fig. 8, fig. 8 is another timing signal diagram in the embodiment of the present application, wherein S1 represents an operating state of the buck switching power supply, where a high level represents that the buck switching power supply operates, and a low level represents that the buck switching power supply is turned off; vbk represents the voltage of the power supply output terminal Vbk; ST represents the voltage of a soft start control signal terminal ST; s2 indicates the operation state of the precharge circuit 3, in which a low level indicates operation and a high level indicates off. As can be seen from fig. 8, the buck switching power supply starts to start at stage T1, the reference circuit and the bias circuit are first turned on, the reference circuit and the bias circuit are electrically connected to the voltage regulator 2 and the soft start module 4 to generate the reference voltage and the working current required by the voltage regulator 2 and the soft start module 4, the soft start control signal terminal ST provides a voltage of 0V at stage T1 to forcibly control the first power transistor T1 and the second power transistor T2 to be turned off, the pre-charge circuit 3 charges the power output terminal VBK, and the stage T2 is entered after the voltage charge of the power output terminal VBK reaches a preset value, at this time, the soft start control signal terminal ST provides a high level, and the first power transistor T1 and the second power transistor T2 start to operate normally; thereafter, in a period t3, the operation of the precharge circuit 3 is stopped, i.e., the charging of the power supply output terminal VBK by the precharge circuit 3 is stopped.

The embodiment of the present application further provides an electronic device, which includes the step-down switching power supply in the above embodiment, wherein the specific structure and principle of the step-down switching power supply are the same as those of the above embodiment, and are not described herein again.

The embodiment of the present application further provides a control method, which is used in the buck switching power supply in the above embodiment, as shown in fig. 2, the buck switching power supply further includes: the precharge circuit 3, the control method includes:

in the start-up phase, the first power transistor T1 is controlled to be turned off, and the precharge circuit 3 is controlled to charge the power output VBK;

after the start-up phase is ended, the first power transistor T1 is controlled to switch between on and off states in response to the first control signal PDRV, the second power transistor T2 is controlled to switch between on and off states in response to the second control signal NDRV, and the precharge circuit 3 is controlled to stop operating.

The specific process and principle of the control method are the same as those of the above embodiments, and are not described herein again.

In the control method in the embodiment of the application, two power transistors are set as the LDMOS to improve the voltage bearing capacity between the source and the drain, in order to save the process cost, the LDMOS and other devices in the advanced process have the same oxide layer thickness, therefore, the gate voltage endurance of the LDMOS is low, on this basis, the low level of the first control signal for controlling the conduction of the first power transistor is further set to be higher than 0V, the high level of the second control signal for controlling the conduction of the second power transistor is set to be lower than the voltage of the power input end to reduce the gate-source voltage difference of the power transistors, that is, the risk that the power transistors are broken down due to the higher gate-source voltage difference is reduced, that is, when the two power transistors are set as the LDMOS, the low level of the first control signal for controlling the conduction of the first power transistor is set to be higher than 0V, the high level of the second control signal for controlling the conduction of the second power transistor is lower than the voltage of the power input end, so that the lithium battery environment can be applied, and the cost is reduced.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

A buck switching power supply, comprising:

the first power transistor is connected between the power supply input end and the switching node in series, and the first power transistor is a P-type transverse double-diffusion transistor;

the second power transistor is connected between the switching node and a grounding end in series, and the second power transistor is an N-type transverse double-diffused transistor;

the output inductor is connected between the switching node and the power supply output end in series;

the output capacitor is connected between the power supply output end and the grounding end in series;

the power transistor driving circuit is electrically connected to the grid of the first power transistor and the grid of the second power transistor, and is used for outputting a first control signal to the grid of the first power transistor and outputting a second control signal to the grid of the second power transistor, wherein the low voltage of the first control signal is a voltage greater than 0V, and the high voltage of the second control signal is less than the voltage of the power supply input end.
A buck switching power supply according to claim 1,

an active level in the first control signal and an active level in the second control signal are not overlapped, the active level in the first control signal is a level for controlling the first power transistor to be conducted, and the active level in the second control signal is a level for controlling the second power transistor to be conducted;

the power transistor driving circuit includes:

the control circuit comprises a signal input end, a first signal output end, a signal feedback end and a second signal output end, the control circuit outputs a first pre-control signal through the first signal output end and outputs a second control signal through the second signal output end, the pulse period of the first pre-control signal is the same as that of the first control signal, and the voltage of the first pre-control signal is smaller than that of the first control signal;

the input end of the first level conversion circuit is electrically connected to the first signal output end of the control circuit, the output end of the first level conversion circuit is electrically connected to the grid electrode of the first power transistor, and the first level conversion circuit is used for performing boost conversion on the first pre-control signal and outputting the first control signal.
Buck switching power supply according to claim 2,

the power transistor driving circuit further comprises a second level shift circuit, an input end of the second level shift circuit is electrically connected to an output end of the first level shift circuit, an output end of the second level shift circuit is electrically connected to a signal feedback end of the control circuit, the second level shift circuit is used for carrying out voltage reduction conversion on the first control signal and outputting a second pre-control signal to the signal feedback end of the control circuit, a pulse period of the second pre-control signal is the same as a pulse period of the first control signal, and voltage of the second pre-control signal is smaller than voltage of the first control signal.
The buck switching power supply of claim 2,

and the working power supply voltage of the control circuit is the voltage output by the power supply output end.
The buck switching power supply of claim 2,

the first level shift circuit includes:

a tenth inverter, an input terminal of which is electrically connected to the input terminal of the first level shift circuit;

an eleventh inverter, an input terminal of which is electrically connected to an output terminal of the tenth inverter, power high level terminals of the tenth inverter and the eleventh inverter being electrically connected to the power output terminal, and power low level terminals of the tenth inverter and the eleventh inverter being grounded;

the first transistor, the second transistor, the third transistor and the fourth transistor are sequentially connected in series between the power supply input end and a ground end to form a first path; and

the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are sequentially connected in series between the power input end and a ground end to form a second path;

the first path and the second path are connected in parallel, a connection node between the first transistor and the second transistor is a first node, the first node is electrically connected to a gate of the fifth transistor, a connection node between the fifth transistor and the sixth transistor is a second node, and the second node is electrically connected to the gate of the first transistor;

a gate of the fourth transistor is electrically connected to an output end of the tenth inverter, and a gate of the eighth transistor is electrically connected to an output end of the eleventh inverter;

the first level conversion circuit further comprises an output circuit, the output circuit is connected in series between the second node and the output end of the first level conversion circuit, the power supply high level end of the output circuit is electrically connected to the power supply input end, and the power supply low level end of the output circuit is electrically connected to the auxiliary voltage end;

the gates of the second transistor and the sixth transistor are electrically connected to the auxiliary voltage terminal, the gates of the third transistor and the seventh transistor are electrically connected to the power output terminal, and the auxiliary voltage terminal is used for providing a voltage greater than 0.7V.
A buck switching power supply according to claim 5,

the voltage of the auxiliary voltage terminal is provided by an external circuit outside the power supply output terminal in a start-up phase, and the voltage of the auxiliary voltage terminal is provided by the power supply output terminal after the start-up phase is finished.
A buck switching power supply according to claim 5,

the output circuit includes:

a nand gate, a first input end of which is electrically connected to the second node, a second input end of which is electrically connected to a soft start control signal boost end, the soft start control signal boost end is electrically connected to a soft start control signal end through a soft start boost circuit, the soft start boost circuit is used for boosting the voltage provided by the soft start control signal end and then outputting the boosted voltage at the soft start control signal boost end, the soft start control signal end is used for providing a low level at a start stage and providing a high level after the start stage is finished;

and the twelfth inverter and the thirteenth inverter are connected in series between the output end of the NAND gate and the output end of the first level conversion circuit.
A buck switching power supply according to claim 3,

the second level shift circuit includes:

a thirteenth inverter, an input end of which is electrically connected to the input end of the second level shift circuit;

a fourteenth inverter, an input terminal of which is electrically connected to an output terminal of the thirteenth inverter, power high level terminals of the thirteenth inverter and the fourteenth inverter being electrically connected to the power input terminal, and power low level terminals of the thirteenth inverter and the fourteenth inverter being electrically connected to an auxiliary voltage terminal;

the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are sequentially connected in series between the power input end and the ground end to form a third path;

the thirteenth transistor, the fourteenth transistor, the fifteenth transistor and the sixteenth transistor are sequentially connected in series between the power input end and the ground end to form a fourth path;

the third path and the fourth path are connected in parallel, a connection node between the eleventh transistor and the twelfth transistor is a third node, the third node is electrically connected to the gate of the sixteenth transistor, a connection node between the fifteenth transistor and the sixteenth transistor is a fourth node, and the fourth node is electrically connected to the gate of the twelfth transistor;

a gate of the ninth transistor is electrically connected to an output end of the fourteenth inverter, and a gate of the thirteenth transistor is electrically connected to an output end of the thirteenth inverter;

a fifteenth inverter and a sixteenth inverter connected in series between the fourth node and the output terminal of the second level shift circuit, wherein power high level terminals of the fifteenth inverter and the sixteenth inverter are electrically connected to the power output terminal, and power low level terminals of the fifteenth inverter and the sixteenth inverter are grounded;

gates of the tenth transistor and the fourteenth transistor are electrically connected to the auxiliary voltage terminal, and gates of the eleventh transistor and the fifteenth transistor are electrically connected to the power supply output terminal.
The buck switching power supply of claim 4, further comprising:

the soft start module is used for controlling the pre-charging circuit to charge the power output end in a start stage, controlling the first power transistor to be cut off, and controlling the pre-charging circuit to stop working after the start stage is finished.
An electronic device comprising a buck-type switching power supply as claimed in any one of claims 1 to 9.
A control method for a buck-type switching power supply as claimed in claims 1 to 9, the buck-type switching power supply further comprising: a precharge circuit, the control method comprising:

in a starting stage, the first power transistor is controlled to be turned off, and the pre-charging circuit is controlled to charge the power supply output end;

after the start-up phase is finished, the first power transistor is controlled to be switched between the on state and the off state in response to the first control signal, the second power transistor is controlled to be switched between the on state and the off state in response to the second control signal, and the pre-charging circuit is controlled to stop working.