CN114725188A - IGBT terminal capable of reducing field limiting ring width and preparation method thereof - Google Patents
IGBT terminal capable of reducing field limiting ring width and preparation method thereof Download PDFInfo
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- CN114725188A CN114725188A CN202210347431.XA CN202210347431A CN114725188A CN 114725188 A CN114725188 A CN 114725188A CN 202210347431 A CN202210347431 A CN 202210347431A CN 114725188 A CN114725188 A CN 114725188A
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- Prior art keywords
- field limiting
- ring
- limiting ring
- phosphorus
- layer
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- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 20
- 229910052698 phosphorus Inorganic materials 0.000 claims description 18
- 239000011574 phosphorus Substances 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the invention discloses an IGBT terminal capable of reducing the width of field limiting rings and a preparation method thereof. The invention reduces the terminal size, increases gross die and reduces the cost; the invention controls the internal electric field of the device and improves the reliability (HTRB).
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an IGBT terminal capable of reducing the width of a field limiting ring and a preparation method thereof.
Background
In a conventional IGBT termination, a Field Limiting Ring (FLR) termination is composed of a plurality of ring rings and a metal field plate. The existing IGBT terminal has the problem of too large size, and then causes the die size to become large.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide an IGBT terminal with a reduced field limiting ring width and a method for manufacturing the same, so as to reduce the size, control the electric field inside the device, and improve the reliability.
In order to solve the technical problem, an embodiment of the present invention provides an IGBT terminal with a reduced field limiting ring width, including a Sub substrate, where multiple field limiting rings are disposed on the Sub substrate, each field limiting ring is composed of a ring and a metal field plate located on the ring, a phosphorus layer is injected on the Sub substrate between the rings, and an oxide isolation layer is disposed on the phosphorus layer.
Correspondingly, the embodiment of the invention also provides a preparation method of the IGBT terminal for reducing the width of the field limiting ring, which comprises the following steps:
step 1: a layer of phosphorus is generally injected on the Sub substrate, and annealing is carried out;
step 2: preparing a printing ring to the Sub substrate;
and step 3: etching an oxidation isolation layer on the phosphorus layer;
and 4, step 4: and etching the metal field plate on the ring to obtain the IGBT terminal with the reduced width of the field limiting ring.
Further, in the step 1, the injection energy range of the phosphorus is 50-100 kev.
Furthermore, the implantation dosage range of the phosphorus is 1e 12-1 e13, and the doping concentration range of the Sub substrate surface is 1e 15-1 e 18.
The invention has the beneficial effects that: the invention reduces the terminal size, increases gross die and reduces the cost; the invention controls the internal electric field of the device and improves the reliability (HTRB).
Drawings
Fig. 1 is a schematic structural diagram of an IGBT terminal with a reduced field limiting ring width according to an embodiment of the present invention.
Fig. 2 is a schematic flow chart of a method for manufacturing an IGBT terminal with a reduced field limiting ring width according to an embodiment of the present invention.
Description of the reference numerals
Sub substrate 1, phosphor layer 2, printing ring 3, metal field plate 4, oxidation isolation layer 5.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict, and the present invention is further described in detail with reference to the drawings and specific embodiments.
If directional indications (such as up, down, left, right, front, and rear … …) are provided in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the movement, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are only used for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
Referring to fig. 1, the IGBT terminal with reduced field limiting ring width according to the embodiment of the present invention includes a Sub substrate, where a plurality of field limiting rings are disposed on the Sub substrate, and each field limiting ring is composed of a primary ring and a metal field plate disposed on the primary ring.
And a phosphorus layer is injected between the Sub substrate and the corresponding printing ring, and an oxidation isolation layer is arranged on the phosphorus layer. The oxidation isolation layer is an LO COS dielectric layer. Preferably, the injection energy is selected from 50kev to 100kev, the injection dosage is 1e12 to 1e13, the wafer surface doping concentration is increased between 1e15 to 1e18, the width of a depletion region is reduced by 10um to 50um, and the terminal size is reduced by 10um to 50 um. The invention controls the electric field in the device and the breakdown voltage by adjusting the concentration and the depth of the phosphor.
Referring to fig. 2, a method for manufacturing an IGBT terminal with a reduced field limiting ring width according to an embodiment of the present invention includes:
step 1: a layer of phosphorus is generally injected on the Sub substrate, and annealing is carried out;
step 2: preparing a printing ring to the Sub substrate;
and step 3: etching an oxidation isolation layer on the phosphorus layer;
and 4, step 4: and etching the metal field plate on the ring to obtain the IGBT terminal with the reduced width of the field limiting ring.
The doping concentration of the surface of the substrate is increased, the width of a depletion region is reduced and the size of a terminal is reduced by commonly injecting phosphor; the invention controls the internal electric field of the device and the breakdown voltage by adjusting the concentration and the depth of phosphor.
In one embodiment, the implantation energy of the phosphorus in step 1 is in a range of 50kev to 100 kev.
In one embodiment, the dose of phosphorus is in the range of 1e 12-1 e13, and the doping concentration of the Sub substrate surface is in the range of 1e 15-1 e 18.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. The utility model provides a reduce IGBT terminal of field limiting ring width, includes the Sub-substrate, is equipped with a plurality of field limiting rings on the Sub-substrate, and the field limiting ring comprises the ring of pring and the metal field plate that is located the ring of pring, and its characterized in that, corresponds on the Sub-substrate and annotates the phosphorus layer between the ring of pring, is equipped with the oxidation isolation layer on the phosphorus layer.
2. A preparation method of an IGBT terminal capable of reducing the width of a field limiting ring is characterized by comprising the following steps:
step 1: a layer of phosphorus is generally injected on the Sub substrate, and annealing is carried out;
step 2: preparing a printing ring to the Sub substrate;
and step 3: etching an oxidation isolation layer on the phosphorus layer;
and 4, step 4: and etching the metal field plate on the ring to obtain the IGBT terminal with the reduced width of the field limiting ring.
3. The method for preparing the IGBT terminal with the reduced field limiting ring width according to claim 1, wherein in the step 1, the injection energy of the phosphorus is 50-100 kev.
4. The method as claimed in claim 3, wherein the phosphorus is implanted in a dose range of 1e 12-1 e13, and the doping concentration of the Sub substrate surface is in a range of 1e 15-1 e 18.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210347431.XA CN114725188A (en) | 2022-04-01 | 2022-04-01 | IGBT terminal capable of reducing field limiting ring width and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210347431.XA CN114725188A (en) | 2022-04-01 | 2022-04-01 | IGBT terminal capable of reducing field limiting ring width and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114725188A true CN114725188A (en) | 2022-07-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210347431.XA Pending CN114725188A (en) | 2022-04-01 | 2022-04-01 | IGBT terminal capable of reducing field limiting ring width and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114725188A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075739A (en) * | 1990-01-02 | 1991-12-24 | Motorola, Inc. | High voltage planar edge termination using a punch-through retarding implant and floating field plates |
| JP2013168549A (en) * | 2012-02-16 | 2013-08-29 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
| CN103367398A (en) * | 2013-07-23 | 2013-10-23 | 上海北车永电电子科技有限公司 | Terminal guard ring and manufacturing method thereof |
| CN104332488A (en) * | 2013-07-22 | 2015-02-04 | 无锡华润上华半导体有限公司 | Semiconductor device, semiconductor device terminal and manufacturing method thereof |
| CN104600103A (en) * | 2013-10-30 | 2015-05-06 | 无锡华润上华半导体有限公司 | High-voltage semiconductor device, high-voltage semiconductor device terminal and manufacturing method thereof |
| CN113889407A (en) * | 2021-09-27 | 2022-01-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench type IGBT device and trench type IGBT device |
-
2022
- 2022-04-01 CN CN202210347431.XA patent/CN114725188A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075739A (en) * | 1990-01-02 | 1991-12-24 | Motorola, Inc. | High voltage planar edge termination using a punch-through retarding implant and floating field plates |
| JP2013168549A (en) * | 2012-02-16 | 2013-08-29 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
| CN104332488A (en) * | 2013-07-22 | 2015-02-04 | 无锡华润上华半导体有限公司 | Semiconductor device, semiconductor device terminal and manufacturing method thereof |
| CN103367398A (en) * | 2013-07-23 | 2013-10-23 | 上海北车永电电子科技有限公司 | Terminal guard ring and manufacturing method thereof |
| CN104600103A (en) * | 2013-10-30 | 2015-05-06 | 无锡华润上华半导体有限公司 | High-voltage semiconductor device, high-voltage semiconductor device terminal and manufacturing method thereof |
| CN113889407A (en) * | 2021-09-27 | 2022-01-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench type IGBT device and trench type IGBT device |
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