CN110534513B - High-low voltage integrated device and manufacturing method thereof - Google Patents
High-low voltage integrated device and manufacturing method thereof Download PDFInfo
- Publication number
- CN110534513B CN110534513B CN201910842339.9A CN201910842339A CN110534513B CN 110534513 B CN110534513 B CN 110534513B CN 201910842339 A CN201910842339 A CN 201910842339A CN 110534513 B CN110534513 B CN 110534513B
- Authority
- CN
- China
- Prior art keywords
- conductive type
- voltage
- low
- well region
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 86
- 238000002955 isolation Methods 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims description 99
- 238000001259 photo etching Methods 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 36
- 238000000137 annealing Methods 0.000 claims description 28
- 238000000151 deposition Methods 0.000 claims description 27
- 239000000945 filler Substances 0.000 claims description 20
- 238000005468 ion implantation Methods 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 150000002500 ions Chemical class 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- -1 oxygen ions Chemical class 0.000 claims description 9
- 230000005684 electric field Effects 0.000 claims description 7
- 230000002146 bilateral effect Effects 0.000 claims description 6
- 230000001413 cellular effect Effects 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 239000010953 base metal Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a high-low voltage integrated device and a manufacturing method thereof, wherein the high-low voltage integrated device comprises a high-voltage vertical constant current device, a low-voltage NMOS device, a low-voltage PMOS device, a low-voltage NPN device and a low-voltage DIODE device which are integrated on the same chip; the low-voltage devices are all positioned in the medium isolation groove, and the high-voltage devices and the low-voltage devices are completely isolated by adopting a medium isolation mode. The invention adopts partial buried oxide isolation technology to realize the compatibility of high-voltage and low-voltage devices, completely avoids the problems of electric leakage and crosstalk, and has lower cost compared with the traditional SOI process; based on the BCD process integration technology design concept, the high-voltage vertical type constant current device and the low-voltage device for current regulation are integrated together, the current regulation circuit design of the constant current device is simplified through a single chip integration mode, the system complexity is reduced, meanwhile, the manufacturing cost is saved, the current regulation function of the constant current device can be realized, and the method is suitable for application occasions with different current sizes.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a high-low voltage integrated device and a manufacturing method thereof.
Background
Constant current sources are a common type of electronic device and apparatus and are used quite commonly in electronic circuits. The constant current source is generally used for protecting the whole circuit, and even if the voltage in the circuit is unstable or the load resistance value changes greatly, the stability of the power supply current of the whole circuit can be still ensured. A Constant current Diode (CRD) is a commonly used semiconductor Constant current device, and the Diode is used as a Constant current source to replace a common Constant current source composed of a plurality of electronic elements such as a transistor, a voltage regulator tube and a resistor, thereby realizing simplification and miniaturization of a circuit structure. At present, the output current of a common constant current diode is between several milliamperes and dozens of milliamperes, and the common constant current diode can be used for directly driving a load. The constant current diode has simple peripheral circuit and convenient use, and is widely applied to the fields of automatic control, instruments, protective circuits and the like. However, the output current of the constant current diode can not be adjusted, the output current can be adjusted only by a plurality of parallel methods, the current value can only be increased according to multiple proportion, or the current-expanding output is realized by an external circuit element. Both of these methods of current regulation result in an increase in the number of electronic components used, which leads to an increase in the complexity and cost of the circuit configuration.
High-voltage power integrated circuits often utilize the high analog precision of Bipolar transistors, the high integration of CMOS, and the high power characteristics of DMOS (Double-Diffused MOSFET) to monolithically integrate Bipolar analog circuits, CMOS logic circuits, CMOS analog circuits, and DMOS high-voltage power devices together (BCD process for short). The BCD process integration technology is a common single-chip integration technology, can greatly reduce the power loss of a system, improve the performance of the system, save the packaging cost of a circuit and have better reliability. As the BCD process has a plurality of types of devices, special requirements of each region of the devices need to be considered, the number of masks manufactured by the process is reduced, and all process steps can be carried out simultaneously. Meanwhile, in order to realize the compatibility of a high-voltage device and a low-voltage device and the compatibility of a bipolar process and a CMOS process, a proper isolation technology needs to be selected.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art and provides a high-low voltage integrated device and a manufacturing method thereof.
In order to solve the above technical problem, an embodiment of the present invention provides a high-low voltage integrated device, including a high-voltage vertical constant current device, a low-voltage NMOS device, a low-voltage PMOS device, a low-voltage NPN device, and a low-voltage DIODE device integrated on the same chip;
the high-voltage vertical constant current device is of a bilateral symmetry structure and is divided into a cell area and a terminal area, and the cell area is formed by connecting a plurality of cells with the same structure in a parallel mode; the cell structure comprises a back collector metal electrode, a first conductive type substrate, a second conductive type epitaxial layer, a thin dielectric layer, a gate electrode and a first emitter metal electrode which are sequentially stacked from bottom to top; the second conduction type epitaxial layer is provided with a first conduction type first well region, a second conduction type contact, a first conduction type contact and a second conduction type depletion channel region;
the first well region of the first conductivity type is positioned at two ends of the upper layer of the epitaxial layer of the second conductivity type, the first conductivity type contact, the second conductivity type contact and the depletion type channel region of the second conductivity type are sequentially positioned on one side of the upper layer of the first well region of the first conductivity type side by side, the thin dielectric layer is positioned on the epitaxial layer of the second conductivity type between part of the second conductivity type contact, the depletion type channel region of the second conductivity type and the first well region of the first conductivity type, and the first emitter metal electrode is positioned on the second conductivity type contact, the first conductivity type contact and the gate electrode;
the terminal area is positioned on two sides of the cellular area and comprises a back collector metal electrode, a first conductive type substrate, a second conductive type epitaxial layer, a dielectric layer field oxide, a metal front dielectric and a first emitter metal electrode which are sequentially stacked from bottom to top, and first conductive type second well regions which are arranged at equal intervals are arranged in the second conductive type epitaxial layer of the terminal area;
the low-voltage NMOS device, the low-voltage PMOS device, the low-voltage NPN device and the low-voltage DIODE device are sequentially positioned in the second conductive type epitaxial layer on one side of the high-voltage vertical type constant current device;
the low-voltage NMOS device, the low-voltage PMOS device, the low-voltage NPN device and the low-voltage DIODE device are also positioned in an isolation region formed by connecting the medium groove and the buried oxide layer, and positioned in a first conductive type second well region in the isolation region, and the polycrystalline silicon filling material is positioned inside the medium groove; the high-voltage device and the low-voltage device are isolated by the isolation region; and dielectric layer field oxide is also arranged on the upper surface of the second conduction type epitaxial layer between the adjacent low-voltage devices.
On the basis of the technical scheme, the invention can be further improved as follows.
Furthermore, the first conductive type second well regions in the isolation region are divided into a plurality of regions, the number of the regions is consistent with the number of the low-voltage devices, and a second conductive type epitaxial layer is arranged between the adjacent first conductive type second well regions.
The beneficial effect of adopting the further scheme is that: the first conductive type second well region is divided into a plurality of regions, so that a junction isolation structure of the PNP triode is formed between the low-voltage devices, and the problems of electric leakage and crosstalk between the low-voltage devices can be further prevented by combining the dielectric isolation structure, and the reliability of the chip during working is improved.
Furthermore, the first conduction type second well region in the isolation region extends downwards and towards two sides to the outside of the isolation region, and the first conduction type contact is also positioned on the inner side of the edge of the first conduction type second well region and is connected with the well region contact electrode;
the second conductive type first well regions in the low-voltage PMOS device, the low-voltage NPN device and the low-voltage DIODE device are all in contact with the buried oxide layer.
Further, the buried oxide layer is positioned in the second conduction type epitaxial layer; or the buried oxide layer is located in the first conductive type substrate.
Furthermore, a field resistance layer is further arranged and is positioned between the first conduction type substrate and the second conduction type epitaxial layer, and the buried oxide layer is positioned in the first conduction type substrate.
Furthermore, medium grooves are arranged between the first conductive type first well region and the first conductive type second well region of the high-voltage vertical type constant current device, polycrystalline silicon fillers are arranged in the medium grooves, and the bottoms of the medium grooves are located below the first conductive type second well region; a second conductive type contact is arranged at the outermost periphery of the terminal region of the high-voltage vertical constant current device and serves as an electric field stopping ring; the depth of the dielectric groove in the isolation region is consistent with that of the dielectric groove in the high-voltage vertical constant current device.
Furthermore, medium grooves are arranged between the first conductive type first well region and the first conductive type second well region in the high-voltage vertical type constant current device, polysilicon fillers are filled in the medium grooves, the medium grooves in the isolation region and the medium grooves in the high-voltage vertical type constant current device extend into the first conductive type substrate, the depth of the medium grooves in the isolation region is consistent with that of the medium grooves in the high-voltage vertical type constant current device, and the second conductive type contact is arranged on the outermost periphery of the terminal region of the high-voltage vertical type constant current device and serves as an electric field stopping ring.
In order to solve the above technical problem, an embodiment of the present invention provides a high-low voltage integrated device, including a high-voltage vertical constant current device, a low-voltage NMOS device, a low-voltage PMOS device, a low-voltage NPN device, and a low-voltage DIODE device integrated on the same chip;
the high-voltage vertical constant current device is of a bilateral symmetry structure and is divided into a cell area and a terminal area, and the cell area is formed by connecting a plurality of cells with the same structure in a parallel mode; the cell structure comprises a back collector metal electrode, a first conductive type substrate, a second conductive type epitaxial layer, a thin dielectric layer, a gate electrode and a first emitter metal electrode which are sequentially stacked from bottom to top; the second conduction type epitaxial layer is provided with a first conduction type first well region, a second conduction type contact, a first conduction type contact and a second conduction type depletion channel region;
the first well region of the first conductivity type is positioned at two ends of the upper layer of the epitaxial layer of the second conductivity type, the first conductivity type contact, the second conductivity type contact and the depletion type channel region of the second conductivity type are sequentially positioned on one side of the upper layer of the first well region of the first conductivity type side by side, the thin dielectric layer is positioned on the epitaxial layer of the second conductivity type between part of the second conductivity type contact, the depletion type channel region of the second conductivity type and the first well region of the first conductivity type, and the first emitter metal electrode is positioned on the second conductivity type contact, the first conductivity type contact and the gate electrode;
the terminal area is positioned on two sides of the cellular area and comprises a back collector metal electrode, a first conductive type substrate, a second conductive type epitaxial layer, a metal front medium and a floating metal electrode which are sequentially stacked from bottom to top, a first conductive type first well region which is arranged at equal intervals is arranged in the second conductive type epitaxial layer of the terminal area, a first conductive type contact is arranged in the first conductive type first well region, and the floating metal electrode is positioned on the first conductive type contact and the metal front medium;
the low-voltage NMOS device, the low-voltage PMOS device, the low-voltage NPN device and the low-voltage DIODE device 105 are sequentially positioned in the second conductive type epitaxial layer on one side of the high-voltage vertical type constant current device;
the low-voltage NMOS device, the low-voltage PMOS device, the low-voltage NPN device and the low-voltage DIODE device are also positioned in an isolation region formed by connecting the medium groove and the buried oxide layer, and the polycrystalline silicon filling is positioned in the medium groove; and dielectric layer field oxide is also arranged on the upper surface of the second conduction type epitaxial layer between the adjacent low-voltage devices.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the low-voltage NMOS device, the low-voltage PMOS device, the low-voltage NPN device and the low-voltage DIODE device are also located in the second well region of the first conduction type in the isolation region.
Furthermore, each low-voltage device is positioned in an isolation region formed by connecting the medium groove and the buried oxide layer;
the low-voltage NMOS device is positioned in the first conductive type first well region, and the first conductive type first well region is positioned on the upper layer of the second conductive type epitaxial layer.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a high-voltage and low-voltage integrated device, including the following steps:
forming a second conductive type epitaxial layer on the first conductive type substrate by adopting an epitaxial process;
implanting oxygen ions into one side of the second conductive type epitaxial layer through photoetching and ion implantation processes, and forming a buried oxide layer after annealing treatment;
forming deep grooves at two ends above the buried oxide layer by adopting a deep groove etching process, filling media at two sides of the deep grooves to form media grooves, and filling the media grooves with polysilicon to form polysilicon fillers;
forming a first conductive type second well region on the upper layer of the second conductive type epitaxial layer by adopting photoetching and ion implantation processes, and performing well region diffusion;
growing an oxide layer on the upper surface of the first part of the second conductive type epitaxial layer by adopting a photoetching and thermal growth mode to form dielectric layer field oxide;
respectively injecting first conductive type impurities and second conductive type impurities into a second conductive type epitaxial layer between field oxides of a dielectric layer by adopting photoetching and ion injection processes, forming a first conductive type first well region and a second conductive type depletion channel region on the other side of the upper layer of the second conductive type epitaxial layer after annealing, wherein the second conductive type depletion channel region is positioned on one side of the upper layer of the first conductive type first well region, a second conductive type first well region and a first conductive type first well region are formed between dielectric grooves, and the first conductive type first well region is positioned in part of the second conductive type first well region;
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer in a thermal growth mode to form a thin dielectric layer, and photoetching and etching after depositing polycrystalline silicon to form a gate electrode;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer by adopting photoetching and ion injection processes, and forming second conductive type contact and first conductive type contact on the upper layers of the first conductive type first well region, the first conductive type second well region and the second conductive type first well region after annealing;
depositing a metal front medium, photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate to form an electrode.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a high-voltage and low-voltage integrated device, including the following steps:
forming a second conductive type epitaxial layer on the first conductive type substrate by adopting an epitaxial process;
forming a first conductive type second well region on the second conductive type epitaxial layer by adopting photoetching and ion implantation processes, and performing well region diffusion;
implanting oxygen ions into the first conduction type second well region on one side of the second conduction type epitaxial layer through photoetching and ion implantation processes, and forming a buried oxide layer after annealing treatment;
forming a deep groove in the second conductive type epitaxial layer by adopting a deep groove etching process, filling media on two sides of the deep groove to form a media groove, and filling the media groove with polycrystalline silicon to form a polycrystalline silicon filler;
growing an oxide layer on the upper surface of the first part of the second conduction type epitaxial layer in a thermal growth mode to form dielectric layer field oxide;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer by adopting photoetching and ion injection processes, forming a first conductive type first well region and a second conductive type depletion channel region on the upper layer of the other side of the second conductive type epitaxial layer after annealing, wherein the second conductive type depletion channel region is positioned on one side of the upper layer of the first conductive type first well region, a second conductive type first well region and a first conductive type first well region are formed between the medium grooves, and the first conductive type first well region is positioned in part of the second conductive type first well region;
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer in a thermal growth mode to form a thin dielectric layer, and photoetching and etching after depositing polycrystalline silicon to form a gate electrode;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer by adopting photoetching and ion injection processes, and forming second conductive type contact and first conductive type contact on the upper layers of the first conductive type first well region, the first conductive type second well region and the second conductive type first well region after annealing;
depositing a metal front medium, photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate to form an electrode.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a high-voltage and low-voltage integrated device, including the following steps:
implanting oxygen ions into one side of the first conductive type substrate through photoetching and ion implantation processes, and forming a buried oxide layer after annealing treatment;
forming a second conductive type epitaxial layer on the first conductive type substrate by adopting an epitaxial process;
forming deep grooves in the second conductive type epitaxial layer and the first conductive type substrate by adopting a deep groove etching process, filling media on two sides of each deep groove to form a media groove, and filling the media groove with polycrystalline silicon to form a polycrystalline silicon filler;
forming a first conductive type second well region in the second conductive type epitaxial layer by adopting photoetching and ion implantation processes, and performing well region diffusion;
growing an oxide layer on the upper surface of the first part of the second conduction type epitaxial layer in a thermal growth mode to form dielectric layer field oxide;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer by adopting photoetching and ion injection processes, forming a first conductive type first well region and a second conductive type depletion channel region on the other side of the upper layer of the second conductive type epitaxial layer after annealing, wherein the second conductive type depletion channel region is positioned on one side of the upper layer of the first conductive type first well region, a second conductive type first well region and a first conductive type first well region are formed between the medium grooves, and the first conductive type first well region is positioned in part of the second conductive type first well region;
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer in a thermal growth mode to form a thin dielectric layer, and photoetching and etching after depositing polycrystalline silicon to form a gate electrode;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer by adopting photoetching and ion injection processes, and forming second conductive type contact and first conductive type contact on the upper layers of the first conductive type first well region, the first conductive type second well region and the second conductive type first well region after annealing;
depositing a metal front medium, photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate to form an electrode.
The invention has the beneficial effects that: based on the BCD process integration technology design concept, the high-voltage vertical type constant current device and the low-voltage device for current regulation are integrated together, the current regulation circuit design of the constant current device is simplified in a single chip integration mode, the system complexity is reduced, the manufacturing cost is saved, the current regulation function of the constant current device can be realized, and the method is suitable for application occasions with different current sizes. The invention adopts partial buried oxide isolation technology to realize the compatibility of high-voltage and low-voltage devices, completely avoids the problems of electric leakage and crosstalk, and has lower cost compared with the traditional SOI process.
Drawings
Fig. 1 is a schematic cross-sectional structural diagram of a high-low voltage integrated device provided in embodiment 1 of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of a high-low voltage integrated device according to embodiment 2 of the present invention;
fig. 3 is a schematic cross-sectional structure diagram of a high-low voltage integrated device according to embodiment 3 of the present invention;
fig. 4 is a schematic cross-sectional structure diagram of a high-low voltage integrated device provided in embodiment 4 of the present invention;
fig. 5 is a schematic cross-sectional structure diagram of a high-low voltage integrated device according to embodiment 5 of the present invention;
fig. 6 is a schematic cross-sectional structure diagram of a high-low voltage integrated device according to embodiment 6 of the present invention;
fig. 7 is a schematic cross-sectional structure diagram of a high-low voltage integrated device according to embodiment 7 of the present invention;
fig. 8 is a schematic cross-sectional structure diagram of a high-low voltage integrated device provided in embodiment 8 of the present invention;
fig. 9 is a schematic cross-sectional structure diagram of a high-low voltage integrated device according to embodiment 9 of the present invention;
fig. 10 is a process flow chart of a method for manufacturing a high-low voltage integrated device according to embodiment 10 of the present invention;
fig. 11 is a process flow chart of a method for manufacturing a high-low voltage integrated device according to embodiment 11 of the present invention;
fig. 12 is a process flow chart of a method for manufacturing a high-low voltage integrated device according to embodiment 12 of the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
c (1) … c (i) … c (n) is a cell structure, i and n are positive integers and represent the number of cells, 101 is a high-voltage vertical constant-current device, 102 is a low-voltage NMOS device, 103 is a low-voltage PMOS device, 104 is a low-voltage NPN device, and 105 is a low-voltage DIODE device; 1 is a second conductive type contact, 2 is a first conductive type contact, 3 is a first conductive type first well region, 4 is a first conductive type second well region, 5 is a second conductive type first well region, 6 is a second conductive type depletion channel region, 7 is a field stop layer, 9 is a second conductive type epitaxial layer, 10 is a first conductive type substrate, 11 is a dielectric trench, 12 is a polysilicon filler, 13 is a buried oxide layer, 21 is a thin dielectric layer, 23 is a dielectric layer field oxide, 25 is a metal front dielectric, 30 is a first emitter metal electrode, 31 is a gate electrode, 32 is a source metal electrode, 33 is a drain metal electrode, 34 is a second emitter metal electrode, 35 is a base metal electrode, 36 is a collector metal electrode, 37 is an anode metal electrode, 38 is a cathode metal electrode, 39 is a body contact electrode, 40 is a back collector metal electrode, 41 is a well region contact electrode, and 42 is a floating metal electrode.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a high-voltage and low-voltage integrated device provided in embodiment 1 of the present invention includes a high-voltage vertical constant current device 101, a low-voltage NMOS device 102, a low-voltage PMOS device 103, a low-voltage NPN device 104, and a low-voltage DIODE device 105 integrated on the same chip;
the high-voltage vertical constant current device 101 is of a bilateral symmetry structure and is divided into a cell area and a terminal area, wherein the cell area is formed by connecting a plurality of cells with the same structure in a parallel manner; the cell structure comprises a back collector metal electrode 40, a first conductive type substrate 10, a second conductive type epitaxial layer 9, a thin dielectric layer 21, a gate electrode 31 and a first emitter metal electrode 30 which are sequentially stacked from bottom to top; the second conductive type epitaxial layer 9 is provided with a first conductive type first well region 3, a second conductive type contact 1, a first conductive type contact 2 and a second conductive type depletion channel region 6;
the first well region 3 of the first conductivity type is positioned at two ends of the upper layer of the epitaxial layer 9 of the second conductivity type, the first conductivity type contact 2, the second conductivity type contact 1 and the depletion channel region 6 of the second conductivity type are sequentially positioned on one side of the upper layer of the first well region 3 of the first conductivity type side by side, the thin dielectric layer 21 is positioned on the epitaxial layer 9 of the second conductivity type between part of the second conductivity type contact 1, the depletion channel region 6 of the second conductivity type and the first well region 3 of the first conductivity type, and the first emitter metal electrode 30 is positioned on the second conductivity type contact 1, the first conductivity type contact 2 and the gate electrode 31;
the terminal region is positioned at two sides of the cellular region and comprises a back collector metal electrode 40, a first conductive type substrate 10, a second conductive type epitaxial layer 9, a dielectric layer field oxide 23, a metal front dielectric 25 and a first emitter metal electrode 30 which are sequentially stacked from bottom to top, and the second conductive type epitaxial layer 9 of the terminal region is provided with first conductive type second well regions 4 which are arranged at equal intervals;
the low-voltage NMOS device 102, the low-voltage PMOS device 103, the low-voltage NPN device 104 and the low-voltage DIODE device 105 are sequentially located in the second conductive type epitaxial layer 9 on one side of the high-voltage vertical type constant current device 101;
the low-voltage NMOS device 102, the low-voltage PMOS device 103, the low-voltage NPN device 104 and the low-voltage DIODE device 105 are also positioned in an isolation region formed by connecting the dielectric groove 11 and the buried oxide layer 13, and positioned in the first conductive type second well region 4 in the isolation region, and the polysilicon filler 12 is positioned inside the dielectric groove 11; the high-voltage device and the low-voltage device are isolated by the isolation region; dielectric layer field oxide 23 is further provided on the upper surface of second conductivity type epitaxial layer 9 between adjacent low voltage devices.
In the above embodiment, in order to have good electrical isolation performance between the high-voltage and low-voltage devices when the back collector metal electrode 40 is connected to a high potential, all the low-voltage devices are placed in the isolation region formed by the dielectric trench 11 and the buried oxide layer 13 in a dielectric isolation manner, so that the problems of leakage and crosstalk between the high-voltage vertical constant current device and the low-voltage devices are completely eliminated.
The low voltage NMOS device 102 includes: the thin dielectric layer 21 is positioned on the first conductive type second well region 4, the gate electrode 31 is positioned on the thin dielectric layer 21, the two second conductive type contacts 1 are positioned on two sides of the gate electrode 31 and positioned in the first conductive type second well region 4, the two second conductive type contacts 1 are respectively provided with a source metal electrode 32 and a drain metal electrode 33, the first conductive type contact 2 is positioned on one side of the two second conductive type contacts 1 and positioned in the first conductive type second well region 4, and the first conductive type contact 2 is provided with a body contact electrode 39;
the low voltage PMOS device 103 includes: the first well region 5 of the second conductivity type is positioned in the second well region 4 of the first conductivity type, the thin dielectric layer 21 positioned on the first well region 5 of the second conductivity type and the gate electrode 31 positioned on the thin dielectric layer 21, two first conductivity type contacts 2 positioned on two sides of the gate electrode 31 and positioned in the first well region 5 of the second conductivity type, a drain metal electrode 33 and a source metal electrode 32 are respectively arranged on the two first conductivity type contacts 2, the second conductivity type contact 1 positioned on one side of the two first conductivity type contacts 2 and positioned in the first well region 5 of the second conductivity type, and a body contact electrode 39 is arranged on the second conductivity type contact 1;
the low voltage NPN device 104 includes: a second conductive type first well region 5 located in the first conductive type second well region 4, a first conductive type first well region 3 located in the second conductive type first well region 5, a second conductive type contact 1 located at one side of the first conductive type first well region 3, a collector metal electrode 36 on the second conductive type contact 1 at one side of the first conductive type first well region 3, a second conductive type contact 1 and a first conductive type contact 2 located on the upper layer of the first conductive type first well region 3 and arranged at intervals, and a base metal electrode 35 and a second emitter metal electrode 34 on the second conductive type contact 1 and the first conductive type contact 2 in the first conductive type first well region 3 respectively;
the low voltage DIODE device 105 includes: the second conductive type first well region 5 is located in the first conductive type second well region 4, and the second conductive type contact 1 and the first conductive type contact 2 are located on the upper layer of the second conductive type first well region 5 and are arranged at intervals, and the second conductive type contact 1 and the first conductive type contact 2 are respectively provided with a cathode metal electrode 38 and an anode metal electrode 37.
The semiconductor material used is silicon or silicon carbide, but is also suitable for other semiconductor materials.
The working principle of the invention is as follows: when the high-voltage vertical constant current device 101 actually works, the back collector metal electrode 40 is connected with a high potential, the emitter metal electrode 30 is grounded, and a gate drive circuit formed by all low-voltage devices controls the potential of the gate electrode 31 of the constant current device. With the increase of the potential of the gate electrode 31, the number of the electron surface charges in the second conductivity type depletion channel region 6 located therebelow increases under the influence of the electric field, so that the resistance value of the second conductivity type depletion channel region 6 is reduced, and the output constant current value of the constant current device is increased. By adjusting the potential of the gate electrode 31 of the constant current device, the function of continuously adjusting the current of the constant current device can be realized, and the constant current device is suitable for application occasions with different current sizes.
As shown in fig. 2, in the high-low voltage integrated device provided in embodiment 2 of the present invention, on the basis of embodiment 1, the first conductivity type second well regions 4 in the isolation region are divided into a plurality of regions, the number of the regions is consistent with the number of the low voltage devices, and a second conductivity type epitaxial layer is disposed between adjacent first conductivity type second well regions 4. By dividing the first conductive type second well region 4 into a plurality of regions, a junction isolation structure of the PNP triode is formed between the low-voltage devices, and the problems of electric leakage and crosstalk between the low-voltage devices can be further prevented by combining the medium isolation structure, so that the reliability of the chip during working is improved.
As shown in fig. 3, in embodiment 3 of the present invention, on the basis of embodiment 1, the first conductive type second well region 4 in the isolation region is extended downward and to both sides to the outside of the isolation region, and the first conductive type contact 2 is further located inside an edge of the first conductive type second well region 4 and connected to the well region contact electrode 41;
the second conductive type first well regions 5 in the low voltage PMOS device 103, the low voltage NPN device 104 and the low voltage DIODE device 105 are all in contact with the buried oxide layer 13.
In the high-low voltage integrated device provided in embodiment 4 of the present invention, on the basis of embodiment 1, the buried oxide layer 13 is located in the second conductive type epitaxial layer 9, as shown in fig. 1; or the buried oxide layer 13 is located in the first conductive type substrate 10 as shown in fig. 4.
As shown in fig. 5, in embodiment 5 of the present invention, on the basis of embodiment 1, a field stop layer 7 is further disposed, where the field stop layer 7 is located between a first conductivity type substrate 10 and a second conductivity type epitaxial layer 9, and the buried oxide layer 13 is located in the first conductivity type substrate 10.
As shown in fig. 6, in the high-voltage and low-voltage integrated device provided in embodiment 6 of the present invention, on the basis of embodiment 1, dielectric trenches 11 are disposed between the first well region 3 of the first conductivity type and the second well region 4 of the first conductivity type of the high-voltage vertical constant current device 101, polysilicon fillers 12 are disposed in the dielectric trenches, and bottoms of the dielectric trenches 11 are located below the second well region 4 of the first conductivity type; a second conductive type contact 1 is arranged at the outermost periphery of the terminal region of the high-voltage vertical constant current device 101 and serves as an electric field stopping ring; the depth of the dielectric groove 11 in the isolation region is consistent with the depth of the dielectric groove 11 in the high-voltage vertical type constant current device.
In the above embodiment, the range of the isolation region surrounded by the dielectric trench 11 should be located inside the region of the first conductivity type second well region 4, and the well region contact electrode 41 is located between the dielectric trench 11 and the edge of the first conductivity type second well region 4, and forms a closed loop structure around the dielectric trench 11, so as to make potential contact with the first conductivity type second well region 4 through the well region contact electrode 41.
As shown in fig. 7, in the high-voltage and low-voltage integrated device provided in embodiment 7 of the present invention, on the basis of embodiment 1, dielectric trenches 11 are disposed in the middle of the first conductive type first well region 3 and the first conductive type second well region 4 in the high-voltage vertical type constant current device 101, polysilicon fillers 12 are disposed in the dielectric trenches, the dielectric trenches 11 in the isolation region and the dielectric trenches 11 in the high-voltage vertical type constant current device extend into the first conductive type substrate 10, the depth of the dielectric trenches 11 in the isolation region is consistent with the depth of the dielectric trenches 11 in the high-voltage vertical type constant current device, and a second conductive type contact 1 is disposed at the outermost periphery of the terminal region of the high-voltage vertical type constant current device 101 to serve as an electric field stop ring.
The high-low voltage integrated device provided in embodiment 8 of the present invention includes a high-voltage vertical constant current device 101, a low-voltage NMOS device 102, a low-voltage PMOS device 103, a low-voltage NPN device 104, and a low-voltage DIODE device 105 integrated on the same chip;
the high-voltage vertical constant current device 101 is of a bilateral symmetry structure and is divided into a cell area and a terminal area, wherein the cell area is formed by connecting a plurality of cells with the same structure in a parallel manner; the cell structure comprises a back collector metal electrode 40, a first conductive type substrate 10, a second conductive type epitaxial layer 9, a thin dielectric layer 21, a gate electrode 31 and a first emitter metal electrode 30 which are sequentially stacked from bottom to top; the second conductive type epitaxial layer 9 is provided with a first conductive type first well region 3, a second conductive type contact 1, a first conductive type contact 2 and a second conductive type depletion channel region 6;
the first well region 3 of the first conductivity type is positioned at two ends of the upper layer of the epitaxial layer 9 of the second conductivity type, the first conductivity type contact 2, the second conductivity type contact 1 and the depletion channel region 6 of the second conductivity type are sequentially positioned on one side of the upper layer of the first well region 3 of the first conductivity type side by side, the thin dielectric layer 21 is positioned on the epitaxial layer 9 of the second conductivity type between part of the second conductivity type contact 1, the depletion channel region 6 of the second conductivity type and the first well region 3 of the first conductivity type, and the first emitter metal electrode 30 is positioned on the second conductivity type contact 1, the first conductivity type contact 2 and the gate electrode 31;
the terminal region is located on two sides of the cell region and comprises a back collector metal electrode 40, a first conductive type substrate 10, a second conductive type epitaxial layer 9, a metal front medium 25 and a floating metal electrode 42 which are sequentially stacked from bottom to top, a first conductive type first well region 3 which is arranged at equal intervals is arranged in the second conductive type epitaxial layer 9 of the terminal region, a first conductive type contact 2 is arranged in the first conductive type first well region 3, and the floating metal electrode 42 is located on the first conductive type contact 2 and the metal front medium 25;
the low-voltage NMOS device 102, the low-voltage PMOS device 103, the low-voltage NPN device 104 and the low-voltage DIODE device 105 are sequentially located in the second conductive type epitaxial layer 9 on one side of the high-voltage vertical type constant current device 101;
the low-voltage NMOS device 102, the low-voltage PMOS device 103, the low-voltage NPN device 104 and the low-voltage DIODE device 105 are also positioned in an isolation region formed by connecting the dielectric groove 11 and the buried oxide layer 13, and the polycrystalline silicon filler 12 is positioned inside the dielectric groove 11; dielectric layer field oxide 23 is further provided on the upper surface of second conductivity type epitaxial layer 9 between adjacent low voltage devices.
Optionally, as shown in fig. 8, the low voltage NMOS device 102, the low voltage PMOS device 103, the low voltage NPN device 104, and the low voltage DIODE device 105 are also located in the first conductivity type second well region 4 within the isolation region.
As shown in fig. 9, in embodiment 9 of the present invention, on the basis of embodiment 8, each low-voltage device is located in an isolation region formed by connecting a dielectric trench 11 and a buried oxide layer 13;
the low-voltage NMOS device 102 is located inside the first conductive type first well region 3, and the first conductive type first well region 3 is located on the upper layer of the second conductive type epitaxial layer 9.
The structure can reduce the use of a mask, reduce the production cost, reasonably optimize the space between the first conductive type first well regions 3 in the terminal of the high-voltage vertical constant current device 101 and ensure the effect of the terminal; the low-voltage devices are isolated by the grooves, so that a better isolation effect can be realized.
As shown in fig. 10, a method for manufacturing a high-voltage and low-voltage integrated device according to embodiment 10 of the present invention includes the following steps:
forming a second conductive type epitaxial layer 9 on the first conductive type substrate 10 by using an epitaxial process;
implanting oxygen ions into one side of the second conductive type epitaxial layer 9 through photoetching and ion implantation processes, and forming a buried oxide layer 13 after annealing treatment;
forming deep grooves at two ends above the buried oxide layer 13 by adopting a deep groove etching process, filling media at two sides of the deep grooves to form a media groove 11, and filling the media groove 11 with polysilicon to form a polysilicon filler 12;
forming a first conductive type second well region 4 on the upper layer of the second conductive type epitaxial layer 9 by adopting photoetching and ion implantation processes, and performing well region diffusion;
growing an oxide layer on the upper surface of the first part of the second conductive type epitaxial layer 9 by adopting a photoetching and thermal growth mode to form a dielectric layer field oxide 23;
respectively injecting first conductive type impurities and second conductive type impurities into a second conductive type epitaxial layer 9 between dielectric layer field oxides 23 by adopting photoetching and ion injection processes, forming a first conductive type first well region 3 and a second conductive type depletion type channel region 6 on the other side of the upper layer of the second conductive type epitaxial layer 9 after annealing, wherein the second conductive type depletion type channel region 6 is positioned on one side of the upper layer of the first conductive type first well region 3, a second conductive type first well region 5 and the first conductive type first well region 3 are formed between dielectric grooves 11, and the first conductive type first well region 3 is positioned in part of the second conductive type first well region 5;
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer 9 in a thermal growth mode to form a thin dielectric layer 21, depositing polycrystalline silicon, and then photoetching and etching to form a gate electrode 31;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer 9 by adopting photoetching and ion injection processes, and forming second conductive type contacts 1 and 2 on the upper layers of the first conductive type first well region 3, the first conductive type second well region 4 and the second conductive type first well region 5 after annealing;
depositing a metal front medium 25, photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate 10 to form an electrode.
As shown in fig. 11, a method for manufacturing a high-voltage and low-voltage integrated device according to embodiment 11 of the present invention includes the following steps:
forming a second conductive type epitaxial layer 9 on the first conductive type substrate 10 by using an epitaxial process;
forming a first conductive type second well region 4 on the second conductive type epitaxial layer 9 by adopting photoetching and ion implantation processes, and performing well region diffusion;
implanting oxygen ions into the first conductivity type second well region 4 on one side of the second conductivity type epitaxial layer 9 through photoetching and ion implantation processes, and forming a buried oxide layer 13 after annealing treatment;
forming a deep groove in the second conductive type epitaxial layer 9 by adopting a deep groove etching process, filling media on two sides of the deep groove to form a media groove 11, and filling the media groove 11 with polycrystalline silicon to form a polycrystalline silicon filler 12;
growing an oxide layer on the upper surface of the first part of the second conductive type epitaxial layer 9 in a thermal growth mode to form a dielectric layer field oxide 23;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer 9 by adopting photoetching and ion injection processes, forming a first conductive type first well region 3 and a second conductive type depletion type channel region 6 on the upper layer of the other side of the second conductive type epitaxial layer 9 after annealing, wherein the second conductive type depletion type channel region 6 is positioned on one side of the upper layer of the first conductive type first well region 3, a second conductive type first well region 5 and the first conductive type first well region 3 are formed between the medium grooves 11, and the first conductive type first well region 3 is positioned in part of the second conductive type first well region 5;
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer in a thermal growth mode to form a thin dielectric layer 21, depositing polycrystalline silicon, and then photoetching and etching to form a gate electrode 31;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer 9 by adopting photoetching and ion injection processes, and forming second conductive type contacts 1 and 2 on the upper layers of the first conductive type first well region 3, the first conductive type second well region 4 and the second conductive type first well region 5 after annealing;
depositing a metal front medium 25, photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate 10 to form an electrode.
As shown in fig. 12, a method for manufacturing a high-voltage and low-voltage integrated device according to embodiment 12 of the present invention includes the following steps:
implanting oxygen ions into one side of the first conductive type substrate 10 by photolithography and ion implantation processes, and forming a buried oxide layer 13 after annealing treatment;
forming a second conductive type epitaxial layer 9 on the first conductive type substrate 10 by using an epitaxial process;
forming deep grooves in the second conductive type epitaxial layer 9 and the first conductive type substrate 10 by adopting a deep groove etching process, filling media on two sides of the deep grooves to form a media groove 11, and filling the media groove 11 with polycrystalline silicon to form a polycrystalline silicon filler 12;
forming a first conductive type second well region 4 in the second conductive type epitaxial layer 9 by adopting photoetching and ion implantation processes, and performing well region diffusion;
growing an oxide layer on the upper surface of the first part of the second conductive type epitaxial layer 9 in a thermal growth mode to form a dielectric layer field oxide 23;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer 9 by adopting photoetching and ion injection processes, forming a first conductive type first well region 3 and a second conductive type depletion type channel region 6 on the other side of the upper layer of the second conductive type epitaxial layer 9 after annealing, wherein the second conductive type depletion type channel region 6 is positioned on one side of the upper layer of the first conductive type first well region 3, a second conductive type first well region 5 and the first conductive type first well region 3 are formed between the medium grooves 11, and the first conductive type first well region 3 is positioned in part of the second conductive type first well region 5;
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer in a thermal growth mode to form a thin dielectric layer 21, depositing polycrystalline silicon, and then photoetching and etching to form a gate electrode 31;
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer 9 by adopting photoetching and ion injection processes, and forming second conductive type contacts 1 and 2 on the upper layers of the first conductive type first well region 3, the first conductive type second well region 4 and the second conductive type first well region 5 after annealing;
depositing a metal front medium 25, photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate 10 to form an electrode.
The high-low voltage integrated device integrates the high-voltage vertical constant current device and the low-voltage device for current regulation based on the BCD process integration technology design concept, simplifies the current regulation circuit design of the constant current device in a single chip integration mode, reduces the system complexity and saves the manufacturing cost. In order to realize the compatibility of a high-voltage device and a low-voltage device, the isolation technology of partial buried oxide is adopted, the implementation is realized through ion implantation and annealing, and the cost is lower than that of the traditional SOI process. The integrated high-voltage vertical constant current device and the low-voltage device have no leakage and crosstalk problems, occupy smaller chip area, can realize the current regulation function of the constant current device, and are suitable for application occasions with different current sizes.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (13)
1. A high-low voltage integrated device comprises a high-voltage vertical constant current device (101), a low-voltage NMOS device (102), a low-voltage PMOS device (103), a low-voltage NPN device (104) and a low-voltage DIODE device (105) which are integrated on the same chip;
the high-voltage vertical constant current device (101) is of a bilateral symmetry structure and is divided into a cell area and a terminal area, and the cell area is formed by connecting a plurality of cells with the same structure in a parallel mode; the cell structure comprises a back collector metal electrode (40), a first conductive type substrate (10), a second conductive type epitaxial layer (9), a thin dielectric layer (21), a gate electrode (31) and a first emitter metal electrode (30) which are sequentially stacked from bottom to top; the second conduction type epitaxial layer (9) is provided with a first conduction type first well region (3), a second conduction type contact (1), a first conduction type contact (2) and a second conduction type depletion channel region (6);
the first well region (3) of the first conduction type is positioned at two ends of the upper layer of the epitaxial layer (9) of the second conduction type, a first conduction type contact (2), a second conduction type contact (1) and a depletion channel region (6) of the second conduction type are sequentially positioned on one side of the upper layer of the first well region (3) of the first conduction type side by side, a thin dielectric layer (21) is positioned on the epitaxial layer (9) of the second conduction type between part of the second conduction type contact (1), the depletion channel region (6) of the second conduction type and the first well region (3) of the first conduction type, and a first emitter metal electrode (30) is positioned on the second conduction type contact (1), the first conduction type contact (2) and a gate electrode (31);
the terminal area is positioned on two sides of the cellular area and comprises a back collector metal electrode (40), a first conductive type substrate (10), a second conductive type epitaxial layer (9), a dielectric layer field oxide (23), a metal front dielectric (25) and a first emitter metal electrode (30) which are sequentially stacked from bottom to top, and first conductive type second well regions (4) which are arranged at equal intervals are arranged in the second conductive type epitaxial layer (9) of the terminal area;
the low-voltage NMOS device (102), the low-voltage PMOS device (103), the low-voltage NPN device (104) and the low-voltage DIODE device (105) are sequentially located in the second conduction type epitaxial layer (9) on one side of the high-voltage vertical type constant current device (101);
the low-voltage NMOS device (102), the low-voltage PMOS device (103), the low-voltage NPN device (104) and the low-voltage DIODE device (105) are also positioned in an isolation region formed by connecting a dielectric groove (11) and a buried oxide layer (13), and positioned in a first conduction type second well region (4) in the isolation region, and a polycrystalline silicon filler (12) is positioned inside the dielectric groove (11); the high-voltage device and the low-voltage device are isolated by the isolation region; and a dielectric layer field oxide (23) is also arranged on the upper surface of the second conductive type epitaxial layer (9) between the adjacent low-voltage devices.
2. A high-low voltage integrated device according to claim 1, characterized in that: the first conduction type second well regions (4) in the isolation region are divided into a plurality of regions, the number of the regions is consistent with the number of low-voltage devices, and a second conduction type epitaxial layer (9) is arranged between every two adjacent first conduction type second well regions (4).
3. A high-low voltage integrated device according to claim 1, characterized in that: the first conduction type second well region (4) in the isolation region extends downwards and towards two sides to the outside of the isolation region, and the first conduction type contact (2) is also positioned on the inner side of the edge of the first conduction type second well region (4) and is connected with a well region contact electrode (41);
the second conductive type first well region (5) in the low-voltage PMOS device (103), the low-voltage NPN device (104) and the low-voltage DIODE device (105) are all contacted with the buried oxide layer (13).
4. A high-low voltage integrated device according to claim 1, characterized in that: the buried oxide layer (13) is located in the second conductivity type epitaxial layer (9); or the buried oxide layer (13) is located in a first conductivity type substrate (10).
5. A high-low voltage integrated device according to claim 1, characterized in that: a field stop layer (7) is further provided, the field stop layer (7) is located between the first conductivity type substrate (10) and the second conductivity type epitaxial layer (9), and the buried oxide layer (13) is located in the first conductivity type substrate (10).
6. A high-low voltage integrated device according to claim 1, characterized in that: a medium groove (11) is formed between the first conductive type first well region (3) and the first conductive type second well region (4) of the high-voltage vertical constant current device (101), polycrystalline silicon fillers (12) are arranged in the medium groove, and the bottom of the medium groove (11) is located below the first conductive type second well region (4); a second conductive type contact (1) is arranged at the outermost periphery of the terminal region of the high-voltage vertical constant current device (101) and serves as an electric field stopping ring; the depth of the dielectric groove (11) in the isolation region is consistent with that of the dielectric groove (11) in the high-voltage vertical type constant current device.
7. A high-low voltage integrated device according to claim 1, characterized in that: the middle of a first conductive type first well region (3) and a first conductive type second well region (4) in the high-voltage vertical type constant current device (101) are both provided with a medium groove (11), polysilicon fillers (12) are arranged in the medium grooves, the medium groove (11) in the isolation region and the medium groove (11) in the high-voltage vertical type constant current device extend into a first conductive type substrate (10), the depth of the medium groove (11) in the isolation region is consistent with that of the medium groove (11) in the high-voltage vertical type constant current device, and a second conductive type contact (1) serving as an electric field stop ring is arranged on the outermost periphery of a terminal region of the high-voltage vertical type constant current device (101).
8. A high-low voltage integrated device comprises a high-voltage vertical constant current device (101), a low-voltage NMOS device (102), a low-voltage PMOS device (103), a low-voltage NPN device (104) and a low-voltage DIODE device (105) which are integrated on the same chip;
the high-voltage vertical constant current device (101) is of a bilateral symmetry structure and is divided into a cell area and a terminal area, and the cell area is formed by connecting a plurality of cells with the same structure in a parallel mode; the cell structure comprises a back collector metal electrode (40), a first conductive type substrate (10), a second conductive type epitaxial layer (9), a thin dielectric layer (21), a gate electrode (31) and a first emitter metal electrode (30) which are sequentially stacked from bottom to top; the second conduction type epitaxial layer (9) is provided with a first conduction type first well region (3), a second conduction type contact (1), a first conduction type contact (2) and a second conduction type depletion channel region (6);
the first well region (3) of the first conduction type is positioned at two ends of the upper layer of the epitaxial layer (9) of the second conduction type, a first conduction type contact (2), a second conduction type contact (1) and a depletion channel region (6) of the second conduction type are sequentially positioned on one side of the upper layer of the first well region (3) of the first conduction type side by side, a thin dielectric layer (21) is positioned on the epitaxial layer (9) of the second conduction type between part of the second conduction type contact (1), the depletion channel region (6) of the second conduction type and the first well region (3) of the first conduction type, and a first emitter metal electrode (30) is positioned on the second conduction type contact (1), the first conduction type contact (2) and a gate electrode (31);
the terminal area is located on two sides of the cellular area and comprises a back collector metal electrode (40), a first conductive type substrate (10), a second conductive type epitaxial layer (9), a metal front medium (25) and a floating metal electrode (42) which are sequentially stacked from bottom to top, first conductive type first well regions (3) which are arranged at equal intervals are arranged in the second conductive type epitaxial layer (9) of the terminal area, first conductive type contacts (2) are arranged in the first conductive type first well regions (3), and the floating metal electrode (42) is located on the first conductive type contacts (2) and the metal front medium (25);
the low-voltage NMOS device (102), the low-voltage PMOS device (103), the low-voltage NPN device (104) and the low-voltage DIODE device (105) are sequentially located in the second conduction type epitaxial layer (9) on one side of the high-voltage vertical type constant current device (101);
the low-voltage NMOS device (102), the low-voltage PMOS device (103), the low-voltage NPN device (104) and the low-voltage DIODE device (105) are also positioned in an isolation region formed by connecting the dielectric groove (11) and the buried oxide layer (13), and the polycrystalline silicon filler (12) is positioned in the dielectric groove (11); and a dielectric layer field oxide (23) is also arranged on the upper surface of the second conductive type epitaxial layer (9) between the adjacent low-voltage devices.
9. A high-low voltage integrated device according to claim 8, characterized in that: the low-voltage NMOS device (102), the low-voltage PMOS device (103), the low-voltage NPN device (104) and the low-voltage DIODE device (105) are also located in the first conduction type second well region (4) in the isolation region.
10. A high-low voltage integrated device according to claim 8, characterized in that: each low-voltage device is positioned in an isolation region formed by connecting the dielectric groove (11) and the buried oxide layer (13);
the low-voltage NMOS device (102) is located inside the first conduction type first well region (3), and the first conduction type first well region (3) is located on the upper layer of the second conduction type epitaxial layer (9).
11. A method for manufacturing a high-low voltage integrated device is characterized by comprising the following steps:
forming a second conductive type epitaxial layer (9) on the first conductive type substrate (10) by adopting an epitaxial process;
implanting oxygen ions into one side of the second conductive type epitaxial layer (9) through photoetching and ion implantation processes, and forming a buried oxide layer (13) after annealing treatment;
forming deep grooves at two ends above the buried oxide layer (13) by adopting a deep groove etching process, filling media at two sides of the deep grooves to form a medium groove (11), and filling the medium groove (11) with polycrystalline silicon to form a polycrystalline silicon filler (12);
forming a first conductive type second well region (4) on the upper layer of the second conductive type epitaxial layer (9) by adopting photoetching and ion implantation processes, and performing well region diffusion;
growing an oxide layer on the upper surface of the first part of the second conductive type epitaxial layer (9) by adopting a photoetching and thermal growth mode to form a dielectric layer field oxide (23);
respectively injecting first conductive type impurities and second conductive type impurities into a second conductive type epitaxial layer (9) between dielectric layer field oxides (23) by adopting photoetching and ion injection processes, forming a first conductive type first well region (3) and a second conductive type depletion type channel region (6) on the other side of the upper layer of the second conductive type epitaxial layer (9) after annealing, wherein the second conductive type depletion type channel region (6) is positioned on one side of the upper layer of the first conductive type first well region (3), forming a second conductive type first well region (5) and a first conductive type first well region (3) between dielectric grooves (11), and the first conductive type first well region (3) is positioned in part of the second conductive type first well region (5);
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer (9) in a thermal growth mode to form a thin dielectric layer (21), and photoetching and etching after depositing polysilicon to form a gate electrode (31);
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer (9) by adopting photoetching and ion injection processes, and forming second conductive type contacts (1) and (2) on the upper layers of the first conductive type first well region (3), the first conductive type second well region (4) and the second conductive type first well region (5) after annealing;
depositing a metal front medium (25), photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate (10) to form an electrode.
12. A method for manufacturing a high-low voltage integrated device is characterized by comprising the following steps:
forming a second conductive type epitaxial layer (9) on the first conductive type substrate (10) by adopting an epitaxial process;
forming a first conductive type second well region (4) on the second conductive type epitaxial layer (9) by adopting photoetching and ion implantation processes, and performing well region diffusion;
implanting oxygen ions into the first conduction type second well region (4) on one side of the second conduction type epitaxial layer (9) through photoetching and ion implantation processes, and forming a buried oxide layer (13) after annealing treatment;
forming a deep groove in the second conductive type epitaxial layer (9) by adopting a deep groove etching process, filling media on two sides of the deep groove to form a medium groove (11), and filling the medium groove (11) with polycrystalline silicon to form a polycrystalline silicon filler (12);
growing an oxide layer on the upper surface of the first part of the second conduction type epitaxial layer (9) in a thermal growth mode to form a dielectric layer field oxide (23);
respectively injecting first conductive type impurities and second conductive type impurities into a second conductive type epitaxial layer (9) by adopting photoetching and ion injection processes, forming a first conductive type first well region (3) and a second conductive type depletion type channel region (6) on the upper layer of the other side of the second conductive type epitaxial layer (9) after annealing, wherein the second conductive type depletion type channel region (6) is positioned on one side of the upper layer of the first conductive type first well region (3), a second conductive type first well region (5) and a first conductive type first well region (3) are formed between medium grooves (11), and the first conductive type first well region (3) is positioned in part of the second conductive type first well region (5);
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer in a thermal growth mode to form a thin dielectric layer (21), and photoetching and etching after depositing polycrystalline silicon to form a gate electrode (31);
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer (9) by adopting photoetching and ion injection processes, and forming second conductive type contacts (1) and (2) on the upper layers of the first conductive type first well region (3), the first conductive type second well region (4) and the second conductive type first well region (5) after annealing;
depositing a metal front medium (25), photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate (10) to form an electrode.
13. A method for manufacturing a high-low voltage integrated device is characterized by comprising the following steps:
implanting oxygen ions into one side of the first conductive type substrate (10) through photoetching and ion implantation processes, and forming a buried oxide layer (13) after annealing treatment;
forming a second conductive type epitaxial layer (9) on the first conductive type substrate (10) by adopting an epitaxial process;
forming deep grooves in the second conductive type epitaxial layer (9) and the first conductive type substrate (10) by adopting a deep groove etching process, filling media on two sides of the deep grooves to form a medium groove (11), and filling the medium groove (11) with polycrystalline silicon to form a polycrystalline silicon filler (12);
forming a first conductive type second well region (4) in the second conductive type epitaxial layer (9) by adopting photoetching and ion implantation processes, and performing well region diffusion;
growing an oxide layer on the upper surface of the first part of the second conduction type epitaxial layer (9) in a thermal growth mode to form a dielectric layer field oxide (23);
respectively injecting first conductive type impurities and second conductive type impurities into a second conductive type epitaxial layer (9) by adopting photoetching and ion injection processes, forming a first conductive type first well region (3) and a second conductive type depletion type channel region (6) on the other side of the upper layer of the second conductive type epitaxial layer (9) after annealing, wherein the second conductive type depletion type channel region (6) is positioned on one side of the upper layer of the first conductive type first well region (3), a second conductive type first well region (5) and a first conductive type first well region (3) are formed between medium grooves (11), and the first conductive type first well region (3) is positioned in part of the second conductive type first well region (5);
growing an oxide layer on the upper surface of the second part of the second conductive type epitaxial layer in a thermal growth mode to form a thin dielectric layer (21), and photoetching and etching after depositing polycrystalline silicon to form a gate electrode (31);
respectively injecting first conductive type impurities and second conductive type impurities into the second conductive type epitaxial layer (9) by adopting photoetching and ion injection processes, and forming second conductive type contacts (1) and (2) on the upper layers of the first conductive type first well region (3), the first conductive type second well region (4) and the second conductive type first well region (5) after annealing;
depositing a metal front medium (25), photoetching and etching the contact hole, depositing a metal layer, and photoetching and etching to form each front metal electrode;
a back metal is deposited under the first conductivity type substrate (10) to form an electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910842339.9A CN110534513B (en) | 2019-09-06 | 2019-09-06 | High-low voltage integrated device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910842339.9A CN110534513B (en) | 2019-09-06 | 2019-09-06 | High-low voltage integrated device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110534513A CN110534513A (en) | 2019-12-03 |
| CN110534513B true CN110534513B (en) | 2022-02-08 |
Family
ID=68667431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910842339.9A Active CN110534513B (en) | 2019-09-06 | 2019-09-06 | High-low voltage integrated device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110534513B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115842029B (en) * | 2023-02-20 | 2024-02-27 | 绍兴中芯集成电路制造股份有限公司 | Semiconductor device and manufacturing method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4543499A (en) * | 1981-04-08 | 1985-09-24 | Hitachi, Ltd. | I2 L circuitry having operating current supplied by higher-voltage circuitry fabricated on same chip |
| US4885628A (en) * | 1984-08-22 | 1989-12-05 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| CN101431057A (en) * | 2008-12-11 | 2009-05-13 | 电子科技大学 | High-capacity BCD technique for twice etching single/poly-silicon |
| CN104638023A (en) * | 2015-02-15 | 2015-05-20 | 电子科技大学 | Vertical current regulative diode and manufacturing method thereof |
| CN105206682A (en) * | 2015-09-09 | 2015-12-30 | 电子科技大学 | Vertical current regulative diode and manufacturing method thereof |
| CN109148444A (en) * | 2018-08-22 | 2019-01-04 | 电子科技大学 | BCD semiconductor device and its manufacturing method |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005116974A (en) * | 2003-10-10 | 2005-04-28 | Seiko Epson Corp | Method of manufacturing semiconductor device |
| KR100808376B1 (en) * | 2006-08-30 | 2008-03-03 | 동부일렉트로닉스 주식회사 | Method for manufacturing of semiconductor device |
| CN101510551B (en) * | 2009-03-30 | 2010-06-09 | 电子科技大学 | High voltage device for drive chip of plasma flat-panel display |
| CN101552291B (en) * | 2009-03-30 | 2012-02-01 | 东南大学 | Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels |
| US8174070B2 (en) * | 2009-12-02 | 2012-05-08 | Alpha And Omega Semiconductor Incorporated | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
| CN102386185A (en) * | 2010-08-30 | 2012-03-21 | 苏州博创集成电路设计有限公司 | High-voltage and low-voltage integrated process device and preparation method thereof |
| CN102194818B (en) * | 2011-04-26 | 2013-01-09 | 电子科技大学 | P-type epitaxial layer-based binary coded decimal (BCD) integrated device and manufacturing method thereof |
| KR20130081547A (en) * | 2012-01-09 | 2013-07-17 | 한국전자통신연구원 | Semiconductor device and method of fabricating the same |
| CN103545363B (en) * | 2012-07-09 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | P type LDMOS device and manufacture method thereof |
| CN103594469B (en) * | 2012-08-17 | 2017-04-12 | 台湾积体电路制造股份有限公司 | Vertical power MOSFET and methods of forming the same |
| CN104779303B (en) * | 2015-02-15 | 2017-08-11 | 电子科技大学 | A kind of vertical current regulative diode and its manufacture method |
| CN105185834B (en) * | 2015-10-19 | 2018-01-26 | 杭州士兰微电子股份有限公司 | Composite high pressure semiconductor devices |
| CN105336736B (en) * | 2015-10-21 | 2019-08-16 | 杭州士兰微电子股份有限公司 | BCD device and its manufacturing method |
| FR3045937A1 (en) * | 2015-12-21 | 2017-06-23 | St Microelectronics Crolles 2 Sas | METHOD FOR MANUFACTURING A JFET TRANSISTOR WITHIN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT. |
| CN108847423B (en) * | 2018-05-30 | 2022-10-21 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor device and method for manufacturing the same |
| CN109065539B (en) * | 2018-08-22 | 2020-10-27 | 电子科技大学 | BCD semiconductor device and manufacturing method thereof |
| CN109216352B (en) * | 2018-09-13 | 2020-10-27 | 电子科技大学 | BCD semiconductor integrated device |
-
2019
- 2019-09-06 CN CN201910842339.9A patent/CN110534513B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4543499A (en) * | 1981-04-08 | 1985-09-24 | Hitachi, Ltd. | I2 L circuitry having operating current supplied by higher-voltage circuitry fabricated on same chip |
| US4885628A (en) * | 1984-08-22 | 1989-12-05 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| CN101431057A (en) * | 2008-12-11 | 2009-05-13 | 电子科技大学 | High-capacity BCD technique for twice etching single/poly-silicon |
| CN104638023A (en) * | 2015-02-15 | 2015-05-20 | 电子科技大学 | Vertical current regulative diode and manufacturing method thereof |
| CN105206682A (en) * | 2015-09-09 | 2015-12-30 | 电子科技大学 | Vertical current regulative diode and manufacturing method thereof |
| CN109148444A (en) * | 2018-08-22 | 2019-01-04 | 电子科技大学 | BCD semiconductor device and its manufacturing method |
Non-Patent Citations (1)
| Title |
|---|
| 600V高低压兼容BCD工艺及驱动电路设计;蒋红利，朱玮，李影，乔明;《微电子学》;20100220;第40卷(第01期);第126-131页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110534513A (en) | 2019-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107017247B (en) | Transient voltage suppressor with low breakdown voltage | |
| US6657262B2 (en) | Monolithically integrated electronic device and fabrication process therefor | |
| US7868394B2 (en) | Metal-oxide-semiconductor transistor and method of manufacturing the same | |
| US10861965B2 (en) | Power MOSFET with an integrated pseudo-Schottky diode in source contact trench | |
| CN109065539B (en) | BCD semiconductor device and manufacturing method thereof | |
| CN110556388A (en) | integrated power semiconductor device and manufacturing method thereof | |
| US20210242342A1 (en) | Semiconductor device and method for manufacturing same | |
| TWI685899B (en) | Enhancements to cell layout and fabrication techniques for mos-gated devices | |
| CN114823872B (en) | Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof | |
| CN104638021B (en) | A kind of horizontal current regulator diode and its manufacture method | |
| US7001806B2 (en) | Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure | |
| CN115312594A (en) | Latch-free lateral IGBT device, manufacturing method and device | |
| CN110534513B (en) | High-low voltage integrated device and manufacturing method thereof | |
| CN110518064B (en) | Semiconductor device and manufacturing method thereof | |
| CN110534581B (en) | Semiconductor device and manufacturing method thereof | |
| US20210296161A1 (en) | Semiconductor Device and Method for Manufacturing Same | |
| CN112054061B (en) | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof | |
| CN111430346B (en) | Power integrated semiconductor device | |
| CN113659011A (en) | Integrated device based on super junction MOSFET and manufacturing method thereof | |
| CN111739938A (en) | Semiconductor device with a plurality of transistors | |
| CN110491889B (en) | SOI transverse constant current diode and manufacturing method thereof | |
| CN116741772B (en) | Semiconductor device and electronic equipment | |
| CN114784083B (en) | Hybrid vertical power device, manufacturing method and electronic equipment | |
| CN113990942B (en) | LDMOS device with circularly symmetric structure and preparation method thereof | |
| CN113035948B (en) | Power device, power electronic equipment and manufacturing method of power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |