CN114725015A - Display substrate, manufacturing method thereof and display device - Google Patents

Display substrate, manufacturing method thereof and display device Download PDF

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Publication number
CN114725015A
CN114725015A CN202210303696.XA CN202210303696A CN114725015A CN 114725015 A CN114725015 A CN 114725015A CN 202210303696 A CN202210303696 A CN 202210303696A CN 114725015 A CN114725015 A CN 114725015A
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layer
metal oxide
active layer
gate insulating
insulating layer
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杨维
付雨婷
余吉吉
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors

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Abstract

The application provides a display substrate, a manufacturing method thereof and a display device, wherein the manufacturing method of the display substrate comprises the following steps: providing a substrate base plate; sequentially forming a first active layer, a first gate insulating layer, a first gate electrode, a second gate insulating layer, a second gate electrode, a first interlayer dielectric layer and a third gate insulating layer on a substrate; forming a via hole above the first active layer, wherein the via hole penetrates through the third gate insulating layer and extends to the first active layer; depositing a metal oxide layer, wherein the metal oxide layer covers the first active layer at the position of the via hole; performing high-temperature annealing to improve the subthreshold swing of the first active layer; and patterning the metal oxide layer to form a second active layer. The method and the device save the etching process procedure, and basically avoid the problems of low process stability and poor product display caused by etching.

Description

Display substrate, manufacturing method thereof and display device
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
Background
The semiconductor type used in an OLED (Organic Light-Emitting Diode) display panel mainly includes three types, i.e., LTPO (Low Temperature Polycrystalline Oxide), LTPS (Low Temperature Poly-silicon), and Oxide. The LTPO semiconductor combines the LTPS semiconductor and the Oxide semiconductor, has the advantages of the LTPS semiconductor, high mobility and fast charging, has the advantages of the Oxide, and has the advantages of low leakage current and low power consumption. Therefore, the OLED display panel using the LTPO semiconductor is a mainstream development trend in the industry.
The LTPO semiconductor process includes LTPS TFT and Oxide TFT. Wherein, according to different film layer structures, Oxide TFT can be subdivided into Top Gate, BCE and EXL structures. At present, LTPO semiconductors with Top Gate structures (referred to as LTPO Oxide Top Gate structures) are the mainstream development structures, but compared with LTPO semiconductors with BCE structures (referred to as LTPO Oxide BCE structures), the LTPO semiconductors with Top Gate structures have complex process procedures and high process cost. However, LTPO semiconductors with BCE structure have poor process stability, which becomes a major factor restricting their development.
Disclosure of Invention
The application provides a display substrate, a manufacturing method thereof and a display device, which aim to improve the process stability of the display substrate with the conventional LTPO Oxide BCE structure.
According to a first aspect of the embodiments of the present application, there is provided a method for manufacturing a display substrate, including:
providing a substrate base plate;
sequentially forming a first active layer, a first gate insulating layer, a first gate electrode, a second gate insulating layer, a second gate electrode, a first interlayer dielectric layer and a third gate insulating layer on the substrate base plate;
forming a via hole over the first active layer, wherein the via hole penetrates through the third gate insulating layer and extends to the first active layer;
depositing a metal oxide layer for forming a second active layer, wherein the metal oxide layer covers the first active layer at the via location;
performing high-temperature annealing to improve the subthreshold swing of the first active layer;
and patterning the metal oxide layer to form a second active layer.
In one embodiment, depositing a metal oxide layer for forming the second active layer includes:
and depositing a metal oxide layer for forming a second active layer on the surface of the third gate insulating layer and the hole bottom and the hole wall of the through hole.
In one embodiment, patterning the metal oxide layer to form the second active layer includes:
and etching the metal oxide layer in the through hole, and patterning the metal oxide layer on the surface of the third gate insulating layer to form a second active layer.
In one embodiment, patterning the metal oxide layer to form a second active layer includes:
and reserving the metal oxide layer in the through hole, and patterning the metal oxide layer on the surface of the third insulating layer to form a second active layer.
In one embodiment, after forming the second active layer, a first source electrode and a first drain electrode are further formed, which specifically includes the steps of:
depositing a metal layer on the metal oxide layer in the via, on the third insulating layer, and on the second active layer;
and patterning the metal layer to form the first source electrode and the first drain electrode.
In one embodiment, the metal oxide layer in the via extends to a surface of the third insulating layer.
In one embodiment, the material of the metal oxide layer is IGZO, IZO or GZO.
In one embodiment, the third gate insulating layer is made of SiO.
According to a second aspect of the embodiments of the present application, there is provided a display substrate manufactured according to any one of the above manufacturing methods.
According to a third aspect of the embodiments of the present application, there is provided a display device including the display substrate manufactured by any one of the above manufacturing methods.
The technical scheme provided by the embodiment of the application has the following beneficial effects:
when the display substrate is manufactured by the method, the exposed first active layer is covered by the metal oxide layer before high-temperature annealing. Therefore, during high-temperature annealing, the oxide layer is not formed on the surface of the first active layer, so that after the high-temperature annealing, the oxide layer on the surface of the first active layer is not required to be removed by etching, and an etching process is omitted, thereby basically avoiding the defect of the third gate insulating layer caused by etching, and further basically avoiding the problems of low process stability and poor product display caused by etching. And an etching process is omitted, and the process cost is effectively reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
FIGS. 1 a-1 d are flow charts illustrating the fabrication of a display substrate according to one embodiment of the present invention;
FIG. 2 is a defect diagram of the third gate insulating layer at the second gate chamfer;
FIG. 3 is a surface topography of the third gate insulation layer before etching;
FIG. 4 is a cross-sectional profile of the third gate insulating layer before etching;
FIG. 5 is a surface topography of the third gate insulating layer after etching;
FIG. 6 is a cross-sectional profile of the third gate insulating layer after etching;
FIG. 7 is a flowchart illustrating steps of a display substrate according to an embodiment of the present disclosure;
FIGS. 8 a-8 c are flow charts illustrating the fabrication of a display substrate according to an embodiment of the present disclosure;
FIG. 9 is a schematic view of another structure of a display substrate provided in an embodiment of the present application;
fig. 10 is a flowchart illustrating another step of a display substrate according to an embodiment of the present disclosure.
The various references in the drawings are:
a first active layer-1'; a first gate insulating layer-2'; a first gate-3'; a second gate insulating layer-4'; a second gate-5'; a first interlayer dielectric layer-6'; a third gate insulating layer-7'; a second active layer-8'; a first source-9'; a first drain-10'; a via-11';
a first active layer-1; a first gate insulating layer-2; a first gate-3; a second gate insulating layer-4; a second gate-5; a first interlayer dielectric layer-6; a third gate insulating layer-7; a metal oxide layer-8; a second active layer-81; a via-9; a first buffer layer-10.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
In the prior art, the basic process of the display substrate using the LTPO Oxide BCE structure mainly includes:
sequentially forming a first active layer 1 ', a first gate insulating layer 2 ', a first gate electrode 3 ', a second gate insulating layer 4 ', a second gate electrode 5 ', a first interlayer dielectric layer 6 ' and a third gate insulating layer 7 ' on a substrate base plate, as shown in fig. 1 a;
forming a via 11 'over the first active layer 1', as shown in fig. 1 b;
performing high-temperature annealing to improve the subthreshold swing of the first active layer 1';
etching (Etch) away the oxide on the surface of the first active layer 1 ', wherein the oxide on the surface of the first active layer 1' is formed during high temperature annealing;
forming a second active layer 8', as shown in fig. 1 c;
and forming subsequent film layers, for example, as shown in fig. 1d, forming a first source 9 'and a first drain 10' (the first source 9 'and the first drain 10' may be simply referred to as source and drain, i.e., SD), and completing the fabrication of the display substrate.
However, the display substrate manufactured by the above process has a problem of process stability.
The inventors have found, through extensive studies, that the material of the third gate insulating layer 7' is a SiO (silicon oxide) thin film. The film quality of the SiO film is relatively poor, and when the oxide on the surface of the first active layer 1' is etched, the SiO film is easily damaged by etching, thereby causing two problems:
1) as shown in fig. 2, the SiO film is prone to generate a defect (Crack) at the chamfer of the second gate 5 ', so that the second gate 5' is prone to generate a short circuit (short) with the SD at the defect, resulting in a poor product display;
2) as shown in fig. 3 and 4, before the etching process, the surface of the SiO film is smooth and the roughness is small; however, as shown in fig. 5 and 6, after the etching process, the surface of the SiO thin film becomes uneven and has a large roughness, and in a severe case, the surface of the SiO thin film may even have pin-holes (pin-holes). Since the SiO thin film is a gate insulating layer in contact with the channel of the second active layer 8 ', pinholes and roughness on the surface of the SiO thin film may affect the characteristic stability of the second active layer 8'.
To this end, an embodiment of the present application provides a method for manufacturing a display substrate, as shown in fig. 7, which specifically includes the steps of:
step S10, providing a base substrate;
step S20, sequentially forming a first active layer 1, a first gate insulating layer 2, a first gate electrode 3, a second gate insulating layer 4, a second gate electrode 5, a first interlayer dielectric layer 6, and a third gate insulating layer 7 on a substrate;
step S30, forming a via hole 9 above the first active layer 1, as shown in fig. 8 a;
step S40, depositing the metal oxide layer 8 for forming the second active layer 81, and covering the first active layer 1 at the position of the via hole 9 by the metal oxide layer 8, as shown in fig. 8 b;
step S50, performing high temperature annealing to improve the subthreshold swing of the first active layer 1;
in step S60, the metal oxide layer 8 is patterned to form a second active layer 81, as shown in fig. 8 c.
The display substrate is fabricated by the above method, and the exposed first active layer 1 is covered with the metal oxide layer 8 before high temperature annealing (CNT Anneal) is performed. Therefore, during high-temperature annealing, an oxide layer is not formed on the surface of the first active layer 1, so that after the high-temperature annealing, the oxide layer on the surface of the first active layer 1 does not need to be removed by etching, and an etching process is omitted, thereby basically avoiding the defect of the third gate insulating layer 7 caused by etching, and further basically avoiding the problems of low process stability and poor product display caused by etching. And the etching process is omitted, and the process cost is effectively reduced.
In step S10, the base substrate may be made of glass, and is preferably white glass. The white glass has higher permeability.
In step S20, the first active layer 1, the first gate insulating layer 2, the first gate electrode 3, the second gate insulating layer 4, the second gate electrode 5, the first interlayer dielectric layer 6, and the third gate insulating layer 7 may be formed by a single patterning process.
The first active layer 1 may also be referred to as an LTPS TFT. The material of the first active layer 1 is preferably p-Si (polysilicon), which has a high electron transfer rate. After the first active layer 1 is formed, it is necessary to repair defects in the interior and on the surface thereof by hydrogen (H). However, hydrogen has low stability and easily escapes from the surface of the first active layer 1.
The material of the first gate insulating layer 2 and the second gate insulating layer 4 is preferably SiO2(silicon oxide), SiO2Has better stability.
The material of the third gate insulating layer 7 is preferably SiO (silicon oxide). The SiO may form a protection for the second active layer 81 (also referred to as Oxide TFT), and reduce the influence of hydrogen (H) escaped from the first active layer 1 on the second active layer 81 after the via hole 9 is disposed above the first active layer 1.
The first gate 3 and the second gate 5 located directly above it are used to form a pixel capacitance. The second gate 5 located obliquely above the first gate 3 serves as a bottom gate of the Oxide semiconductor portion.
Further, other film layers, such as a Polyimide (PI) layer, a Barrier (Barrier) layer, and/or a first Buffer (Buffer) layer, may be formed between the first active layer 1 and the substrate according to requirements. At this time, when the display substrate is manufactured, other film layers are formed on the base substrate, and then the first active layer 1 and the like are formed over the other film layers.
In step S30, the via hole 9 may be formed by a mask process. The via hole 9 extends upward from the first active layer 1 to penetrate through the third gate insulating layer 7, so that the first active layer 1 is exposed. The aperture of the via hole 9 is in the micron order to ensure good contact between the first source electrode and the first drain electrode deposited in the via hole 9 and the first active layer 1, and to facilitate deposition of the metal oxide layer 8 in the via hole 9. In a specific example, the aperture of the via 9 is 20-80 μm.
In step S40, metal oxide layers 8 are deposited on the surface of the third gate insulating layer 7 and the bottom and wall of the via hole 9, and the third gate insulating layer 7 and the exposed first active layer 1 are covered by the metal oxide layers 8. The metal oxide layer 8 is deposited on both the bottom and the wall of the via hole 9, that is, the metal oxide layer 8 is not completely filled in the via hole 9, but the metal oxide layer 8 is deposited only on the bottom and the wall of the via hole 9. Thus, the metal oxide layer 8 can form better protection for the third gate insulating layer 7 and the exposed first active layer 1, and the subthreshold swing of the first active layer 1 can be improved without basically influencing high-temperature annealing.
The thickness of the metal oxide layer 8 on the surface of the third gate insulating layer 7 may be in the nanometer range, i.e., a numerical range greater than 1nm and less than 1000 nm. Optionally, the thickness of the metal oxide layer 8 on the surface of the third gate insulating layer 7 is 100-500nm, which includes 100nm and 500 nm. Preferably, the thickness of the metal oxide layer 8 on the surface of the third gate insulating layer 7 is 100-200nm, including 100nm and 200 nm. When the metal oxide layer 8 is deposited, the thickness of the metal oxide layer 8 on the surface of the third gate insulating layer 7 may be greater than the thickness of the metal oxide layer 8 in the via hole 9, depending on the deposition process. When the metal oxide layer 8 on the surface of the third gate insulating layer 7 is hundreds of nanometers, the thickness of the metal oxide layer 8 in the via hole 9 is tens of nanometers, and at this time, the metal oxide layer 8 can meet the thickness requirement for forming the second active layer 81, and basically does not affect the improvement of the Subthreshold swing (ss for short) of the first active layer 1.
The material of the metal oxide layer 8 may be any one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and GZO (gallium zinc oxide). Preferably, the metal oxide layer 8 is made of IGZO, which has a high electron mobility and good stability.
In step S50, the subthreshold swing is an important parameter when the MOSFET is operated in the subthreshold state and used as a logic switch, and is also referred to as an S factor. It is defined as: s-dgvgs/d (log10 Id) in mV/dec.
Hydrogen on the surface of the first active layer 1 is unstable and needs to be annealed at a high temperature. After high-temperature annealing, hydrogen on the surface of the first active layer 1 escapes, so that the number of defects on the surface of the first active layer 1 is increased, and the subthreshold swing of the first active layer 1 is increased.
When the metal oxide layer 8 is deposited on the surface of the first active layer 1 and then annealed at a high temperature, hydrogen on the surface of the first active layer 1 can still escape, and the metal oxide layer 8 has no influence on improving the subthreshold swing of the first active layer 1.
The annealing time and the annealing temperature in the high-temperature annealing are substantially the same as those in the normal high-temperature annealing.
In step S60, the second active layer 81 may be formed through a mask process. At this time, the metal oxide layer 8 in the via hole 9 may remain (as shown in fig. 9) or may be etched away. The pattern of the mask is set according to the requirement.
When the metal oxide layer 8 is remained in the via hole 9, the first active layer 1 can be protected by the metal oxide layer 8, and the risk that the first active layer 1 is oxidized in the subsequent manufacturing process is reduced.
Further, when the metal oxide layer 8 remains in the via 9, the metal oxide layer 8 in the via 9 extends to the surface of the third insulating layer to reduce the risk of peeling off the metal oxide layer 8 in the via 9. The width of the metal oxide layer 8 in the via hole 9 extending to the surface of the third insulating layer can be specifically set according to requirements.
After the second active layer 81 is formed, a subsequent film layer is continuously formed, and the manufacturing of the display substrate is completed. The subsequent film layer is the same as the normal subsequent film layer, and includes, for example, a first source electrode, a first drain electrode, and the like.
Note that, when the metal oxide layer 8 remains in the via hole 9, then the metal layer constituting the first source electrode and the first drain electrode is deposited on the metal oxide layer 8 in the via hole 9, and the metal layer is in direct contact with the metal oxide layer 8 in the via hole 9.
The second embodiment of the present application provides another manufacturing method of a display substrate, as shown in fig. 10, specifically including the steps of:
step S10, providing a base substrate;
step S20, sequentially forming a first active layer 1, a first gate insulating layer 2, a first gate electrode 3, a second gate insulating layer 4, a second gate electrode 5, a first interlayer dielectric layer 6, and a third gate insulating layer 7 on a substrate;
step S30, forming a via hole 9 above the first active layer 1;
step S40, depositing the metal oxide layer 8 for forming the second active layer 81, and covering the first active layer 1 at the position of the via hole 9 by the metal oxide layer 8;
step S50, patterning the metal oxide layer 8 to form a second active layer 81;
step S60, performing high temperature annealing to improve the subthreshold swing of the first active layer 1.
In this manufacturing method, when step S50 is performed, that is, when the metal oxide layer 8 is patterned, the metal oxide layer 8 in the via hole 9 needs to be left. When the step S60, i.e., the high temperature annealing, is performed, the first active layer 1 is protected by the metal oxide layer 8, preventing the first active layer 1 from being oxidized. Thus, after high-temperature annealing, the oxide layer on the surface of the first active layer 1 does not need to be removed by etching, and the etching process is omitted, so that the defect of the third gate insulating layer 7 caused by etching is basically avoided, and the problems of low process stability and poor product display caused by etching are basically avoided. And the etching process is omitted, and the process cost is effectively reduced.
In step S10, the material of the base substrate may be glass, and white glass is preferable.
In step S20, the first active layer 1, the first gate insulating layer 2, the first gate electrode 3, the second gate insulating layer 4, the second gate electrode 5, the first interlayer dielectric layer 6, and the third gate insulating layer 7 may be formed by a single patterning process.
The material of the first active layer 1 is preferably p-Si. After the first active layer 1 is formed, it is necessary to repair defects in and on the surface thereof by hydrogen (H). The material of the first gate insulating layer 2 and the second gate insulating layer 4 is preferably SiO2. The material of the third gate insulating layer 7 is preferably SiO.
Other film layers, such as a polyimide layer, a barrier layer and/or a first buffer layer 10, etc., may be formed between the first active layer 1 and the substrate as required.
In step S30, via holes 9 may be formed using a reticle process. The aperture of the via 9 is in the order of microns, in a specific example the aperture of the via 9 is 20-80 μm.
In step S40, metal oxide layers 8 are deposited on the surface of the third gate insulating layer 7 and the bottom and wall of the via hole 9, and the third gate insulating layer 7 and the exposed first active layer 1 are covered by the metal oxide layers 8.
The thickness of the metal oxide layer 8 on the surface of the third gate insulating layer 7 may be in the order of nanometers. Preferably, the thickness of the metal oxide layer 8 on the surface of the third gate insulating layer 7 is 100-500nm, including 100nm and 500 nm. More preferably, the thickness of the metal oxide layer 8 on the surface of the third gate insulating layer 7 is 100-200nm, including 100nm and 200 nm.
The material of the metal oxide layer 8 may be any one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and GZO (gallium zinc oxide).
In step S50, the second active layer 81 may be formed through a mask process. The metal oxide layer 8 in the via 9 extends to the surface of the third insulating layer.
In step S60, the annealing time and annealing temperature during the high-temperature annealing are substantially the same as those during the normal high-temperature annealing.
After the second active layer 81 is formed, a subsequent film layer is continuously formed, and the manufacturing of the display substrate is completed. The subsequent film layer is the same as the normal subsequent film layer, and includes, for example, a first source electrode, a first drain electrode, and the like. A metal layer constituting the first source and the first drain is deposited on the metal oxide layer 8 in the via hole 9, the metal layer being in direct contact with the metal oxide layer 8 in the via hole 9.
The third embodiment of the present application provides a display substrate. The display substrate is manufactured according to the first embodiment or the second embodiment. In this display substrate, the exposed first active layer 1 is covered with a metal oxide layer 8 before high temperature annealing is performed. Therefore, during high-temperature annealing, an oxide layer is not formed on the surface of the first active layer 1, so that after the high-temperature annealing, the oxide layer on the surface of the first active layer 1 does not need to be removed by etching, and an etching process is omitted, thereby basically avoiding the defect of the third gate insulating layer 7 caused by etching, and further basically avoiding the problems of low process stability and poor product display caused by etching. And the etching process is omitted, and the process cost is effectively reduced.
The fourth embodiment of the application provides a display device. The display device includes a display substrate fabricated according to the first embodiment or the second embodiment. In this display substrate, the exposed first active layer 1 is covered with a metal oxide layer 8 before high temperature annealing is performed. Therefore, during high-temperature annealing, an oxide layer is not formed on the surface of the first active layer 1, so that after the high-temperature annealing, the oxide layer on the surface of the first active layer 1 does not need to be removed by etching, and an etching process is omitted, thereby basically avoiding the defect of the third gate insulating layer 7 caused by etching, and further basically avoiding the problems of low process stability and poor product display caused by etching. And the etching process is omitted, and the process cost is effectively reduced.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A manufacturing method of a display substrate is characterized by comprising the following steps:
providing a substrate base plate;
sequentially forming a first active layer, a first gate insulating layer, a first gate electrode, a second gate insulating layer, a second gate electrode, a first interlayer dielectric layer and a third gate insulating layer on the substrate base plate;
forming a via hole over the first active layer, wherein the via hole penetrates through the third gate insulating layer and extends to the first active layer;
depositing a metal oxide layer for forming a second active layer, wherein the metal oxide layer covers the first active layer at the via location;
performing high-temperature annealing to improve the subthreshold swing of the first active layer;
and patterning the metal oxide layer to form a second active layer.
2. The method for manufacturing a display substrate according to claim 1, wherein depositing the metal oxide layer for forming the second active layer comprises:
and depositing a metal oxide layer for forming a second active layer on the surface of the third gate insulating layer and the hole bottom and the hole wall of the through hole.
3. The method for manufacturing a display substrate according to claim 2, wherein the patterning of the metal oxide layer to form the second active layer comprises:
and etching the metal oxide layer in the through hole, and patterning the metal oxide layer on the surface of the third gate insulating layer to form a second active layer.
4. The method for manufacturing a display substrate according to claim 2, wherein the patterning of the metal oxide layer to form the second active layer comprises:
and reserving the metal oxide layer in the through hole, and patterning the metal oxide layer on the surface of the third insulating layer to form a second active layer.
5. The method for manufacturing a display substrate according to claim 4, wherein after the second active layer is formed, a first source electrode and a first drain electrode are further formed; forming a first source electrode and a first drain electrode, and specifically comprising the steps of:
depositing a metal layer on the metal oxide layer in the via, on the third insulating layer, and on the second active layer;
and patterning the metal layer to form the first source electrode and the first drain electrode.
6. The method for manufacturing the display substrate according to claim 4, wherein the metal oxide layer in the via hole extends to a surface of the third insulating layer.
7. The method for manufacturing a display substrate according to any one of claims 1 to 6, wherein the metal oxide layer is made of IGZO, IZO or GZO.
8. The method of manufacturing a display substrate according to any one of claims 1 to 6, wherein the third gate insulating layer is made of SiO.
9. A display substrate manufactured by the method according to any one of claims 1 to 8.
10. A display device comprising the display substrate manufactured by the manufacturing method according to any one of claims 1 to 8.
CN202210303696.XA 2022-03-24 2022-03-24 Display substrate, manufacturing method thereof and display device Pending CN114725015A (en)

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