CN114664654A - Semiconductor photoetching method - Google Patents
Semiconductor photoetching method Download PDFInfo
- Publication number
- CN114664654A CN114664654A CN202210571637.0A CN202210571637A CN114664654A CN 114664654 A CN114664654 A CN 114664654A CN 202210571637 A CN202210571637 A CN 202210571637A CN 114664654 A CN114664654 A CN 114664654A
- Authority
- CN
- China
- Prior art keywords
- sio
- laser
- film
- wavelength
- single pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70008—Production of exposure light, i.e. light sources
- G03F7/70025—Production of exposure light, i.e. light sources by lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
Abstract
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor photoetching method which comprises the step S01 of preparing SiO on a silicon wafer2Film of SiO2The uniformity of the film thickness is controlled within 10 percent; step S02, in SiO2Selecting a membrane breaking area on the membrane; SiO in the film-breaking zone by laser pulses2Deep grooves are first cut on the film, and then the whole SiO is etched2The film is subjected to a chemical etching process to form SiO2The film thickness is reduced to SiO at the bottom of the deep groove2Removing the film to reach the surface of the silicon wafer; step S03, obtaining SiO on the silicon wafer2The pattern of the film. The chip manufacturing process is simplified, the cost is reduced, and the chip is more environment-friendly and convenient.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor photoetching method.
Background
In the case of chip fabrication, it has to be said that photolithography, which is an important step in the fabrication of semiconductor devices, is used to obtain SiO on a silicon wafer2Pattern of filmThe SiO is required to be prepared on a silicon wafer in sequence2Film → photoresist → pattern formation by exposure → development → film → soaking in etching solution for chemical etching → photoresist removal; therefore, in the conventional photolithography process, patterns on the photomask are transferred to the substrate by an etching process, and the conventional process requires a lithography machine, a photoresist and a photolithography mask, which are undoubtedly short boards of the current photolithography technique in China, and influence the progress of the current semiconductor photolithography technique in China.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, a semiconductor photoetching method is provided, and the problems of complex chip manufacturing process and high cost caused by the fact that a photoetching machine, photoresist and a photoetching plate are required in the traditional photoetching process are solved.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a semiconductor lithography method is provided, comprising
Step S01, preparing SiO on the silicon chip2Film of SiO2The uniformity of the film thickness is controlled within 10 percent;
step S02, in SiO2Selecting a membrane disruption area on the membrane;
SiO in the film-breaking zone by laser pulses2The film is first cut into deep grooves and then the whole SiO2The film is subjected to a chemical etching process to form SiO2The film thickness is reduced to SiO at the bottom of the deep groove2Removing the film to reach the surface of the silicon wafer;
step S03, obtaining SiO on the silicon wafer2The pattern of the film.
Further, in step S02, SiO2The film is etched to SiO on the bottom of the deep trench before chemical etching2The film is textured to improve the roughness of the bottom surface of the deep groove.
Furthermore, the laser emits a pulse laser string group, the single pulse form of the pulse laser string group can be modulated, namely the time and the intensity of a single pulse can be controlled by programming, the number of pulses of each pulse string can be set, and the relative intensity can be set;
wherein, the interval between the pulses of the pulse laser string group is less than or equal to 1000 ns.
Further, the laser adopts
Nanosecond green laser with wavelength of 532nm and single pulse width of 1-100 ns, or
Nanosecond UV laser with wavelength of 355nm and single pulse width of 1-100 ns, or
Picosecond green laser with wavelength of 532nm and single pulse width of 3-50 ps, or
Picosecond UV laser with a wavelength of 355nm and a single pulse width of 3-50 ps, or
An infrared femtosecond laser with wavelength of 1064nm and single pulse width of 3-50 ps, or
A green femtosecond laser with a wavelength of 532nm and a single pulse width of 100fs-900fs, or
An ultraviolet femtosecond laser with a wavelength of 355nm and a single pulse width of 100fs-900fs, or
The wavelength of the deep ultraviolet femtosecond laser is less than or equal to 266nm, and the single pulse width is 100fs-900 fs.
The invention has the beneficial effects that:
the semiconductor photoetching method of the invention directly uses laser to remove SiO originally removed by photoetching2And (3) a membrane. Can directly obtain SiO without the processes of photoresist, photoetching plate, exposure development, etching and photoresist removal2The pattern of the film. Part of the photolithography process may be replaced. Therefore, the chip manufacturing process is simplified, the cost is reduced, and the chip is more environment-friendly and convenient.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a diagram showing a configuration of a pulse laser burst set according to a second embodiment;
FIG. 2 is a view of SiO on a silicon wafer in the third embodiment2Schematic diagram of the film after cutting deep groove;
FIG. 3 is SiO 2 on silicon wafer of example III2Schematic representation of the film after chemical etching;
wherein the content of the first and second substances,
1. silicon wafer, 2, SiO2Film, 21, deep trench;
3. a single laser pulse.
Detailed Description
The invention will now be further described with reference to specific examples. These drawings are simplified schematic diagrams only illustrating the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
Example one
A semiconductor lithography method comprises
Step S01, preparing SiO on the silicon wafer 12 Film 2, SiO2The thickness uniformity of the film 2 is controlled within 10 percent;
step S02, in SiO2Selecting a film breaking area on the film 2, adopting a laser to emit laser pulses to the film breaking area, and enabling SiO (silicon dioxide) of the film breaking area to be subjected to laser pulses2Removing the film 2 and directly reaching the silicon wafer 1;
step S03, obtaining SiO on the silicon wafer 12The pattern of the film 2.
In this example, SiO2The membrane 2 is prepared by a dry method or a wet method; SiO 22The thickness of the film 2 is 0.5-3 microns in the field of semiconductor chips, and the SiO of partial photovoltaic cells2The thickness is generally 50-1000 nm.
In this embodiment, the laser is one of the following lasers:
nanosecond green laser with wavelength of 532nm and single pulse width of 1-100 ns, or
Nanosecond UV laser with wavelength of 355nm and single pulse width of 1-100 ns, or
Picosecond green laser with wavelength of 532nm and single pulse width of 3-50 ps, or
Picosecond ultraviolet laser with wavelength of 355nm and single pulse width of 3-50 ps, or
An infrared femtosecond laser with wavelength of 1064nm and single pulse width of 3-50 ps, or
A green femtosecond laser with a wavelength of 532nm and a single pulse width of 100fs-900fs, or
An ultraviolet femtosecond laser with wavelength of 355nm and single pulse width of 100fs-900fs, or
The wavelength of the deep ultraviolet femtosecond laser is less than or equal to 266nm, and the single pulse width is 100fs-900 fs.
In the embodiment, when the laser emits laser, the laser can be used together with a beam shaping device and a galvanometer, wherein the beam shaping device is used for shaping the passing laser and regulating and controlling the energy distribution form of light spots; the galvanometer is used for moving the position of the passing laser to remove any pattern. The principle structure of the beam shaper and the galvanometer belongs to the prior art, and is not described in detail.
When the film is broken by the laser, the removal resolution is regulated and controlled by the wavelength of the laser, the single-pulse energy density of the laser, the single-pulse time width, the spot size, the energy distribution form and the like.
The removal depth is regulated and controlled by the number of pulses of the laser continuously irradiating the surface of the material at the same position or the number of times of scanning the same position by repeatedly moving the light beam.
For example, assuming a theoretical state that the thickness of the actual oxide film is 400nm and the resolution of the laser in the removal depth direction is 400nm, the laser can remove the SiO in the film breaking region after the film breaking2The film 2 is used for realizing bottom sinking, namely the upper surface of the bottom silicon wafer 1 is not damaged;
assuming a state where the actual oxide film thickness is 400nm and the laser resolution in the removal depth direction is 500nm, the laser is removing 400nmSiO2The film 2 also removes the 100nm silicon wafer 1, which is damaging to the substrate.
Some products can accept silicon wafer damage, and some products can not accept silicon wafer damage, and can be selected according to actual conditions.
Example two
The semiconductor lithography method of the present embodiment is based on the first embodiment, and is different in that the laser of the present embodiment can emit a pulse laser train, the single pulse form of the pulse laser train can be modulated, that is, the time and the intensity of a single pulse can be programmed and controlled, and the number of pulses of each train of pulses can be set, and the relative intensity can be set; wherein, the interval between the pulses of the pulse laser string group is less than or equal to 1000 ns.
FIG. 1 is a schematic diagram of a pulsed laser train; in the figure, the horizontal axis is the time axis and the vertical axis is the power axis, and a single square wave represents a single laser pulse 3, unlike a conventional pulse laser. In the pulse group modulation mode, a pulse group contains a plurality of single laser pulses 3, and the interval time of each single laser pulse 3 is much shorter than that of a common pulse laser. The energy of each pulse, and the interval between pulses, can also be set as desired.
As shown in fig. 3, the energy at the early stage is large, the energy at the later stage is gradually reduced, the laser pulse with large energy is used for laser ablation, and the laser pulse with small energy is used for fine ablation.
EXAMPLE III
The semiconductor lithography method of the present embodiment is different from the first embodiment in that in step S02, the SiO in the film breaking region is pulsed by the laser2The film 2 is first cut with deep grooves 21 and then the whole SiO2The film 2 is subjected to a chemical etching process to form SiO2The thickness of the film 2 decreases as a whole to the SiO at the bottom of the deep trench 212The film 2 is removed and reaches the surface of the silicon chip 1;
in this embodiment, for the etching process, a buffered oxide etching agent, such as a mixture of hydrofluoric acid and ammonium fluoride, may be used in combination with a laser to complete the process.
For example, assuming that the thickness of the actual oxide film is 600nm, the resolution of the laser in the removal depth direction is 400nm, and the silicon wafer is not allowed to sink to the bottom (i.e. the silicon wafer 1 at the bottom of the deep trench 21 is not damaged); in operation, the laser pulse is firstly used for SiO in the film breaking area2The film 2 is first cut with a 400nm deep trench 21 and then SiO2The film 2 is subjected to a chemical etching process using a buffered oxide etchant formulation to remove SiO2The thickness of the film 2 is more than 200nm, and the deep groove 21 is exposed from the bottom silicon wafer 1, so that the SiO of the pulse laser at the film breaking area can be prevented from being taken out2After the film 2, the pulse laser damages the silicon chip 1, now a two-step mode is adopted, the first step of laser pulse film breaking is adopted, but the bottom is not broken, and then the second step is adopted to remove the residual SiO at the bottom of the deep groove 21 by using a chemical etching process2，Until the silicon chip 1 is exposed, if the laser pulse is directly acted on the silicon chip 1, the silicon chip 1 can be damaged, and the chemical etching process can not damage the silicon chip 1.
Example four
Based on the third embodiment, on the basis of the third embodiment, the deep trench 21 after the first-step laser pulse is subjected to texture processing, specifically, the surface of the oxide film is subjected to surface processing by using laser, and the texture processing is performed, so that the roughness of the bottom surface of the deep trench 21 is improved. SiO in the bottom of the deep trench 212When the film 2 is chemically etched by soaking in a buffered oxide etchant after being textured, the SiO at the bottom of the deep trench 212The contact area of the film 2 is increased, thereby increasing the etching speed of the bottom of the deep groove 21, and the purpose of chemical etching selectivity is achieved by a physical structure method of texture processing.
The semiconductor photoetching method of the invention replaces part of photoetching process, and can not need photoresist, photoetching plate, exposure and development, etching and photoresist removal processes, thereby simplifying the chip manufacturing process, reducing the cost, and being more environment-friendly and convenient.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (4)
1. A semiconductor lithography method, comprising
Step S01, preparing SiO on the silicon chip2Film of SiO2The uniformity of the film thickness is controlled within 10 percent;
step S02, in SiO2Selecting a membrane breaking area on the membrane;
SiO in the film-breaking zone by laser pulses2The film is first cut into deep grooves and then the whole SiO2The film is subjected to a chemical etching process to form SiO2The film thickness is reduced to SiO at the bottom of the deep groove2Film is removedRemoving to reach the surface of the silicon wafer;
step S03, obtaining SiO on the silicon wafer2The pattern of the film.
2. The semiconductor lithography method according to claim 1,
in step S02, SiO2The film is etched to SiO on the bottom of the deep trench before chemical etching2The film is textured to improve the roughness of the bottom surface of the deep groove.
3. The semiconductor lithography method according to claim 1,
the laser emits a pulse laser string group, the single pulse form of the pulse laser string group can be modulated, namely the time and the intensity of a single pulse can be controlled by programming, the number of pulses of each string of pulses can be set, and the relative intensity can be set;
wherein, the interval between the pulses of the pulse laser string group is less than or equal to 1000 ns.
4. The semiconductor lithography method according to claim 1,
the laser adopts
Nanosecond green laser with wavelength of 532nm and single pulse width of 1-100 ns, or
Nanosecond UV laser with wavelength of 355nm and single pulse width of 1-100 ns, or
Picosecond green laser with wavelength of 532nm and single pulse width of 3-50 ps, or
Picosecond ultraviolet laser with wavelength of 355nm and single pulse width of 3-50 ps, or
An infrared femtosecond laser with wavelength of 1064nm and single pulse width of 3-50 ps, or
A green femtosecond laser with a wavelength of 532nm and a single pulse width of 100fs-900fs, or
An ultraviolet femtosecond laser with a wavelength of 355nm and a single pulse width of 100fs-900fs, or
The wavelength of the deep ultraviolet femtosecond laser is less than or equal to 266nm, and the single pulse width is 100fs-900 fs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210571637.0A CN114664654A (en) | 2022-05-25 | 2022-05-25 | Semiconductor photoetching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210571637.0A CN114664654A (en) | 2022-05-25 | 2022-05-25 | Semiconductor photoetching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114664654A true CN114664654A (en) | 2022-06-24 |
Family
ID=82038401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210571637.0A Pending CN114664654A (en) | 2022-05-25 | 2022-05-25 | Semiconductor photoetching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114664654A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013069978A (en) * | 2011-09-26 | 2013-04-18 | Dainippon Screen Mfg Co Ltd | Method and apparatus for processing substrate |
| CN103928567A (en) * | 2013-01-16 | 2014-07-16 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
| CN104364916A (en) * | 2012-06-01 | 2015-02-18 | 皇家飞利浦有限公司 | Improved light extraction using feature size and shape control in led surface roughening |
-
2022
- 2022-05-25 CN CN202210571637.0A patent/CN114664654A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013069978A (en) * | 2011-09-26 | 2013-04-18 | Dainippon Screen Mfg Co Ltd | Method and apparatus for processing substrate |
| CN104364916A (en) * | 2012-06-01 | 2015-02-18 | 皇家飞利浦有限公司 | Improved light extraction using feature size and shape control in led surface roughening |
| CN103928567A (en) * | 2013-01-16 | 2014-07-16 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI447794B (en) | Laser processing of workpieces containing low-k dielectric material | |
| TWI494983B (en) | Wafer dicing using hybrid multi-step laser scribing process with plasma etch | |
| US6214703B1 (en) | Method to increase wafer utility by implementing deep trench in scribe line | |
| TWI605508B (en) | Method and apparatus for dicing wafers having thick passivation polymer layer | |
| TWI644350B (en) | Wafer dicing with wide kerf by laser scribing and plasma etching hybrid approach | |
| JP6109159B2 (en) | Wafer dicing using multi-pulse burst pulse train laser and plasma etching | |
| KR101552607B1 (en) | Wafer dicing using hybrid split-beam laser scribing process with plasma etch | |
| CN110998826B (en) | Particle contamination mitigation during wafer dicing | |
| JP6527517B6 (en) | Method for dicing wafer and carrier therefor | |
| TW201304067A (en) | Wafer dicing using hybrid galvanic laser scribing process with plasma etch | |
| KR20200098733A (en) | Mask residue removal for substrate dicing by laser and plasma etch | |
| WO2014011373A1 (en) | Uniform masking for wafer dicing using laser and plasma etch | |
| TWI735406B (en) | Alternating masking and laser scribing approach for wafer dicing using laser scribing and plasma etch | |
| KR102476266B1 (en) | A hybrid wafer dicing approach using a multi-pass laser scribing process and a plasma etching process | |
| TW201517171A (en) | Maskless hybrid laser scribing and plasma etching wafer dicing process | |
| JP7470104B2 (en) | Wafer dicing using a hybrid laser scribing and plasma etching technique with intermediate breakthrough processing | |
| TW201545235A (en) | Baking tool for improved wafer coating process | |
| CN114664654A (en) | Semiconductor photoetching method | |
| US20220246476A1 (en) | Hybrid wafer dicing approach using an actively-focused laser beam laser scribing process and plasma etch process | |
| KR20080054995A (en) | Marking method for semiconductor wafer | |
| KR20050115404A (en) | Method of manufacturing an isolation in semiconductor device | |
| TW201508865A (en) | Method of coating water soluble mask for laser scribing and plasma etch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220624 |
|
| RJ01 | Rejection of invention patent application after publication |