CN114640351A

CN114640351A - Decoding circuit, TDC circuit, data processing chip, optical system, and decoding method

Info

Publication number: CN114640351A
Application number: CN202011487169.6A
Authority: CN
Inventors: 姚廷宇; 王陈銮; 向少卿
Original assignee: Hesai Technology Co Ltd
Current assignee: Hesai Technology Co Ltd
Priority date: 2020-12-16
Filing date: 2020-12-16
Publication date: 2022-06-17

Abstract

A decoding circuit, comprising: the code bit generating unit is suitable for generating a group of logic codes according to a group of phase logic values, wherein each two phase logic values correspond to one logic code, and the logic codes corresponding to the two phase logic values meeting the preset requirement are different from other logic codes in the group of logic codes and are used for marking phase signals at the abrupt change edges in the group of phases; the two phase logic values characterize the phases of a pair of multiphase clock signals at the sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and the first multi-phase clock signals; and the decoding unit is suitable for obtaining a first code according to the group of logic codes.

Description

Decoding circuit, TDC circuit, data processing chip, optical system, and decoding method

Technical Field

The invention relates to the field of electricity, in particular to a decoding circuit, a TDC circuit, a data processing chip, an optical system and a decoding method.

Background

A Time To Digital Converter (TDC) is a device dedicated to Time interval quantization, and is a major approach for implementing a Time interval measurement technique at present. The analog TDC is mainly used for time amplification by utilizing charge and discharge of a capacitor and is represented by a voltage signal; the digital TDC quantizes the output directly in the digital domain using a delay unit. Compared with an analog TDC design, the digital TDC based on the programmable logic circuit and the digital signal processing has incomparable advantages in the aspects of design flexibility, stability, high integration degree, low cost and the like. With the development of integrated circuits, TDCs are gradually focusing on Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs).

At present, TDC chips are mostly designed by adopting CMOS technology, and the circuit structure mainly utilizes various delay lines formed by internal CMOS gate circuits to realize digital quantization of TDC, such as common structures of tap delay chains, differential delay chains, multi-phase clock sampling, pulse contraction and the like. The multi-phase clock sampling is to convert the direct counting method of a single reference clock into the method of using a plurality of fixed phase-shifted clocks, and to equalize different time regions at fixed intervals. In a TDC based on multiphase (multiple phase) sampling, it is necessary to convert multiphase information obtained by sampling into quantized information of time by a decoder. The existing TDC often has the problem of inaccurate quantization time.

Disclosure of Invention

The invention solves the problem that the sampling of the multi-phase clock is easy to cause inaccurate quantization time.

To solve the above problem, the present invention provides a decoding circuit, comprising: the code bit generating unit is suitable for generating a group of logic codes according to a group of phase logic values, wherein each two phase logic values correspond to one logic code, and the logic codes corresponding to the two phase logic values meeting the preset requirement are different from other logic codes in the group of logic codes and are used for marking phase signals at the abrupt change edges in the group of phases; the two phase logic values characterize the phases of a pair of multiphase clock signals at the sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and the first multi-phase clock signals; and the decoding unit is suitable for obtaining a first code according to the group of logic codes.

Optionally, the phase logic value is 0 or 1, the phase logic value is 0 to represent that the phase is 0, and the phase logic value is 1 to represent that the phase is pi.

Optionally, when the two phase logic values meeting the predetermined requirement are phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the former multi-phase clock signal is 1, and the phase logic value corresponding to the latter multi-phase clock signal is 0; when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to the last and first multi-phase clock signals, the predetermined requirement comprises: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

Optionally, when the two phase logic values meeting the predetermined requirement are phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the former multi-phase clock signal is 0, and the phase logic value corresponding to the latter multi-phase clock signal is 1; when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to the last and first multi-phase clock signals, the predetermined requirement comprises: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

Optionally, the logic codes corresponding to the two phase logic values meeting the predetermined requirement are 1, and the other logic codes in the group of logic codes are 0; or, the logic codes corresponding to the two phase logic values meeting the predetermined requirement are 0, and the other logic codes in the group of logic codes are 1.

Optionally, the code bit generating unit includes: a plurality of sets of sub-generation units, the sub-generation units comprising: an inverter and a NAND gate; one input end of the NAND gate and the input end of the inverter are suitable for respectively inputting two phase logic values corresponding to a logic code, the output end of the inverter is connected with the other input end of the NAND gate, and the output end of the NAND gate is suitable for outputting the logic code.

Optionally, when the two phase logic values corresponding to the one-bit logic code are phase logic values corresponding to two adjacent multi-phase clock signals, one input end of the nand gate is adapted to input a phase logic value corresponding to a previous multi-phase clock signal, and an input end of the inverter is adapted to input a phase logic value corresponding to a subsequent multi-phase clock signal; when the two phase logic values corresponding to the one-bit logic code are the phase logic values corresponding to the last and the first multi-phase clock signals, one input end of the nand gate is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

Optionally, when the two phase logic values corresponding to the one-bit logic code are phase logic values corresponding to two adjacent multi-phase clock signals, the input end of the inverter is adapted to input a phase logic value corresponding to a previous multi-phase clock signal, and one input end of the nand gate is adapted to input a phase logic value corresponding to a subsequent multi-phase clock signal; when the two phase logic values corresponding to the one-bit logic code are the phase logic values corresponding to the last and the first multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and one input end of the nand gate is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

Optionally, the decoding unit is adapted to sequentially arrange the set of logical codes to obtain a set of unique codes, obtain binary codes corresponding to the set of unique codes according to the set of unique codes, and use the binary codes as the first codes.

Optionally, the decoding unit includes: a one-hot decoder; the input end of the one-hot decoder is suitable for inputting the group of logic codes, and the output end of the one-hot decoder is suitable for outputting the first codes.

The present invention also provides a TDC circuit, including: the decoding circuit and the phase sampling circuit are suitable for sampling the phases of the multi-phase clock signals at the sampling moment to generate a group of phase logic values; a processing circuit adapted to obtain a quantized fine time at least from the first encoding.

Optionally, the TDC circuit further includes: a clock signal generation unit adapted to generate the multi-phase clock signals; the clock signal generation unit includes: a plurality of delay units, the output ends of which are adapted to output the multi-phase clock signal; the output end of the previous delay unit is connected with the input end of the next delay unit, and the output end of the last delay unit is connected with the input end of the first delay unit.

Optionally, the TDC circuit further includes: the counting unit is suitable for calculating the number of the cycles of one multiphase clock signal before the sampling moment and outputting the cycles; the processing circuit is further adapted to obtain a quantized coarse time at least based on the number of cycles.

Optionally, the processing circuit is adapted to obtain the quantized coarse time according to a period time of the multi-phase clock signal and the number of cycles.

Optionally, the counting unit includes: a first counter adapted to count the number of periods of one multiphase clock signal cycle before said sampling instant; a second counter adapted to count the number of periods during which the further multiphase clock signal is cycled before said sampling instant; and the selection unit is suitable for selecting the counter which is not in the jump state from the first counter and the second counter, and taking the number of cycles counted by the counter as the output of the counting unit.

Optionally, the first counter and the second counter are both in a skip state when a sudden change edge of the multi-phase clock signal occurs; the selection unit includes: a judging unit adapted to determine which of the first counter or the second counter is not in a skip state according to the phase logic value.

Optionally, the determining unit is further adapted to output a flag bit, where the flag bit represents: the number of cycles counted by which of the first counter and the second counter is used as an output of the counting unit.

Optionally, the processing circuit is adapted to obtain quantized fine time based on the delay difference between the multi-phase clock signals and the first encoding.

The invention also provides a data processing chip, comprising: the above TDC circuit adapted to cooperate with one or more photodetectors.

The present invention also provides an optical system comprising: the TDC circuit described above, as well as a front-end circuit and at least one photoelectric conversion unit adapted to generate a first pulse in response to a laser pulse; the front-end circuit is suitable for generating a trigger signal according to the pulse signal, wherein the trigger signal comprises a trigger pulse, and the abrupt change edge of the trigger pulse corresponds to the abrupt change edge of the first pulse; the occurrence time of the abrupt change edge of the trigger signal corresponds to the sampling time of the multi-phase clock signal.

The invention also provides a decoding method, which comprises the following steps: generating a group of logic codes according to a group of phase logic values, wherein each two phase logic values correspond to one-bit logic code, and the logic codes corresponding to the two phase logic values meeting the preset requirement are different from other logic codes in the group of logic codes and are used for marking phase signals at the abrupt change edges in the group of phases; the two phase logic values characterize the phases of a pair of multiphase clock signals at the sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and the first multi-phase clock signals; a first code is obtained from the set of logical codes.

Optionally, the obtaining a first code according to the set of logical codes includes: and arranging the group of logic codes in sequence to obtain a group of one-hot codes, obtaining binary codes corresponding to the one-hot codes according to the group of one-hot codes, and taking the binary codes as the first codes.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the decoding circuit generates a group of logic codes according to a group of phase logic values, two phase logic values meeting the preset requirement generate specific logic codes different from other logic codes, which can represent which phase signal is at a rising edge or a falling edge, and a first code is generated based on the logic codes, so that the position of a sampling moment in time delay can be known, and then more accurate quantization fine time can be obtained, the quantization fine time has the quantization result deviation of at most 1 Least Significant Bit (LSB), and the method is not influenced by duty ratio, and the design complexity is reduced.

Drawings

FIG. 1 is a schematic diagram of a TDC circuit according to an embodiment of the present invention;

FIG. 2 is a waveform diagram of signals associated with a TDC circuit in accordance with an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a voltage controlled oscillator according to an embodiment of the present invention;

FIG. 4 is a waveform diagram of a multi-phase clock signal according to an embodiment of the present invention;

FIG. 5 is a block diagram of a decoding circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a decoding circuit according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of the connection between the photodetecting unit and the data processing chip according to the present invention;

fig. 8 is a schematic diagram of the structure of the optical system of the present invention.

Detailed Description

In order to find the cause of the inaccurate quantization time, the inventor has further studied the digital TDC based on multi-phase clock sampling:

a Single Photon Avalanche Diode (SPAD) is taken as a detector of the laser ranging system, and a digital TDC based on multi-phase clock sampling is used for time measurement. In the application of laser ranging, the scheme that a single SPAD device is used as a pixel brings obvious noise interference, noise factors such as dark counts and ambient light are difficult to distinguish from effective signals, and the relative application effect is poor. Therefore, a plurality of SPAD devices are usually used as one pixel, that is, a plurality of SPADs are connected in parallel to one TDC to acquire trigger information, and by certain condition judgment, noise filtering can be realized, effective signals can be acquired more accurately, and the dynamic range is improved. Meanwhile, a plurality of pixels are arranged in a certain array to form an area array SPAD detector, so that the photosensitive surface of the detector can be enlarged to increase the range of a detectable field of view.

In conjunction with fig. 1 and 2, 4 spads(s) are taken as an example to constitute one pixel (macro pixel). After the SPAD is triggered into an avalanche, a high level pulse is generated. The front-end circuit (detection front-end)11 generates a trigger signal TRG, each pulse width of which is about 1nS, from a high-level pulse generated after SPAD is triggered into avalanche. It is understood that if a plurality of SPADs are triggered within one pulse duration of the trigger signal TRG, the trigger signal TRG generates only one pulse.

For example, the front-end circuit 11 generates a first pulse of the trigger signal TRG in response to a first pulse of the SPAD1 signal generated after a first SPAD avalanche, a second pulse of the trigger signal TRG in response to a first pulse of the SPAD2 signal generated after a second SPAD avalanche, and a third pulse of the trigger signal TRG in response to a first pulse of the SPAD3 signal generated after a third SPAD avalanche. Since the rising edge of the first pulse in SPAD4 generated after the avalanche of the fourth SPAD occurs within the duration of the third pulse in trigger signal TRG, which is very short in interval with the rising edge of the first pulse in SPAD3, a new pulse is not additionally generated.

The front-end circuit 11 also outputs a photon number signal photon count. The photon number signal photon count indicates that several SPADs are triggered within one pulse duration of the trigger signal TRG. In fig. 2, Cnt ═ 1 indicates that 1 SPAD is triggered, and Cnt ═ 2 indicates that 2 SPADs are triggered.

The rising edge of the trigger signal TRG may trigger the phase sampler 12 to sample the phases of the multiphase clock signals ph and phb generated by the Voltage Controlled Oscillator (VCO)18, and at the same time trigger the count sampler 13 and the count sampler 14 to sample the outputs of the first counter and the second counter _ b.

As shown in fig. 3, the voltage controlled oscillator 18 may be a ring oscillator that provides multiple phases (multiple phases) for the TDC. The ring oscillator of the n-stage differential structure can output 2n phases. Taking 5 steps as an example, the voltage-controlled oscillator 18 includes 5 delay units. The first delay unit outputs a first multi-phase clock signal ph0 to be input into the second delay unit, the second multi-phase clock signal ph1 to the third delay unit after being delayed by the second delay unit, the third multi-phase clock signal ph2 to the fourth delay unit after being delayed by the third delay unit, the fourth multi-phase clock signal ph3 to the fifth delay unit after being delayed by the fourth delay unit, and the fifth multi-phase clock signal ph4 to the first delay unit after being delayed by the fifth delay unit.

The first delay unit delays the fifth multi-phase clock signal ph4 to output a sixth multi-phase clock signal phb0 to the second delay unit, delays the second delay unit to output a seventh multi-phase clock signal phb1 to the third delay unit, delays the third delay unit to output an eighth multi-phase clock signal phb2 to the fourth delay unit, delays the fourth delay unit to output a ninth multi-phase clock signal phb3 to the fifth delay unit, and delays the fifth delay unit to output a tenth multi-phase clock signal phb4 to the first delay unit. The first delay unit delays the tenth multi-phase clock signal phb4 to output the first multi-phase clock signal ph 0.

As can be seen from the above operation process, the first multi-phase clock signal ph0 returns to the first delay unit after 10 times of delay along the oscillator loop, and completes one cycle. The delay times of the multi-phase clock signal in one period is related to the number of delay units in the oscillator. The signal waveforms shown in fig. 4 can be obtained by detecting 10 multiphase clock signals output from 5 delay units along the oscillator loop.

The first counter inputs the first multi-phase clock signal ph0, and the first multi-phase clock signal ph0 triggers the first counter to jump once every period T. The count sampler 13 samples the position of the first counter on the rising edge of the trigger signal TRG, so as to obtain the first coarse time. For example, the first multi-phase clock signal ph0 goes through 5 cycles, triggering the first counter to jump 5 times, and the first coarse time is 5 × T.

If the sampling time falls into the jump edge of the first counter, it may not be possible to determine which position the sampling time is located, which is called a metastable state, and a sampling error may occur at this time. For this, a second counter _ b spaced from the first counter by a certain time may be provided. In this embodiment, the sixth multi-phase clock signal phb0 is input to the second counter _ b, and the sixth multi-phase clock signal phb0 triggers the second counter _ b to jump once every period T. The count sampler 14 samples the position of the second counter _ b at the rising edge of the trigger signal TRG, so that the second coarse time can be obtained. This is so that the first counter and the second counter _ b are not in the jump state at the same time.

The phase sampler 12 samples the phases of the 10 multiphase clock signals and the logic circuit 15 outputs a selection signal sel, which may characterize which of the first counter and the second counter _ b is not in the toggle state, depending on the phase sampling results of the 10 multiphase clock signals.

The selector 16 selects one of the first coarse time and the second coarse time as a final coarse time (i.e., an upper bit of the quantization time) based on the selection signal sel. At the same time, the logic circuit 15 also outputs a flag bit res indicating which of the first counter and the second counter _ b is used as the final coarse time. This avoids metastability errors for the coarse time calculation.

For the first multi-phase clock ph0 to the tenth multi-phase clock signal phb4, there is a delay difference Δ T in sequence. As described above, the first multiphase clock ph0 is considered to be sequentially transmitted at the delay time difference Δ T, and the time from the thinning to the resolution of the delay time difference Δ T can be determined from the position where the waveform is transmitted at the sampling time, and is referred to as the thinning time.

The two dashed lines in fig. 4 represent sampling of the phases of the multi-phase clock signal at time T0 and at time T0+ Δ T, respectively. After the delay time difference Δ T from time T0, the second multi-phase clock signal ph1 changes from the phase of 0 to pi (low level to high level), and the seventh multi-phase clock signal phb1 changes from the phase of pi to 0 (high level to low level).

With the delay difference Δ T as an interval, the phase sampler 12 samples the phases of the 10 multiphase clock signals 10 times to obtain phase logic values, and the phase logic values are sent to the decoder 17, so as to obtain the codes shown in table 1. The entries in the table corresponding to ph0-phb4 are phase logic values, one of which characterizes the phase of a multiphase clock signal at the sampling instant. A logical value of 0 for the phase indicates a phase of 0, and a logical value of 1 for the phase indicates a phase of π. From these phase logic values, the code and binary code bins shown in table 1 can be obtained.

TABLE 1

ph0	ph1	ph2	ph3	ph4	phb0	phb1	phb2	phb3	phb4	code	binary
													1	0	0	0	0	0	1	1	1	1	0	0000
1	1	0	0	0	0	0	1	1	1	1	0001
												1	1	1	0	0	0	0	0	1	1	2	0010
1	1	1	1	0	0	0	0	0	1	3	0011
												1	1	1	1	1	0	0	0	0	0	4	0100
0	1	1	1	1	1	0	0	0	0	5	0101
												0	0	1	1	1	1	1	0	0	0	6	0110
0	0	0	1	1	1	1	1	0	0	7	0111
												0	0	0	0	1	1	1	1	1	0	8	1000
0	0	0	0	0	1	1	1	1	1	9	1001

As can be seen from table 1, from the phases of the first multi-phase clock signal ph0 to the tenth multi-phase clock signal phb4, the position of the sampling instant in 10 time delays can be determined, i.e. the fine time of quantization (i.e. the lower bits of the quantization time) can be represented. The fine time precision obtained by this method can reach Δ T, i.e. the coarse time quantized by counter or counter _ b is refined to one tenth of a period. For example, the decoder output 0010 indicates that 2 × Δ T has passed.

As an asynchronously sampled TDC, if a transition occurs in the sampling of the multiphase clock signal and the sampling time falls on its transition edge (the rising edge and the falling edge in the waveform shown in fig. 4), metastable sampling occurs and the phase logic value output by the phase sampler 12 is inaccurate.

It can be seen from fig. 4 that each transition of the quantization time corresponds to a level transition of two phases. For example, at the time T0, among the first through tenth multi-phase clock signals ph0 through phb4, the first multi-phase clock signal ph0 is at a rising edge, and the sixth multi-phase clock signal phb0 is at a falling edge. That is, the first multi-phase clock signal ph0 and the sixth multi-phase clock signal phb0 are both in a toggle state. In this case, both the first multi-phase clock signal ph0 and the sixth multi-phase clock signal phb0 may be recognized incorrectly, so that the 2 phase logic values corresponding to ph0 and phb0 are incorrect.

When the decoder 17 generates the decoding result based on the 10 phase logic values ph0 to phb4, the quantization result will have an error of 2 LSBs because there are 2 erroneous phase logic values in the 10 phase logic values.

In order to reduce the quantization error, the present inventors have provided a new decoding circuit that controls the quantization error to be within 1 LSB. In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

It should be noted that, when the present embodiment relates to the above-mentioned contents that have been described in detail, the contents are directly referred to and are not described in detail again, and the contents of the same portion belong to the scope covered by the embodiments of the present application.

The inventor of the present application carefully studies the phase logic values of the multi-phase clock signals and the waveforms of the multi-phase clock signals, and finds that, in a refinement time (Δ T time), when the phase logic value corresponding to a certain multi-phase clock signal is 1 and the phase logic value of the following multi-phase clock signal is 0, it can be determined that the rising edge of the multi-phase clock signal is inverted.

Referring to table 2, when the phase logic value of a multi-phase clock signal is 1 and the phase logic values of the following multi-phase clock signals are 0, the combination of the phase logic values [ 10 ] appears in the table. From the phase logic value [ 10 ] combination, it can be determined which multi-phase clock signal has a rising edge inversion. In the result of one phase sampling, the phase logic value [ 10 ] combination occurs only once and is not affected by the phase logic value [ 01 ] combination caused by the falling edge.

TABLE 2

Based on the above analysis, the decoding circuit proposed by the inventor of the present application includes: code bit generation unit and decoding unit.

The code bit generating unit can generate a group of logic codes according to a group of phase logic values, wherein each two phase logic values correspond to one logic code, and the logic codes corresponding to the two phase logic values meeting the preset requirement are different from other logic codes in the group of logic codes; the two phase logic values characterize the phases of a pair of multiphase clock signals at the sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals. The decoding unit may obtain a first code from the set of logical codes.

The set of phase logic values is obtained by phase sampling a multi-phase clock signal within one period. The multi-phase clock signal is a clock signal generated by a ring oscillator composed of a plurality of delay units. The phase logic value is 0 or 1, the phase logic value is 0 to represent that the phase is 0, and the phase logic value is 1 to represent that the phase is pi.

Take the example where the multi-phase clock signals comprise a first multi-phase clock ph0 to a tenth multi-phase clock signal phb 4. The pair of multi-phase clock signals comprises: adjacent first and second multi-phase clocks ph0 and ph1, adjacent second and third multi-phase clocks ph1 and ph2, adjacent third and fourth multi-phase clocks ph2 and ph3, adjacent ninth and tenth multi-phase clocks phb3 and phb4 to … …, and tenth multi-phase clock phb4 (last multi-phase clock) and ph 0.

The phases of the first multi-phase clock ph0 to the tenth multi-phase clock signal phb4 are sampled 10 times at intervals of the delay difference Δ T, and the logical values of the phases corresponding to ph0-phb4 in table 3 can be obtained.

TABLE 3

The code bit generating unit generates a one-bit logic code according to the phase logic values corresponding to the pair of multiphase clock signals, and one group of phase logic values corresponds to one group of logic codes. The decoding unit generates a first code according to the set of logical codes.

The first code may be a one-hot code, and the decoding unit sequentially arranges the set of logical codes to obtain a set of one-hot codes, which is shown in a 1hot code item in table 3. The number of the multi-phase clock signals is the same as the number of the bits of the one-hot codes, the multi-phase clock signals correspond to the logic codes in the first codes one by one, each multi-phase clock signal corresponds to one logic code in the one-hot codes,

when two phase logic values meeting a predetermined requirement are phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is as follows: the previous multi-phase clock signal corresponds to a phase logic value of 1, and the subsequent multi-phase clock signal corresponds to a phase logic value of 0.

For example, in the first row of table 3, ph0 is 1 and ph1 is 0, which indicates that the first multi-phase clock signal ph0 has a phase logic value of 1, and the second multi-phase clock signal ph1 has a phase logic value of 0, then the code bit generating unit generates the first logic code of 1 and the other logic codes of 0 according to ph0 and ph 1. The one-hot code generated by the decoding unit according to these logical codes is 1000000000. Of course, in another embodiment, the logic code corresponding to the two phase logic values meeting the predetermined requirement may be set to 0, and the other logic code may be set to 1.

When the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to the last and first multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

For example, in the last row of table 3, phb4 is 1 and ph0 is 0, which indicates that the last multi-phase clock signal phb4 has a phase logic value of 1 and the first multi-phase clock signal ph0 has a phase logic value of 0, the code bit generation unit generates the last logic code of 1 and the other bits have logic codes of 0 according to phb4 and ph 0. The one-hot code generated by the decoding unit according to these logic codes is 0000000001.

The coding unit may include: a one-hot decoder; the input end of the one-hot decoder is suitable for inputting the group of logic codes, and the output end of the one-hot decoder is suitable for outputting the first codes.

In combination with the above analysis, the code bit generating unit of the present embodiment finds out the phase logic value corresponding to the combination of the phase logic values [ 10 ] through logic judgment, and generates a set of unique code according to the phase logic value corresponding to the combination. The position of a 1 in the one-hot code may indicate which multi-phase clock signal is undergoing a rising edge inversion, so that it is possible to know which multi-phase clock signal is sampled, i.e., the position of the sampling instant in the delay, and thus obtain a quantized fine time. For example, the code bit generation unit generates 0100000000 as the logic code, indicating that the second multiphase clock signal is rising edge flipping, so the thinning time is 2 × Δ T. The sampling position is identified according to the rising edge and is not influenced by the falling edge, so that the quantization result deviation of 1 LSB at most in quantization time is obtained, the influence of the duty ratio of the clock signal is avoided, and the design complexity is reduced.

Optionally, the first code may also be a binary code, and the decoding unit obtains a binary code corresponding to the one-hot code according to a set of unique codes, and uses the binary code as the first code.

Fig. 5 is a schematic diagram of a decoding circuit according to an embodiment of the present invention, which is used as the decoder 17 in fig. 1.

As shown in fig. 5, the code bit generation unit of the present embodiment may include: a plurality of sets of sub-generation units, the sub-generation units comprising: an inverter and a nand gate.

The first input end of the NAND gate and the input end of the inverter are suitable for respectively inputting two phase logic values corresponding to a logic code, the output end of the inverter is connected with the second input end of the NAND gate, and the output end of the NAND gate is suitable for outputting the logic code.

When the two phase logic values corresponding to the one-bit logic code are the phase logic values corresponding to the two adjacent multi-phase clock signals, the first input end of the nand gate is suitable for inputting the phase logic value corresponding to the previous multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the next multi-phase clock signal.

For example, the first input terminal of the nand gate in the first sub-generation unit inputs the first multi-phase clock signal ph0, and the input terminal of the inverter inputs the second multi-phase clock signal ph 1; the first input end of the NAND gate in the second sub-generation unit inputs a second multi-phase clock signal ph1, and the input end of the inverter inputs a third multi-phase clock signal ph 2; the first input end of the nand gate in the third sub-generation unit inputs a third multi-phase clock signal ph2, and the input end of the inverter inputs a fourth multi-phase clock signal ph 3; the first input end of the nand gate in the fourth sub-generation unit inputs the fourth multi-phase clock signal ph3, and the input end of the inverter inputs the fifth multi-phase clock signal ph 4; the first input end of the nand gate in the fifth sub-generation unit inputs the fifth multi-phase clock signal ph4, and the input end of the inverter inputs the sixth multi-phase clock signal phb 0; the first input end of the nand gate in the sixth sub-generation unit inputs the sixth multi-phase clock signal phb0, and the input end of the inverter inputs the seventh multi-phase clock signal phb 1; the seventh multiphase clock signal phb1 is input to the first input terminal of the nand gate in the seventh sub-generation unit, and the eighth multiphase clock signal phb2 is input to the input terminal of the inverter; the eighth multi-phase clock signal phb2 is input to the first input terminal of the nand gate in the eighth sub-generation unit, and the ninth multi-phase clock signal phb3 is input to the input terminal of the inverter; the first input of the nand-gate in the ninth sub-generation unit inputs the ninth multi-phase clock signal phb3, and the input of the inverter inputs the tenth multi-phase clock signal phb 4.

When the two phase logic values corresponding to the one-bit logic code are the last phase logic value corresponding to the first multi-phase clock signal, the first input end of the nand gate is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

For example, the first input terminal of the nand gate in the tenth sub-generation unit inputs the tenth multi-phase clock signal ph4, and the input terminal of the inverter inputs the first multi-phase clock signal ph 0.

As can be seen from the circuit configuration of fig. 5, the nand gate outputs a low level (logic value 0) only when the first input terminal of the nand gate inputs a high level (logic value 1) and the input terminal of the inverter inputs a low level (logic value 0); otherwise, the nand gates each output a high level (logic value 1). The decoding unit may include an inverter for inverting the output of the nand gate and then sequencing the inverted output to obtain a set of unique codes.

Referring to table 4, when the phase logic value of a multi-phase clock signal is 0 and the phase logic values of the following multi-phase clock signals are 1, the combination of the phase logic values [ 01 ] appears in the table. According to the phase logic value [ 01 ] combination, which multi-phase clock signal has falling edge inversion can be judged. In the result of one phase sampling, the phase logic value [ 01 ] combination occurs only once and is not affected by the phase logic value [ 10 ] combination caused by the rising edge.

TABLE 4

Based on the above analysis, the present embodiment can also perform decoding according to the falling edge. Specifically, when two phase logic values meeting the predetermined requirement are phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is as follows: the previous multi-phase clock signal corresponds to a phase logic value of 0, and the subsequent multi-phase clock signal corresponds to a phase logic value of 1.

For example, in the first row of table 4, phb0 is 0 and phb1 is 1, indicating that the sixth multi-phase clock signal phb0 corresponds to a phase logic value of 0, and the seventh multi-phase clock signal phb1 corresponds to a phase logic value of 1, the code bit generating unit generates the sixth logic code of 1 and the other bits of 0 according to phb0 and phb 1. The one-hot code generated by the decoding unit based on these logical codes is 0000010000. Of course, in another embodiment, the logic code corresponding to the two phase logic values meeting the predetermined requirement may be set to 0, and the other logic code may be set to 1.

For example, in the last row of table 4, ph4 is 0 and phb0 is 1, which indicates that the last multi-phase clock signal ph4 has a phase logic value of 0 and the first multi-phase clock signal phb0 has a phase logic value of 1, then the code bit generating unit generates a fifth bit logic code of 1 and the other bits have a logic code of 0 according to ph4 and phb 0. The one-hot code generated by the decoding unit based on these logical codes is 0000100000.

The code bit generating unit finds out the phase logic value according with the phase logic value [ 01 ] combination through logic judgment, and generates a group of one-hot codes according to the phase logic value according with the combination. The position of a 1 in the one-hot code may indicate which multi-phase clock signal is falling edge-flipped, so that it is possible to know which multi-phase clock signal is sampled, i.e. the position of the sampling instant in the delay, so that a quantized fine time can be obtained. For example, the code bit generating unit generates 0000001000 logic code, which indicates that the second multiphase clock signal is rising edge flipping, so the thinning time is 2 × Δ T. The sampling position is identified according to the falling edge and is not influenced by the rising edge, so that the quantization result deviation of 1 LSB at most in quantization time is obtained, the influence of the duty ratio is avoided, and the design complexity is reduced.

Fig. 6 is a schematic diagram of a decoding circuit according to another embodiment of the present invention, which is used as the decoder 17 in fig. 1.

As shown in fig. 6, in the code bit generating unit, when the two phase logic values corresponding to one bit of logic code are the phase logic values corresponding to two adjacent multiphase clock signals, the input end of the inverter is adapted to input the phase logic value corresponding to the previous multiphase clock signal, and the second input end of the nand gate is adapted to input the phase logic value corresponding to the next multiphase clock signal.

For example, the input terminal of the inverter inputs the first multi-phase clock signal ph0, and the second input terminal of the nand gate in the first sub-generation unit inputs the second multi-phase clock signal ph 1; the input end of the inverter inputs a second multiphase clock signal ph1, and the second input end of the nand gate in the second sub-generation unit inputs a third multiphase clock signal ph 2; the input end of the inverter inputs a third multi-phase clock signal ph2, and the second input end of the nand gate in the third sub-generation unit inputs a fourth multi-phase clock signal ph 3; the input end of the inverter inputs a fourth multi-phase clock signal ph3, and the second input end of the nand gate in the fourth sub-generation unit inputs a fifth multi-phase clock signal ph 4; the input end of the inverter inputs a fifth multi-phase clock signal ph4, and the second input end of the nand gate in the fifth sub-generation unit inputs a sixth multi-phase clock signal phb 0; the input end of the inverter inputs a sixth multi-phase clock signal phb0, and the second input end of the nand gate in the sixth sub-generation unit inputs a seventh multi-phase clock signal phb 1; the input end of the inverter inputs a seventh multiphase clock signal phb1, and the second input end of the nand gate in the seventh sub-generation unit inputs an eighth multiphase clock signal phb 2; the input end of the inverter inputs an eighth multi-phase clock signal phb2, and the second input end of the nand gate in the eighth sub-generation unit inputs a ninth multi-phase clock signal phb 3; the input of the inverter inputs the ninth multi-phase clock signal phb3, and the second input of the nand-gate in the ninth sub-generation unit inputs the tenth multi-phase clock signal phb 4.

When the two phase logic values corresponding to the one-bit logic code are the phase logic values corresponding to the last and the first multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the second input end of the nand gate is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

For example, the input terminal of the inverter inputs the tenth multi-phase clock signal ph4, and the second input terminal of the nand gate in the tenth sub-generation unit inputs the first multi-phase clock signal ph 0.

As can be seen from the circuit configuration of fig. 6, the nand gate outputs a low level (logic value 0) only when the input terminal of the inverter inputs a low level (logic value 0) and the second input terminal of the nand gate inputs a high level (logic value 1); otherwise, the nand gates each output a high level (logic value 1). The decoding unit may include an inverter for inverting the output of the nand gate and then sequencing the inverted output to obtain a set of unique codes.

With continued reference to fig. 1, the present invention further provides a TDC circuit, which includes the decoding circuit of the above embodiment, and a phase sampling circuit and a processing circuit (not shown in the figure).

The phase sampling circuit is adapted to sample the phases of the multi-phase clock signal at sampling instants to generate a set of phase logic values. The processing circuit is adapted to obtain a quantized fine time at least from the first encoding. The phase sampling circuit may be implemented by the phase sampler 12.

In particular, the processing circuit obtains a quantized fine time from the delay difference between the multiphase clock signals and said first encoding. As analyzed above, it is known from the first code which multiphase clock signal is rising or falling edge flipping, whereby a quantized fine time can be obtained. For example, the processing circuit obtains a quantized refinement time of 2 × Δ T from the first encoding 0000001000.

The TDC circuit described in this embodiment further includes: a clock signal generation unit adapted to generate the multi-phase clock signal. The clock signal generation unit includes: a plurality of delay units, the output ends of which are adapted to output the multi-phase clock signal; the output end of the previous delay unit is connected with the input end of the next delay unit, and the output end of the last delay unit is connected with the input end of the first delay unit. The clock signal generation unit may be implemented by a voltage controlled oscillator 18.

The TDC circuit further includes: and the counting unit is suitable for calculating the number of the cycles of one multi-phase clock signal before the sampling moment and outputting the number. The processing circuit is further adapted to obtain a quantized coarse time at least based on the number of cycles. In particular, the processing circuit obtains the quantized coarse time from a period time of the multi-phase clock signal and a number of periods of the cycle.

The counting unit may include: the device comprises a first counter, a second counter and a selection unit. The first counter is adapted to count the number of periods of one multiphase clock signal cycle before said sampling instant. The second counter is adapted to count the number of periods of the further multiphase clock signal cycle before said sampling instant. The selection unit is adapted to select a counter not in the jump state from among the first counter and the second counter, and to use the number of cycles counted by the counter as an output of the counting unit.

The first counter and the second counter are both in a jump state when a sudden change edge of the multi-phase clock signal occurs; the selection unit includes: a judging unit adapted to determine which of the first counter or the second counter is not in a jump state according to the phase logic value. The judgment unit is further adapted to output a flag bit, and the flag bit represents: the number of cycles counted by which of the first counter and the second counter is used as an output of the counting unit.

The first counter may be implemented by a first counter and a count sampler 13, and the second counter may be implemented by a second counter _ b and a count sampler 14. The determination unit may be implemented by a logic circuit 15. The function of the selection unit to select the output value is partly implemented by the selector 16. Reference is made to the preceding description as to the manner of calculating the number of cycles and the manner of calculating the quantized coarse time.

In the design of the TDC circuit with high throughput, the delay of the decoding circuit becomes one of the important factors for limiting the TDC throughput, and it can be seen from the above description that the decoding circuit provided in the embodiment of the present invention is a simple and parallel topology structure, which greatly reduces the delay of the decoding circuit and can effectively improve the TDC throughput compared with the prior art that increases the complexity of design and decoding logic.

As shown in fig. 7, an embodiment of the present invention further provides a data processing chip, which includes the TDC circuit of the above embodiment, where the TDC circuit is adapted to cooperate with one or more photodetectors.

The photodetector may comprise a SPAD array. The SPAD array comprises a plurality of rows and a plurality of columns, each row and each column are respectively provided with a plurality of photoelectric conversion units, and each photoelectric conversion unit comprises one or more SPADs. When one photoelectric conversion unit includes a plurality of SPADs, the plurality of SPADs may be connected to the same TDC circuit to be used as one pixel. In the application of ToF measurement, a signal reading circuit comprises a TDC, and the TDC outputs SPAD triggering time and the number of SPADs triggered simultaneously in the same time to a synchronous circuit for generating a histogram and judging subsequent ToF time.

For example, each photodetecting unit 1000 includes four SPADs, namely SPAD1001A, SPAD1001B, SPAD1001C, and SPAD 1001D. The outputs of all SPADs are coupled to the same TDC.

As shown in fig. 8, the embodiment of the present invention further provides an optical system 110 including: a light emitting module 111, a light detecting module 112 and a control module 113. The optical transmission module 111 refers to a part (which may include circuits, devices, structures, etc.) for laser transmission in the optical detection system; the optical detection module 112 refers to a portion (which may include circuits, devices, structures, etc.) of the optical detection system for detecting the echo signal of the laser.

The light Emitting module 111 includes a light Emitting array 1111, for example, implemented by a Vertical-Cavity Surface-Emitting Laser (VCSEL) array. The light emitting array 1111 includes a plurality of rows and a plurality of columns. Wherein, each row and each column are respectively provided with a plurality of light emitting units 11111, and each light emitting unit 11111 comprises at least one light emitter; the light emitting array 1111 is further configured with a light emitting array driving circuit, coupled to each light emitter, for driving the light emitter to operate.

The light detection module 112 includes: the optical electrical detection array 1121 may be, for example, the optical electrical detection array of fig. 7, and is configured to receive an optical echo signal after the detection beam reaches the target 114. In addition, the optical detection module 112 may further include a signal readout circuit (not shown) for reading out and transmitting the signal generated by the optical detection array 1121 to the control module 113.

In the optical detection system, an emission lens set 1114 can be further arranged and is positioned on the emergent light path of the light emission array 1111; in the optical detection system, a receiving lens group 1122 may be further provided, and the photodetection array 1121 may be located on a focal plane of the receiving lens group 1122.

The control module 113 is coupled to the light emitting array 1111 and the photodetection array 1121; the light emitting arrays are respectively controlled to emit detection light beams according to a certain sequence and power, and the corresponding light detection arrays receive echo signals.

The optical detection module 112 further includes a data processing chip 1123 and a front-end circuit (not shown), and the data processing chip 1123 includes the TDC circuit of the above-described embodiment. The data processing chip of the embodiment of the present invention may be the data processing chip shown in fig. 7. The front-end circuit is suitable for generating a trigger signal according to the pulse signal, wherein the trigger signal comprises a trigger pulse, and the abrupt change edge of the trigger pulse corresponds to the abrupt change edge of the first pulse. The occurrence time of the abrupt change edge of the trigger signal corresponds to the sampling time of the multi-phase clock signal.

The embodiment of the invention also provides a decoding method, which comprises the following steps: generating a group of logic codes according to a group of phase logic values, wherein each two phase logic values correspond to one-bit logic code, and the logic codes corresponding to the two phase logic values meeting the preset requirement are different from other logic codes in the group of logic codes and are used for marking phase signals at the abrupt change edges in the group of phases; the two phase logic values characterize the phases of a pair of multiphase clock signals at the sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and the first multi-phase clock signals; a first code is obtained from the set of logical codes.

Optionally, when the two phase logic values meeting the predetermined requirement are phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the former multi-phase clock signal is 0, and the phase logic value corresponding to the latter multi-phase clock signal is 1; when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to the last and the first multi-phase clock signals, the predetermined requirement comprises: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A decoding circuit, comprising:

a code bit generation unit adapted to generate a set of logical codes based on the set of phase logical values,

the logic codes corresponding to the two phase logic values meeting the preset requirement are different from other logic codes in the group of logic codes, and are used for marking the phase signals at the abrupt change edges in the group of phases; the two phase logic values characterize the phases of a pair of multiphase clock signals at the sampling moment; the pair of multiphase clock signals are two adjacent multiphase clock signals, or the last and the first multiphase clock signals;

and the decoding unit is suitable for obtaining a first code according to the group of logic codes.

2. The decoding circuit of claim 1, wherein the phase logic value is 0 or 1, a phase logic value of 0 being indicative of a phase of 0, and a phase logic value of 1 being indicative of a phase of π.

3. The decoding circuit of claim 2, wherein when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the former multi-phase clock signal is 1, and the phase logic value corresponding to the latter multi-phase clock signal is 0;

when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to the last and first multi-phase clock signals, the predetermined requirement comprises: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

4. The decoding circuit of claim 2, wherein when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the former multi-phase clock signal is 0, and the phase logic value corresponding to the latter multi-phase clock signal is 1;

when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to the last and first multi-phase clock signals, the predetermined requirement comprises: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

5. The decoding circuit according to any of claims 1-4, wherein the logic codes corresponding to the two phase logic values meeting the predetermined requirement are 1, and the other logic codes in the set of logic codes are 0; or, the logic codes corresponding to the two phase logic values meeting the predetermined requirement are 0, and the other logic codes in the group of logic codes are 1.

6. The decoding circuit of claim 1, wherein the code bit generation unit comprises: a plurality of sets of sub-generation units, the sub-generation units comprising: an inverter and a NAND gate;

one input end of the NAND gate and the input end of the inverter are suitable for respectively inputting two phase logic values corresponding to a logic code, the output end of the inverter is connected with the other input end of the NAND gate, and the output end of the NAND gate is suitable for outputting the logic code.

7. The decoding circuit as claimed in claim 6, wherein when the two phase logic values corresponding to one-bit logic code are the phase logic values corresponding to two adjacent multi-phase clock signals, one input terminal of the nand gate is adapted to input the phase logic value corresponding to the previous multi-phase clock signal, and the input terminal of the inverter is adapted to input the phase logic value corresponding to the next multi-phase clock signal;

when the two phase logic values corresponding to the one-bit logic code are the phase logic values corresponding to the last and the first multi-phase clock signals, one input end of the nand gate is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

8. The decoding circuit of claim 6, wherein when the two phase logic values corresponding to one-bit logic code are the phase logic values corresponding to two adjacent multi-phase clock signals, the input terminal of the inverter is adapted to input the phase logic value corresponding to the previous multi-phase clock signal, and the input terminal of the nand gate is adapted to input the phase logic value corresponding to the next multi-phase clock signal;

when the two phase logic values corresponding to the one-bit logic code are the phase logic values corresponding to the last and the first multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and one input end of the nand gate is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

9. The decoding circuit according to claim 1, wherein the decoding unit is adapted to sequentially arrange the set of logical codes to obtain a set of unique codes, and obtain a binary code corresponding to the set of unique codes according to the set of unique codes, and use the binary code as the first code.

10. The decoding circuit of claim 1, wherein the decoding unit comprises: a one-hot decoder;

the input end of the one-hot decoder is suitable for inputting the group of logic codes, and the output end of the one-hot decoder is suitable for outputting the first codes.

11. A TDC circuit, comprising: the decoding circuit of any of claims 1-10, and

a phase sampling circuit adapted to sample phases of the multi-phase clock signal at sampling instants to generate a set of phase logic values;

a processing circuit adapted to obtain a quantized fine time at least from the first encoding.

12. The TDC circuit according to claim 11, further comprising: a clock signal generation unit adapted to generate the multi-phase clock signals; the clock signal generation unit includes: a plurality of delay units, the output ends of which are adapted to output the multi-phase clock signal;

the output end of the previous delay unit is connected with the input end of the next delay unit, and the output end of the last delay unit is connected with the input end of the first delay unit.

13. The TDC circuit according to claim 11, further comprising:

the counting unit is suitable for calculating the number of the cycles of one multiphase clock signal before the sampling moment and outputting the cycles;

the processing circuit is further adapted to obtain a quantized coarse time at least based on the number of cycles.

14. The TDC circuit according to claim 13, wherein said processing circuit is adapted to obtain said quantized coarse time from a period time of the multi-phase clock signal and a number of periods of said cycles.

15. The TDC circuit according to claim 13, wherein the counting unit includes:

a first counter adapted to count the number of periods of one multiphase clock signal cycle before said sampling instant;

a second counter adapted to count the number of periods of another multiphase clock signal cycle before said sampling instant;

and the selection unit is suitable for selecting the counter which is not in the jump state from the first counter and the second counter, and taking the number of cycles counted by the counter as the output of the counting unit.

16. The TDC circuit as claimed in claim 15, wherein said first and second counters are both in a toggle state when a sudden change edge of the multi-phase clock signal occurs; the selection unit includes:

a judging unit adapted to determine which of the first counter or the second counter is not in a jump state according to the phase logic value.

17. The TDC circuit according to claim 16, wherein said decision unit is further adapted to output a flag bit characterizing: the number of cycles counted by which of the first counter and the second counter is used as an output of the counting unit.

18. The TDC circuit according to claim 11, wherein said processing circuit is adapted to obtain a quantized fine time from the delay difference between said multi-phase clock signals and said first encoding.

19. A data processing chip, comprising:

the TDC circuit of any one of claims 11 to 18, adapted to cooperate with one or more photodetectors.

20. An optical system, comprising: the TDC circuit as claimed in any one of claims 11 to 18, and a front-end circuit and at least one photoelectric conversion unit,

the photoelectric conversion unit is suitable for responding to laser pulses to generate first pulses;

the front-end circuit is suitable for generating a trigger signal according to the pulse signal, wherein the trigger signal comprises a trigger pulse, and the abrupt change edge of the trigger pulse corresponds to the abrupt change edge of the first pulse;

the occurrence time of the abrupt change edge of the trigger signal corresponds to the sampling time of the multi-phase clock signal.

21. A decoding method, comprising:

generating a group of logic codes according to a group of phase logic values, wherein each two phase logic values correspond to one-bit logic code, and the logic codes corresponding to the two phase logic values meeting the preset requirement are different from other logic codes in the group of logic codes and are used for marking phase signals at the abrupt change edges in the group of phases; the two phase logic values characterize the phases of a pair of multiphase clock signals at the sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and the first multi-phase clock signals;

a first code is obtained from the set of logical codes.

22. The decoding method of claim 21, wherein the phase logic value is 0 or 1, a phase logic value of 0 indicates a phase of 0, and a phase logic value of 1 indicates a phase of pi.

23. The decoding method of claim 22, wherein when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the former multi-phase clock signal is 1, and the phase logic value corresponding to the latter multi-phase clock signal is 0;

24. The decoding method of claim 22, wherein when the two phase logic values meeting the predetermined requirement are the phase logic values corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the former multi-phase clock signal is 0, and the phase logic value corresponding to the latter multi-phase clock signal is 1;

25. The decoding method according to any of claims 21-24, wherein the two phase logic values meeting the predetermined requirement correspond to a logic code of 1, and the other logic codes in the set of logic codes are 0; or, the logic codes corresponding to the two phase logic values meeting the predetermined requirement are 0, and the other logic codes in the group of logic codes are 1.

26. The decoding method of claim 21, wherein said obtaining a first code from said set of logical codes comprises:

and arranging the group of logic codes in sequence to obtain a group of one-hot codes, obtaining binary codes corresponding to the one-hot codes according to the group of one-hot codes, and taking the binary codes as the first codes.