CN110491945A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN110491945A CN110491945A CN201910743007.5A CN201910743007A CN110491945A CN 110491945 A CN110491945 A CN 110491945A CN 201910743007 A CN201910743007 A CN 201910743007A CN 110491945 A CN110491945 A CN 110491945A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000926 separation method Methods 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- -1 LDD ion Chemical class 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
This application discloses a kind of semiconductor devices and its manufacturing methods, belong to technical field of semiconductors.The semiconductor devices successively includes bottom, separation layer and graph layer along the thickness direction of semiconductor devices；Graph layer includes top level structure, the first n-type region, first grid, second grid, p-type trap, N-type drift region domain and the second n-type region；Along the width direction of semiconductor devices, first grid and second grid are oppositely arranged, and the first n-type region, p-type trap, N-type drift region domain and the second n-type region are between first grid and second grid；First n-type region, p-type trap, N-type drift region domain and the second n-type region are set gradually along the length direction of semiconductor devices.The application crosses all and first grid and second grid is set side by side, and reduces the threshold voltage of semiconductor devices；Meanwhile the anticreeping power of semiconductor devices is increased by the way that separation layer is arranged.
Description
Technical field
This application involves technical field of semiconductors, and in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
In semiconductor integrated circuit, the circuit based on bilateral diffusion field-effect tranisistor is known as dual diffusion metal oxygen
Compound semiconductor (Double-diffused Metal Oxide Semiconductor, DMOS) utilizes two kinds of foreign atoms
Sideways diffusion speed difference forms self aligned submicrometer channel, can achieve higher working frequency and speed.
In the related technology, DMOS device is usually provided with N-type drift region domain (N Drift) to increase the work of semiconductor devices
Make voltage (VDD), however as VDDIncrease, cause the electrical leakage problems of DMOS device, while also leading to the threshold of DMOS device
Threshold voltage (Vt) higher.
Summary of the invention
The embodiment of the present application provides a kind of semiconductor devices and its manufacturing method, can solve and provides in the related technology
Threshold voltage of semiconductor device is higher and has the problem of leaky.
On the one hand, the embodiment of the present application provides a kind of semiconductor devices, comprising:
It successively include bottom, separation layer and graph layer along the thickness direction of the semiconductor devices；
The graph layer includes top level structure, the first n-type region, first grid, second grid, p-type trap, N-type drift region
Domain and the second n-type region；
Along the width direction of the semiconductor devices, the first grid and the second grid are oppositely arranged, and described
One n-type region, the p-type trap, the N-type drift region domain and second n-type region are located at the first grid and described
Between second grid；
First n-type region, the p-type trap, the N-type drift region domain and second n-type region are along described half
The length direction of conductor device is set gradually.
In an alternative embodiment, the separation layer includes silicon oxide layer.
In an alternative embodiment, the top level structure includes silicon top level structure, and the bottom includes silicon bottom.
On the one hand, the embodiment of the present application provides a kind of manufacturing method of semiconductor devices, which comprises
A substrate is provided, along the thickness direction of the substrate, the substrate successively includes bottom, separation layer and top layer；
Along the length direction of the substrate, successively carry out the first ion implanting and the second ion implanting, the top layer according to
It is secondary to be respectively formed p-type trap and N-type drift region domain；
The first channel and the second channel, first channel and second ditch are formed by etching technics to the top layer
Road is sequentially located at the two sides of the p-type trap and the N-type drift region domain along the width direction of the substrate；
Polysilicon is filled in first channel, forms first grid, polysilicon is filled in second channel, forms the
Two grids；
Along the length direction of the substrate, in the region close to the first grid and the second grid to the top layer
Third ion implanting is carried out, the first n-type region is formed；
Along the length direction of the substrate, the region close to the N-type drift region domain to the top layer carry out the 4th from
Son injection, forms the second n-type region, and the top layer removes first n-type region, the first grid, the second grid, institute
State p-type trap, other regions in the N-type drift region domain form top level structure.
In an alternative embodiment, described to fill polysilicon in first channel, first grid is formed, described
Second channel fills polysilicon, is formed before second grid, further includes:
In the table of first channel, second channel, the p-type trap, the N-type drift region domain and the top layer
Face forms grid oxic horizon.
In an alternative embodiment, described to fill polysilicon in first channel, first grid is formed, described
Second channel fills polysilicon, forms second grid, comprising:
The polysilicon is filled in first channel by boiler tube, institute is filled in second channel by the boiler tube
State polysilicon；
To the polysilicon by chemically mechanical polishing CMP process carry out planarization process, obtain the first grid and
The second grid.
In an alternative embodiment, the third ion implanting is lightly doped drain LDD ion implanting.
In an alternative embodiment, the 4th ion implanting is source drain SDN type ion implanting.
Technical scheme includes at least following advantage:
By the way that first grid and second grid is set side by side, it is higher to solve threshold voltage caused by setting n-type region
The problem of, unlatching ability of the grid to channel of semiconductor devices is increased, the threshold voltage of semiconductor devices is reduced；Together
When, the anticreeping power of semiconductor devices is increased by the way that separation layer is arranged.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the application specific embodiment or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the application, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the plan view for the semiconductor devices that one exemplary embodiment of the application provides；
Fig. 2 is sectional view of the semiconductor devices that provides of one exemplary embodiment of the application along first direction；
Fig. 3 is the sectional view of the semiconductor devices that provides of one exemplary embodiment of the application in a second direction；
Fig. 4 is the flow chart of the manufacturing method for the semiconductor devices that one exemplary embodiment of the application provides；
Fig. 5 to Figure 10 is the process signal of the manufacturing method for the semiconductor devices that one exemplary embodiment of the application provides
Figure.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In the description of the present application, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for describe the application and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore should not be understood as the limitation to the application.In addition, term " first ", " second ",
" third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
In the description of the present application, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also may be used also indirectly connected through an intermediary
To be the connection inside two elements, it can be wireless connection, be also possible to wired connection.For the ordinary skill people of this field
For member, the concrete meaning of above-mentioned term in this application can be understood with concrete condition.
As long as in addition, the non-structure each other of technical characteristic involved in the application different embodiments disclosed below
It can be combined with each other at conflict.
Fig. 1 shows the top view of the semiconductor devices of one exemplary embodiment of the application offer；Fig. 2 shows this
Apply for the left view sectional view for the semiconductor devices that an exemplary embodiment provides；Fig. 3 shows one exemplary reality of the application
The front cross-sectional view of the semiconductor devices of example offer is provided.
With reference to Fig. 1, the direction D1 where defining the thickness of semiconductor devices 100 provided by the embodiments of the present application is first party
To the direction D2 where the width of semiconductor devices 100 is second direction, the direction D3 where the length of semiconductor devices 100
For third direction.
With reference to Fig. 2, semiconductor devices 100 successively includes bottom 110, separation layer 120 and graph layer 130 along the direction D1；
In the direction D1, defining bottom 110 to the direction of graph layer 130 is "upper", and the direction for defining graph layer 130 to bottom 110 is
"lower".Wherein, separation layer 120 can be oxide (such as silica), nitride (such as silicon nitride) or nitrogen oxides (example
Such as silicon oxynitride)；Bottom 110 can be semiconductor, such as silicon, germanium etc..
Referring to figs. 1 to Fig. 3, graph layer 130 includes the first n-type region 131, first grid 132, second grid 133, p-type
Trap 134, N-type drift region domain 135, the second n-type region 136 and top level structure 137；As shown in Figure 1, top level structure 137 is surround
In the first n-type region 131, first grid 132, second grid 133, p-type trap 134, N-type drift region domain 135 and the second N-type region
Except domain 136.Wherein, top level structure 137 can be semiconductor material, such as silicon, germanium etc..Optionally, top level structure 137 and bottom
The material of layer 110 is identical.
With reference to Fig. 1 and Fig. 2, in the direction D2, defining first grid 133 to the direction of first grid 132 is " preceding ", definition the
One grid 132 to the direction of second grid 133 is " rear "；With reference to Fig. 1 and Fig. 3, in the direction D3, define the first n-type region 131 to
The direction of second n-type region 136 is " right side ", and the direction for defining 136 to the first n-type region 131 of the second n-type region is " left side ".
With reference to Fig. 1 and Fig. 2, along the direction D2, first grid 132 and the second grid 133 are oppositely arranged, the first N-type region
Domain 131, p-type trap 134, N-type drift region domain 135 and the second n-type region 136 are located at first grid 132 and in graph layer 130
Region between two grids 133.
With reference to Fig. 1 and Fig. 3, along the direction D3, it is disposed with the first n-type region 131, p-type trap 134, N-type drift from left to right
Move region 135 and the second n-type region 136.
In conclusion the semiconductor devices of the embodiment of the present application is solved by the way that first grid and second grid is set side by side
The higher problem of threshold voltage caused by setting n-type region, increases unlatching energy of the grid to channel of semiconductor devices
Power reduces the threshold voltage of semiconductor devices；Meanwhile the leakproof electric energy of semiconductor devices is increased by the way that separation layer is arranged
Power.
Fig. 4 shows the flow chart of the manufacturing method of the semiconductor devices of one exemplary embodiment of the application offer.This
Semiconductor making method in embodiment can be used for manufacturing semiconductor devices of the Fig. 1 into Fig. 3 embodiment, in the embodiment of the present application
The direction being related to is identical to Fig. 3 embodiment as Fig. 1.This method comprises:
Step 401, a substrate is provided.
Illustratively, as shown in figure 5, along the direction D1 where the thickness of substrate 500, substrate 500 successively includes bottom
(Substrate) layer 510, isolation (Box) layer 520 and top (Top) layer 530.Wherein, separation layer 520 can be oxide (such as
Silica), nitride (such as silicon nitride) or nitrogen oxides (such as silicon oxynitride)；Bottom 510 and top layer 530 can be phase
Same material, can be semiconductor, such as silicon, germanium etc..The substrate 500 is commonly referred to as the silicon (Silicon-On- in insulating substrate
Insulator, SOI) structure.
Step 402, along the length direction of substrate, the first ion implanting and the second ion implanting are successively carried out, top layer according to
It is secondary to be respectively formed p-type trap and N-type drift region domain.
Illustratively, as shown in fig. 6, successively executing the first ion implanting and the second ion implanting to the right along the direction D3, point
It Xing Cheng not p-type trap 531 and N-type drift region domain 532.Wherein, the first ion implanting is p-well ion implanting, and the second ion implanting is N
Type drift ion implanting.
Step 403, the first channel and the second channel are formed by etching technics in top layer.
Illustratively, as shown in fig. 7, forward along the direction D2, distinguishing shape in top layer 530 by photoetching and dry etch process
At the first channel 5331 and the second channel 5341, the first channel 5331 and the second channel 5341 are sequentially located at p-type trap along the direction D2
531 and N-type drift region domain 532 two sides
Step 404, polysilicon is filled in the first channel, forms first grid, filled polysilicon in the second channel, form the
Two grids.
Illustratively, as shown in figure 8, in the first channel 5331, the second channel 5341, p-type trap 531, N-type drift region domain
534 and top layer 530 surface formed grid oxic horizon 5301；As shown in figure 9, being filled by boiler tube in the first channel 5331 more
Crystal silicon fills polysilicon in the second channel 5341 by boiler tube；Chemically mechanical polishing (Chemical is passed through to polysilicon
Mechanical Polishing, CMP) technique progress planarization process, obtain first grid 533 and second grid 534.
Step 405, along the length direction of substrate, top layer is carried out respectively close to the region of first grid and second grid
Third ion implanting and the 4th ion implanting form the first n-type region.
Illustratively, as shown in Figure 10, along the direction D3, in the region close to first grid 533 and second grid 534 to top
Layer 530 carry out lightly doped drain (Lightly Doped Drain, LDD) ion implantings and source drain (Source Drain,
SD) N-type ion is injected, and forms the first n-type region 535.
Step 406, along the length direction of substrate, the region close to N-type drift region domain top layer is carried out respectively third from
Son injection and the 4th ion implanting, form the second n-type region 536, and top layer removes the first n-type region, first grid, second grid, P
Type trap, N-type drift region domain other regions formed top level structure.
Illustratively, as shown in Figure 10, along the direction D3, top layer 530 is carried out in the region close to N-type drift region domain 532
LDD ion implanting and SDN type ion implanting, form the second n-type region 536, and top layer removes the first n-type region 535, first grid
533, second grid 534, p-type trap 531, N-type drift region domain 532 other regions formed top level structure 537.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes among the protection scope created still in the application.
Claims (8)
1. a kind of semiconductor devices characterized by comprising
It successively include bottom, separation layer and graph layer along the thickness direction of the semiconductor devices；
The graph layer include top level structure, the first n-type region, first grid, second grid, p-type trap, N-type drift region domain with
And second n-type region；
Along the width direction of the semiconductor devices, the first grid and the second grid are oppositely arranged, first N-type
Region, the p-type trap, the N-type drift region domain and second n-type region are located at the first grid and the second gate
Between pole；
First n-type region, the p-type trap, the N-type drift region domain and second n-type region are along the semiconductor
The length direction of device is set gradually.
2. semiconductor devices according to claim 1, which is characterized in that the separation layer includes silicon oxide layer.
3. semiconductor devices according to claim 1, which is characterized in that the top level structure includes silicon top level structure, institute
Stating bottom includes silicon bottom.
4. a kind of manufacturing method of semiconductor devices, which is characterized in that the described method includes:
A substrate is provided, along the thickness direction of the substrate, the substrate successively includes bottom, separation layer and top layer；
Along the length direction of the substrate, the first ion implanting and the second ion implanting are successively carried out, is successively divided in the top layer
It Xing Cheng not p-type trap and N-type drift region domain；
The first channel and the second channel, first channel and second channel edge are formed by etching technics in the top layer
The width direction of the substrate is sequentially located at the two sides of the p-type trap and the N-type drift region domain；
Polysilicon is filled in first channel, forms first grid, polysilicon is filled in second channel, forms second gate
Pole；
Along the length direction of the substrate, the top layer is distinguished close to the region of the first grid and the second grid
Third ion and the 4th ion implanting are carried out, the first n-type region is formed；
Along the length direction of the substrate, described the is carried out respectively to the top layer in the region close to the N-type drift region domain
Three ion implantings and the 4th ion implanting form the second n-type region, and the top layer is except first n-type region, described the
One grid, the second grid, the p-type trap, the N-type drift region domain other regions formed top level structure.
5. according to the method described in claim 4, forming the it is characterized in that, described fill polysilicon in first channel
One grid is filled polysilicon in second channel, is formed before second grid, further includes:
In the surface shape of first channel, second channel, the p-type trap, the N-type drift region domain and the top layer
At grid oxic horizon.
6. according to the method described in claim 5, forming the it is characterized in that, described fill polysilicon in first channel
One grid fills polysilicon in second channel, forms second grid, comprising:
The polysilicon is filled in first channel by boiler tube, it is described more in second channel filling by the boiler tube
Crystal silicon；
Planarization process is carried out by chemically mechanical polishing CMP process to the polysilicon, obtains the first grid and described
Second grid.
7. according to any method of claim 4 to 6, which is characterized in that the third ion implanting is lightly doped drain
LDD ion implanting.
8. according to any method of claim 4 to 6, which is characterized in that the 4th ion implanting is source drain SDN
Type ion implanting.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910743007.5A CN110491945B (en) | 2019-08-13 | 2019-08-13 | Semiconductor device and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910743007.5A CN110491945B (en) | 2019-08-13 | 2019-08-13 | Semiconductor device and method for manufacturing the same |
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| CN110491945A true CN110491945A (en) | 2019-11-22 |
| CN110491945B CN110491945B (en) | 2023-08-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113644132A (en) * | 2021-07-13 | 2021-11-12 | 上海华力集成电路制造有限公司 | Double-gate DMOS device based on SOI wafer and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1149203A (en) * | 1995-03-30 | 1997-05-07 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| CN105977290A (en) * | 2015-03-12 | 2016-09-28 | 英飞凌科技股份有限公司 | Semiconductor device, integrated circuit and method of manufacturing semiconductor device |
| CN106057897A (en) * | 2015-04-14 | 2016-10-26 | 英飞凌科技股份有限公司 | Semiconductor device comprising a transistor including a body contact portion and method for manufacturing the semiconductor device |
| CN107393871A (en) * | 2016-04-13 | 2017-11-24 | 英飞凌科技股份有限公司 | Integrated circuit and its manufacture method and semiconductor devices |
-
2019
- 2019-08-13 CN CN201910743007.5A patent/CN110491945B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1149203A (en) * | 1995-03-30 | 1997-05-07 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| CN105977290A (en) * | 2015-03-12 | 2016-09-28 | 英飞凌科技股份有限公司 | Semiconductor device, integrated circuit and method of manufacturing semiconductor device |
| CN106057897A (en) * | 2015-04-14 | 2016-10-26 | 英飞凌科技股份有限公司 | Semiconductor device comprising a transistor including a body contact portion and method for manufacturing the semiconductor device |
| CN107393871A (en) * | 2016-04-13 | 2017-11-24 | 英飞凌科技股份有限公司 | Integrated circuit and its manufacture method and semiconductor devices |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113644132A (en) * | 2021-07-13 | 2021-11-12 | 上海华力集成电路制造有限公司 | Double-gate DMOS device based on SOI wafer and manufacturing method thereof |
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| CN110491945B (en) | 2023-08-15 |
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