CN114639599B - Local service life control method for semiconductor device - Google Patents
Local service life control method for semiconductor device Download PDFInfo
- Publication number
- CN114639599B CN114639599B CN202210559291.2A CN202210559291A CN114639599B CN 114639599 B CN114639599 B CN 114639599B CN 202210559291 A CN202210559291 A CN 202210559291A CN 114639599 B CN114639599 B CN 114639599B
- Authority
- CN
- China
- Prior art keywords
- conductive type
- heavily doped
- type region
- semiconductor device
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 238000011084 recovery Methods 0.000 abstract description 31
- 239000000969 carrier Substances 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 8
- 230000006798 recombination Effects 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000005215 recombination Methods 0.000 description 6
- 229910001385 heavy metal Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- -1 Pt or Au Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2258—Diffusion into or out of AIIIBV compounds
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for controlling the local service life of a semiconductor device, wherein the semiconductor device at least comprises a group of two different conductive types, and at least two materials are added into the semiconductor device, wherein the minority carrier lifetime of the first material is longer than that of the second material; local lifetime control is achieved using the second material having a relatively short minority carrier lifetime; the second material is completely doped or contains at least a portion of the second conductivity type. The method realizes local service life control, can reduce the number of carriers stored in the diode in reverse recovery, reduces the maximum reverse recovery current in the reverse recovery process, and improves the speed of reverse recovery.
Description
Technical Field
The present invention relates to a method for controlling the lifetime of minority carriers of a semiconductor device, and more particularly, to a method for controlling the local lifetime of a semiconductor device.
Background
In the last decades, controlling the spatial distribution of recombination centers parallel to the axial direction of two different conductivity types (PN junctions) has become a very attractive new technique for improving the device trade-off performance, which can result in shorter turn-off times, smaller reverse overshoot currents and greater softness than the classical lifetime control techniques, which optimizes the device performance, i.e. achieves a better performance trade-off. For the traditional service life control technology, deep-level metal impurities have high diffusion coefficients, and electron irradiation generates uniformly distributed composite centers, so that the composite centers cannot be distributed in narrow local areas. The controllable local lifetime provides a new design parameter and a larger design freedom for optimizing the performance compromise of the device, and compared with the traditional lifetime control technology which introduces a recombination center in a large range in the whole device, the new lifetime control technology is called local lifetime control technology.
Lifetime control techniques, which are widely used in bipolar power devices to accelerate the extraction of excess electrons and holes, have been used to achieve higher switching speeds. The following common life control technologies are currently available:
1. heavy metal ions, such as Pt or Au, are doped to form some deep energy levels in the forbidden band of the power device (mainly silicon), thereby accelerating the recombination of electrons and holes and thus reducing minority carrier lifetime. The deep level of Au formation is closer to the center of the forbidden band, so that its leakage is larger. The working junction temperature of the device is difficult to exceed 150 ℃;
in the following, Pt is taken as an example to describe a common method for realizing lifetime control:
a. firstly, growing ILD (after a dielectric layer) on the front surface of the device, sputtering a layer of Pt metal on the back surface of the device, and forming Pt Silicide (metal Silicide) at high temperature, wherein the typical process condition is 550 ℃ for 30 minutes.
b. And (4) wet etching, and removing Pt which does not completely form the Silicide.
c. And (4) performing a high-temperature thermal process to push knots. Typical conditions are 950 ℃, 30 minutes;
since the diffusion rate of Pt in Silicon is fast, 950 ℃, Pt can be completely diffused into Silicon in 30 minutes of thermal process. Therefore, the service life control realized by adopting a mode of doping heavy metal ions is also called global service life control.
The disadvantage of using heavy metal ions to achieve lifetime control is that heavy metal ions can cause pollution to the production line. After the device is doped with heavy metal ions, the subsequent process flow needs to be independently controlled by a machine table, so that the pollution is prevented. This adds significantly to the difficulty.
2. High energy ion implantation accelerates the recombination of electrons and holes by ions striking the wafer to form some defect levels.
The defect levels formed by ion implantation require a low temperature anneal, typically around 300 c for about 1 hour, to repair some of the unstable defect levels. However, higher temperature thermal processes, such as above 400 ℃, repair all defects formed and thus have no life control implications. The ion implantation is usually performed after the front side process is completed. The level of defects created by ion implantation depends on where the ion implantation can reach.
The current common modes are electron irradiation, He injection and the like. Electrons are light and can easily penetrate through a wafer, so that the lifetime control formed by electron irradiation is generally global lifetime control, the defect energy level formed by electron irradiation is closer to the center of a forbidden band, and thus the leakage of the device, particularly the high-temperature leakage, is large, and the device is difficult to work under the condition that the junction temperature exceeds 150 ℃.
He is injected, because He is heavier, the highest energy of a common ion injection machine can only reach 1.5MeV, and the depth of the injection can be 5-6 um. However, after the front metal is manufactured on the device, the thickness of the front metal is usually 4-5 um, and the He is difficult to enter the surface of the silicon wafer after the thickness of the dielectric layer of 1um is added. Unless there is a higher energy ion implanter, for example, the highest energy may be up to 3MeV, or even 6 MeV; however, this machine is more expensive and causes great difficulty in production. The lifetime control of He implantation is a technique of local lifetime control.
Disclosure of Invention
The invention aims to provide a local service life control method of a semiconductor device, which can improve the performance and application environment of the semiconductor device through local service life control technology quickly at low cost.
To achieve the above technical object, the present invention provides a method for controlling local lifetime of a semiconductor device, the semiconductor device at least comprises a set of two different conductivity types, wherein: incorporating at least two materials into said semiconductor device, wherein the minority carrier lifetime of a first material is longer than the minority carrier lifetime of a second material, said minority carrier lifetime of said second material being 1/2 or less of the minority carrier lifetime of said first material; using said second material having a relatively short minority carrier lifetime to achieve localized lifetime control; the second material is completely doped with the second conductive type or at least comprises a part of the second conductive type; the second material uses silicon germanium SiGe, polycrystalline silicon containing grains or a direct band gap semiconductor, which is gallium arsenide GaAs or indium phosphide InP, to reduce minority carrier lifetime.
In the present invention, the semiconductor device comprises at least two materials, one of which has a long minority carrier lifetime and the other of which has a short minority carrier lifetime. Minority carrier lifetime is short to realize local lifetime control. The device comprises at least one set of two different conductivity types (PN junctions). The material with a short minority carrier lifetime is completely doped or at least comprises a part of the second conductivity type. The scheme of the invention is a technology for controlling the local service life, which can reduce the number of carriers stored in a diode in reverse recovery, reduce the maximum reverse recovery current in the reverse recovery process and improve the reverse recovery speed. Meanwhile, because the technology of local area lifetime control is adopted, the softness factor in the reverse recovery process is not substantially deteriorated.
As a further improvement, additional buffer layers are added between the different materials.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and forming a first conductive type drift region, and a second conductive type region positioned at the upper part, wherein a control layer made of the second material is arranged between the epitaxial layer and the second conductive type region.
As a further improvement, a second conductivity type doping is introduced during the growth of the second material, or formed by ion implantation after the production of the second material, the second conductivity type doping forming two different conductivity types at the bottom of the control layer or at the upper part of the epitaxial layer.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and used for forming a drift region of the first conductive type, and a second conductive type region positioned on the upper portion, wherein a control layer made of the second material is arranged on the upper portion of the second conductive type region.
As a further improvement, the semiconductor device is an insulated gate bipolar transistor IGBT, which includes: the transistor comprises a back second conductive type region, a back first conductive type region, a first conductive type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conductive type region and a heavily doped second conductive type region, wherein a control layer made of the second material is arranged on the outer side of the back second conductive type region.
As a further improvement, the semiconductor device is a MOSFET for use in a bridge circuit and implementing soft switching, comprising: the MOSFET comprises a heavily doped first conduction type substrate, a first conduction type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conduction type region and a heavily doped second conduction type region, wherein the first conduction type drift region and the grid oxide layer are arranged on the substrate, the heavily doped first conduction type region and the heavily doped second conduction type region are arranged above the channel, the heavily doped second conduction type region is connected with the channel, the heavily doped first conduction type region and the heavily doped second conduction type region are connected with a source electrode through source electrode metal, the middle upper layer inside the channel is made of the second material, and the MOSFET is conducted by utilizing a parasitic body diode to realize zero-voltage switching.
As a further improvement, the method of disposing the second material comprises: the arrangement is introduced either on the whole silicon wafer or, for termination regions subjected to a higher breakdown voltage, only in the active region of the semiconductor device by means of etching or selective growth.
The control method is simple, convenient to produce and implement, suitable for various semiconductor devices and functional requirements, capable of improving the devices and the performance of the devices and capable of realizing the local service life control of the semiconductor devices at low cost.
Drawings
FIG. 1 is a diagram of a conventional fast recovery diode;
FIG. 2 is a schematic diagram of a first embodiment of a fast recovery diode according to the present invention;
FIG. 3 is a schematic diagram of a second embodiment of the fast recovery diode of the present invention;
FIG. 4 is a schematic diagram of a third embodiment of the fast recovery diode of the present invention;
FIG. 5 is a schematic diagram of an IGBT of the present invention;
FIG. 6 is a diagram of a MOSFET in accordance with the present invention;
FIG. 7 is a schematic view of a production scheme of the present invention.
Reference numerals are as follows: the semiconductor device comprises a heavily doped first conduction type substrate 1, an epitaxial layer 2, a second conduction type region 3, a control layer 4, a back second conduction type region 11, a back first conduction type region 12, a first conduction type drift region 13, a gate oxide layer 14, a gate 15, a channel 16, a heavily doped first conduction type region 17, a heavily doped second conduction type region 18, a heavily doped first conduction type substrate 21 and an active region 22.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the field of semiconductor devices, the first conductivity type and the second conductivity type are opposite conductivity types, and may be the first conductivity type is an N type, and the second conductivity type is a P type; the first conductivity type may be P-type, and the second conductivity type may be N-type. The present invention is understood to mean that the first conductivity type is N-type and the second conductivity type is P-type.
As shown in fig. 1 to 7, the present invention provides a method for controlling local lifetime of a semiconductor device, wherein the semiconductor device at least comprises a set of two different conductivity types (PN junctions), wherein: incorporating at least two materials into said semiconductor device, wherein the minority carrier lifetime of a first material is longer than the minority carrier lifetime of a second material, said minority carrier lifetime of said second material being 1/2 or less of the minority carrier lifetime of said first material; using said second material having a relatively short minority carrier lifetime to achieve localized lifetime control; the second material is completely doped with the second conductive type or at least comprises a part of the second conductive type; the second material adopts silicon germanium SiGe, polycrystalline silicon containing crystal grains or a direct band gap semiconductor which is gallium arsenide GaAs or indium phosphide InP to reduce minority carrier lifetime.
In the present invention, the semiconductor device comprises at least two materials, one of which has a long minority carrier lifetime and the other of which has a short minority carrier lifetime. The minority carrier lifetime of the first material is standard and common semiconductor device material, and the control method provided by the invention is to introduce the minority carrier lifetime with short lifetime for realizing the local lifetime control. The device comprises at least one set of two different conductivity types (PN junctions). The material with a short minority carrier lifetime is completely doped or at least comprises a part of the second conductivity type. The scheme of the invention is a technology for controlling the local service life, which can reduce the number of carriers stored in a diode in reverse recovery, reduce the maximum reverse recovery current in the reverse recovery process and improve the reverse recovery speed. Meanwhile, because the technology of local area lifetime control is adopted, the softness factor in the reverse recovery process is not substantially deteriorated.
As a further improvement, additional buffer layers are added between the different materials.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and forming a first conductive type drift region, and a second conductive type region positioned at the upper part, wherein a control layer made of the second material is arranged between the epitaxial layer and the second conductive type region.
As a further improvement, a second conductivity type doping is introduced during the growth of the second material, or formed by ion implantation after the production of the second material, the second conductivity type doping forming two different conductivity types (PN junctions) at the bottom of the control layer or at the upper part of the epitaxial layer.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and used for forming a drift region of the first conductive type, and a second conductive type region positioned on the upper portion, wherein a control layer made of the second material is arranged on the upper portion of the second conductive type region.
As a further improvement, the semiconductor device is an insulated gate bipolar transistor IGBT, which includes: the gate structure comprises a back second conductive type region, a back first conductive type region, a first conductive type drift region, a gate oxide layer, a gate, a channel, a heavily doped first conductive type region and a heavily doped second conductive type region, wherein a control layer made of the second material is arranged on the outer side of the back second conductive type region.
As a further improvement, the semiconductor device is a MOSFET for use in a bridge circuit and implementing soft switching, comprising: the MOSFET comprises a heavily doped first conduction type substrate, a first conduction type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conduction type region and a heavily doped second conduction type region, wherein the first conduction type drift region and the grid oxide layer are arranged on the substrate, the heavily doped first conduction type region and the heavily doped second conduction type region are arranged above the channel, the heavily doped second conduction type region is connected with the channel, the heavily doped first conduction type region and the heavily doped second conduction type region are connected with a source electrode through source electrode metal, the middle upper layer inside the channel is made of the second material, and the MOSFET is conducted by utilizing a parasitic body diode to realize zero-voltage switching.
As a further improvement, the method of disposing the second material comprises: the arrangement is introduced either on the whole silicon wafer or, for termination regions subjected to a higher breakdown voltage, only in the active region of the semiconductor device by means of etching or selective growth.
Fig. 1 is a simplest fast recovery reverse diode, the substrate being a heavily doped first conductivity type substrate 1, the doping concentration being high in order to form a good ohmic contact. An epitaxial layer 2 on top of the substrate to form a drift region of the first conductivity type, the thickness and doping concentration of the drift region being dependent on the breakdown voltage of the device. However, in order to improve the reverse recovery softness of the fast recovery diode, a graded region may be provided between the heavily doped first conductivity type substrate 1 and the epitaxial layer 2, and the doping concentration may gradually transition from a high concentration to a high concentration, or a Buffer region may be added. The second conductivity type region 3 is formed by ion implantation and is of the second conductivity type in order to reduce the number of carriers stored during reverse recovery of the diodeThe doping concentration of the region 3 is usually lower, and the common doping concentration is 5e 12-5 e13/cm 2 In the meantime. The lower the doping concentration, the higher the on-state voltage drop of the device and the lower the number of carriers stored by reverse recovery, which is a trade-off relationship. However, too low a doping concentration may result in the ohmic contact of the second conductivity type region being affected and, in addition, may reduce the surge current capability of the device. This is all a matter of special attention in the design.
To further speed up the reverse recovery capability of the diode, the patent proposes the following local lifetime control technique. And additionally introducing a control layer 4 made of the second material on the heavily doped first conductive type substrate 1 and the epitaxial layer 2, wherein the control layer 4 is an additional material different from the heavily doped first conductive type substrate 1 and the epitaxial layer 2, and the material is characterized by lower minority carrier lifetime.
Some materials that can be selected, such as SiGe, have an order of magnitude lower minority carrier lifetime than Si because of the addition of Ge to silicon; in SiGe, if the Ge content exceeds 15%, the lattice deformation is severe, and therefore, in practical applications, it is usually less than 15%. Or polysilicon, which has a reduced minority carrier lifetime due to the introduction of some Grain. Silicon is an indirect bandgap semiconductor, and direct recombination of electrons and holes is difficult, so that minority carrier lifetime is long. If a layer of direct band gap semiconductor, such as GaAs and InP, is introduced, minority carrier lifetime can be greatly reduced. There may be some mismatch in the crystal lattice of different semiconductor materials, and an additional buffer layer may be required at this time. The minority carrier lifetime of the second material incorporated in the present invention is less than the minority carrier lifetime of the first material and can be 1/2, 1/3 or even 1/100 and 1/1000 of the minority carrier lifetime of the first material. A preferred embodiment is 1/10 for the first material having a minority carrier lifetime.
The material of the control layer 4 needs to be doped with a second conductivity type. The second conductivity type doping can be introduced during material growth, such as SiGe growth, and can be achieved. Or may be formed by ion implantation after the material is produced.
The location of the two different conductivity types (PN junctions) formed is shown in dashed lines in fig. 2. Because the place of the junction is usually the place where the electric field strength is strongest. The place where the electric field strength is strongest is inside the control layer 4, which may increase the leakage of the device, and a more preferred scheme is shown by the dotted line in fig. 3, where the junction is located below the control layer 4.
As another embodiment, as shown in fig. 4, the control layer 4 may be introduced after the heavily doped first conductive type substrate 1, the epitaxial layer 2, and the second conductive type region 3 of the device are formed, and the control layer 4 is then extended.
The invention is also applicable to bipolar power devices in which the device requires injection of electrons and holes to increase the concentration of carriers in the drift region, thereby reducing the on-resistance and achieving a low on-voltage drop. However, when the device is subjected to withstand voltage, the excess electrons and holes in the device need to be pumped away. The patent proposes a new local lifetime control mode to accelerate the extraction of carriers, thereby increasing the switching speed of the device. The patent is also applicable to unipolar devices, typically unipolar devices such as MOSFETs, having a parasitic body diode. When MOSFETs are used in bridge circuits, to achieve soft switching, ZVS is achieved by utilizing the parasitic body diode conduction, which also reduces the minority carrier lifetime to speed up the reverse recovery of the MOSFET parasitic body diode.
The invention provides a technical application embodiment of an Insulated Gate Bipolar Transistor (IGBT), as shown in figure 5, the structure of a common Trench Based FS IGBT comprises: the back side second conductivity type region 11, the Collector, and the back side first conductivity type region 12 are used to form a field stop. The doping concentration and the thickness of the first conductivity type drift region 13 determine the breakdown voltage of the device. The gate oxide 14 and the gate 15 form a trench gate, wherein the gate oxide 14 is typically silicon dioxide and the gate 15 is polysilicon, which is used to form the gate. Further comprising: a channel 16, a heavily doped first conductivity type region 17, and a heavily doped second conductivity type region 18. The heavily doped second conductivity type region 18 is connected to the channel 16. Heavily doped firstThe conductivity type region 17 and the heavily doped second conductivity type region 18 are together connected to the source via a source metal. In order to reduce the turn-off loss of the IGBT, it is desirable to implant the back surface second conductivity type region 11 with as little second conductivity type as possible, reducing the implantation efficiency thereof. The method is to reduce the doping dose of the second conductive type, such as the implantation dose is usually 5e 12-5 e13/cm 2 And reducing the energy injected from the second conductive type region to accelerate the recombination of electrons. And local lifetime control can be performed in the second conductivity type region on the back surface. According to the above solution, the second material is added on the back second conductivity type region 11, and the minority carrier lifetime of the second material is reduced. Thus, the injection of holes can be reduced, thereby reducing the turn-off loss of the IGBT.
The invention also provides the technical application embodiment of the metal-oxide-semiconductor field effect transistor MOSFET, in particular to a MOSFET structure which is used in a bridge circuit and realizes soft switching. As shown in fig. 6, the transistor comprises a heavily doped first conductive type substrate, a first conductive type drift region, a gate oxide layer and a gate electrode on the substrate form a trench gate, the gate oxide layer is made of silicon dioxide, the gate electrode is made of polysilicon, a channel, a heavily doped first conductive type region and a heavily doped second conductive type region, the heavily doped second conductive type region is connected with the channel, and the heavily doped first conductive type region and the heavily doped second conductive type region are connected with a source electrode through a source electrode metal.
Although a MOSFET is a multi-sub device, its parasitic body diode needs to be turned on to realize ZVS, which also requires a local lifetime control technique. A new material may be introduced to reduce the lifetime control technique. The dotted line shown in fig. 6, i.e., the inner, middle and upper layer, is made of the second material, which is composed of the new material. The new material has short minority carrier lifetime and can help the recombination of electrons and holes, thereby improving the speed of reverse recovery.
In the prior art, the introduction of materials is introduced on the whole silicon wafer. However, the terminal region is required to bear a relatively high breakdown voltage, and the invention is also improved by the corresponding technology. As shown in fig. 7, new materials can be introduced only in the active region 22 of the device by etching or by selective growth. There are also some applications, such as RC-IGBTs, where IGBTs and diodes are integrated. It is also possible that the new material is only used in the diode part and the IGBT part is not introduced with this new material.
The invention relates to a local service life control technology, which can reduce the number of carriers stored in a diode in reverse recovery, reduce the maximum reverse recovery current in the reverse recovery process and improve the reverse recovery speed. Meanwhile, because the technology of local area lifetime control is adopted, the softness factor in the reverse recovery process is not substantially deteriorated. The control method is simple, convenient to produce and implement, suitable for various semiconductor devices and functional requirements, capable of improving the devices and the performance of the devices and capable of achieving local service life control of the semiconductor devices at low cost. The local lifetime control technique introduced in the patent can be used in cooperation with other lifetime control techniques, such as Au/Pt doping, resistance irradiation, He injection and the like, so that a better effect is achieved.
It is to be understood that the scope of the present invention is not to be limited to the non-limiting embodiments, which are illustrated as examples only. The essential protection sought herein is further defined in the scope provided by the independent claims, as well as in the claims dependent thereon.
Claims (8)
1. A method for controlling the local lifetime of a semiconductor device, said semiconductor device comprising at least one set of two different conductivity types, characterized by:
incorporating at least two materials into said semiconductor device, wherein the minority carrier lifetime of a first material is longer than the minority carrier lifetime of a second material, said minority carrier lifetime of said second material being 1/2 or less of the minority carrier lifetime of said first material;
local lifetime control is achieved using the second material having a relatively short minority carrier lifetime;
the second material is completely doped with the second conductive type or at least comprises a part of the second conductive type;
the second material adopts silicon germanium SiGe, polycrystalline silicon containing crystal grains or a direct band gap semiconductor which is gallium arsenide GaAs or indium phosphide InP to reduce minority carrier lifetime.
2. The method of claim 1, wherein: additional buffer layers are added between the different materials.
3. The method of claim 2, wherein: the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and forming a first conductive type drift region, and a second conductive type region positioned at the upper part, wherein a control layer made of the second material is arranged between the epitaxial layer and the second conductive type region.
4. A semiconductor device local lifetime controlling method according to claim 3, wherein: introducing a second conductive type doping during the growth of the second material, or forming the second conductive type doping through ion implantation after the second material is produced, wherein the second conductive type doping forms two different conductive types at the bottom of the control layer or at the upper part of the epitaxial layer.
5. The method of claim 2, wherein: the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and forming a first conductive type drift region, and a second conductive type region positioned on the upper part, wherein a control layer made of the second material is arranged on the upper part of the second conductive type region.
6. The method of claim 2, wherein: the semiconductor device is an Insulated Gate Bipolar Transistor (IGBT) and comprises: the transistor comprises a back second conductive type region, a back first conductive type region, a first conductive type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conductive type region and a heavily doped second conductive type region, wherein a control layer made of the second material is arranged on the outer side of the back second conductive type region.
7. The method of claim 2, wherein: the semiconductor device is a metal-oxide-semiconductor field effect transistor MOSFET used in a bridge circuit and realizing soft switching, and comprises: the MOSFET comprises a heavily doped first conduction type substrate, a first conduction type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conduction type region and a heavily doped second conduction type region, wherein the first conduction type drift region and the grid oxide layer are arranged on the substrate, the heavily doped first conduction type region and the heavily doped second conduction type region are arranged above the channel, the heavily doped second conduction type region is connected with the channel, the heavily doped first conduction type region and the heavily doped second conduction type region are connected with a source electrode through source electrode metal, the middle upper layer inside the channel is made of the second material, and the MOSFET is conducted by utilizing a parasitic body diode to realize zero-voltage switching.
8. The method of claim 2, wherein: the method of disposing the second material comprises: the arrangement is introduced either on the whole silicon wafer or, for termination regions subjected to a higher breakdown voltage, only in the active region of the semiconductor device by means of etching or selective growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210559291.2A CN114639599B (en) | 2022-05-23 | 2022-05-23 | Local service life control method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210559291.2A CN114639599B (en) | 2022-05-23 | 2022-05-23 | Local service life control method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114639599A CN114639599A (en) | 2022-06-17 |
| CN114639599B true CN114639599B (en) | 2022-08-02 |
Family
ID=81953263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210559291.2A Active CN114639599B (en) | 2022-05-23 | 2022-05-23 | Local service life control method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114639599B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701162A (en) * | 2013-12-06 | 2015-06-10 | 江苏物联网研究发展中心 | Semiconductor component, PIN diode and IGBT manufacture methods |
| CN107516681A (en) * | 2016-06-15 | 2017-12-26 | 全球能源互联网研究院有限公司 | A kind of fast recovery diode and its manufacture method |
| CN107946360B (en) * | 2017-05-02 | 2023-10-20 | 中国电子科技集团公司第二十四研究所 | Power MOSFET device with carrier life adjusting region and manufacturing method thereof |
| CN109216472A (en) * | 2018-08-28 | 2019-01-15 | 全球能源互联网研究院有限公司 | fast recovery diode and preparation method thereof |
-
2022
- 2022-05-23 CN CN202210559291.2A patent/CN114639599B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114639599A (en) | 2022-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7538412B2 (en) | Semiconductor device with a field stop zone | |
| US7602045B2 (en) | Semiconductor device and inverter device using the same | |
| US7994569B2 (en) | Semiconductor device and method for forming the same | |
| CN108122971B (en) | RC-IGBT device and preparation method thereof | |
| JP2000323488A (en) | Diode and manufacture thereof | |
| CA2285067C (en) | Silicon carbide field controlled bipolar switch | |
| CN109166916B (en) | Insulated gate bipolar transistor and preparation method thereof | |
| CN109192771B (en) | Charge storage type insulated gate bipolar transistor and preparation method thereof | |
| CN101752415A (en) | Insulated gate bipolar transistor and method for producing same | |
| CN110137250B (en) | High-speed IGBT device with ultralow conduction voltage drop | |
| CN109065608B (en) | Transverse bipolar power semiconductor device and preparation method thereof | |
| CN115020479A (en) | Depletion type silicon carbide bipolar device structure and manufacturing method | |
| US8592903B2 (en) | Bipolar semiconductor device and manufacturing method | |
| KR20010094144A (en) | Insulated gate bipolar transistor having high breakdown voltage in reverse blocking mode and method for fabricating the same | |
| KR101398125B1 (en) | Self aligned fast recovery diode and fabrication method thereof | |
| CN108155230B (en) | Transverse RC-IGBT device and preparation method thereof | |
| CN111933705A (en) | Manufacturing method of power semiconductor device and power semiconductor device | |
| CN109346509B (en) | Charge storage type insulated gate bipolar transistor and preparation method thereof | |
| CN114639599B (en) | Local service life control method for semiconductor device | |
| US20230047794A1 (en) | Multi-trench Super-Junction IGBT Device | |
| CN116110961A (en) | Trench gate bipolar transistor and manufacturing process thereof | |
| CN114023815B (en) | Semi-vertical GaN-based reverse conducting IGBT device and preparation method thereof | |
| CN115084229A (en) | P + shielding layer self-clamping groove type silicon carbide IGBT device and preparation method thereof | |
| CN110534582B (en) | Fast recovery diode with composite structure and manufacturing method thereof | |
| KR100505562B1 (en) | Insulated Gate Bipolar Transistor with Multi-Layer Buffer Structure and Manufacturing Method Thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |