CN114629443A - Doherty power amplifier - Google Patents
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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Abstract
The invention discloses a Doherty power amplifier, which comprises an input unit, a front-stage tube core, an inter-stage unit, a rear-stage tube core and an output unit, wherein the rear-stage tube core comprises a carrier amplifier tube core and a peak amplifier tube core; the input unit includes a first input matching circuit; the interstage unit comprises a first output matching circuit, a second input matching circuit and a third input matching circuit; the output unit includes a second output matching circuit and a third output matching circuit. The Doherty power amplifier has the advantages of large output power and high back-off efficiency, and has the characteristics of low cost and small volume.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a Doherty power amplifier.
Background
With the rapid development of the fifth generation mobile communication technology (5G), the communication system puts higher requirements on the core component radio frequency power amplifier in the radio frequency transmitter. One of the core technologies of 5G is Massive MIMO (Massive Multiple Input Multiple Output), which is a large-scale Multiple Input Multiple Output (MIMO), on the one hand, compared with MIMO (Multiple Input Multiple Output), the Massive MIMO is greatly increased in the number of antennas, and is increased from a conventional 2/4/8 antenna to a 64/128/256 antenna; on the other hand, the method has the advantages that the vertical-dimension space domain can be utilized, and the radiation of the signals is an electromagnetic beam, so that the channel capacity can be improved, and the inter-channel interference can be reduced. Meanwhile, because the coverage range of the 5G base station is smaller than that of the 3G base station and the 4G base station, operators generally adopt a system of a macro base station and a small base station, wherein the macro base station has a wide coverage area and large power, and the small base station has a small coverage area and small power, but generally speaking, the number of the 5G base stations is several times that of the 3G base station and the 4G base station, and millions of base stations are expected to be built in the whole country. By combining the above two points, that is, the number of base stations increases dramatically and the number of antennas/channels in the base stations also increases several times, higher requirements are inevitably put forward on the performance of the radio frequency power amplifier of the core component.
In recent years, the development of the third generation semiconductor is faster and faster, and the applications based on the third generation semiconductor are also infinite. As a third generation semiconductor, the GaN chip-based power amplifier has the remarkable advantages of high power density, high efficiency, high breakdown voltage and the like. Compared with the first generation semiconductor LDMOS, the GaN has the advantages that the application frequency is high, the LDMOS can only work below 4GHz generally, and meanwhile, the GaN power amplifier has higher efficiency than the LDMOS; compared with the second generation semiconductor GaAs, the power density of the GaN is higher, the working efficiency is higher, and the working voltage is higher. At present, a GaN power amplifier is completely open in the applications of radar, radio frequency energy, satellite communication and the like, and as the frequency band of 5G is over 4GHz and is not suitable for the traditional LDMOS, the GaN power amplifier is also applied to a part of base stations, but the price is a bottleneck limiting the large-scale application of GaN.
The power amplifier for communication pursues better linearity, generally works under the state of rolling back, but the power amplifier efficiency under the state of rolling back can sharply decline, under the prerequisite that the number of channels is more, power is bigger, the inefficiency can provide higher requirement to the energy supply of basic station to become mutually and increase the basic station cost, consequently, it is an inherent demand of this type of power amplifier to promote the power amplifier efficiency under the state of rolling back.
Therefore, in view of the above technical problems, it is necessary to provide a Doherty power amplifier.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a Doherty power amplifier, which has the characteristics of low cost and small size, and has the advantages of large output power and high back-off efficiency.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a Doherty power amplifier comprises an input unit, a front-stage tube core, an inter-stage unit, a rear-stage tube core and an output unit, wherein the rear-stage tube core comprises a carrier amplifier tube core and a peak amplifier tube core;
the input unit comprises a first input matching circuit, a second input matching circuit and a third input matching circuit, wherein the first input matching circuit is used for matching the input impedance of the front-stage die to a first impedance threshold value;
the interstage unit comprises a first output matching circuit, a second input matching circuit and a third input matching circuit, wherein the first output matching circuit is used for matching the output impedance of a preceding stage die to a first impedance threshold value, the second input matching circuit is used for matching the input impedance of a carrier amplifier die to a second impedance threshold value, and the third input matching circuit is used for matching the input impedance of a peak amplifier die to a third impedance threshold value;
the output unit comprises a second output matching circuit and a third output matching circuit, the second output matching circuit is used for matching the output impedance of the carrier amplifier tube core to a second impedance threshold value, and the third output matching circuit is used for matching the output impedance of the peak amplifier tube core to a third impedance threshold value.
In an embodiment, the inter-stage unit further includes a power divider and a phase compensation line, an input end of the power divider is connected to the first output matching circuit, a first output end of the power divider is directly connected to the second input matching circuit, and a second output end of the power divider is connected to the third input matching circuit through the phase tuning line.
In an embodiment, the output unit further includes a first transmission cancellation line, a second transmission cancellation line, and an impedance transformation line, the first transmission cancellation line is connected to the second output matching circuit, the second transmission cancellation line is connected to the third output matching circuit, and the impedance transformation line is connected to the first transmission cancellation line and the second transmission cancellation line.
In an embodiment, the first input matching circuit, the second input matching circuit, the third input matching circuit, the first output matching circuit, the second output matching circuit, and the third output matching circuit are all topology structures including series inductors and parallel capacitors, and are used for adjusting input impedance or output impedance, wherein the inductors are formed by winding microstrip lines.
In an embodiment, the first transmission cancellation line and the second transmission cancellation line are both topology structures including a plurality of series inductors, and are used for adjusting output impedance and phase, wherein the inductors are formed by winding microstrip lines.
In one embodiment, the carrier amplifier is in a class AB operating state, the peak amplifier is in a class C operating state, and the Doherty power amplifier includes a saturation state and a back-off state, wherein:
in a saturation state, the carrier amplifier and the peak amplifier work normally, and the matching impedance of the first transmission cancellation line and the matching impedance of the second transmission cancellation line are both a first rated impedance value;
in a backspacing state, the carrier amplifier normally works, the peak amplifier does not work, the matching impedance of the first transmission cancellation line and the matching impedance of the second transmission cancellation line are respectively a second rated impedance value and an open-circuit high impedance value, and the second rated impedance value is 1/2 of the first rated impedance value.
In an embodiment, the Doherty power amplifier further comprises a plurality of bias circuits, which are used for supplying power to the front-stage die and the back-stage die and isolating the radio-frequency signals in the working frequency band.
In one embodiment, the input unit, the inter-stage unit and the output unit are integrated passive devices formed based on an IPD technology, the integrated passive devices include a substrate and a plurality of dielectric layers and metal layers on a surface of the substrate, and the metal layers are connected to each other through metalized via holes.
In one embodiment, the operating frequency band of the Doherty power amplifier is 4.8-5 GHz, the power gain Gp is more than or equal to 25dB, the peak output power Psat is more than or equal to 45dBm, and the operating efficiency DE when the Doherty power amplifier backs off by 6dB is more than or equal to 40%.
In one embodiment, the front-stage die and the back-stage die are GaN power dies; and/or the first impedance threshold, the second impedance threshold, and the third impedance threshold are equal.
The invention has the following beneficial effects:
the Doherty power amplifier has the advantages of large output power and high back-off efficiency, and has the characteristics of low cost and small volume.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a block schematic diagram of a Doherty power amplifier in the present invention;
FIG. 2 is a schematic diagram of a stack of integrated passive devices in an embodiment of the invention;
fig. 3 is a schematic diagram of a Doherty power amplifier in the present invention;
FIG. 4 is a DC offset simulation diagram for a subsequent die in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of a die output matching circuit in an embodiment of the invention;
FIGS. 6a-6c are graphs of frequency-insertion loss simulations of a die output matching circuit in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a die input matching circuit in an embodiment of the invention;
FIGS. 8a-8c are graphs of frequency-insertion loss simulations of a die input matching circuit in accordance with an embodiment of the present invention;
FIG. 9 is a schematic diagram of a first transmission cancellation line in accordance with an embodiment of the present invention;
FIG. 10 is a schematic diagram of a second transmission cancellation line in accordance with an embodiment of the present invention;
fig. 11 is an IPD layout of the Doherty power amplifier in an embodiment of the present invention;
fig. 12 is a graph of input power-output power simulation for a Doherty power amplifier in an embodiment of the present invention;
fig. 13 is a graph of output power versus operating efficiency simulation for a Doherty power amplifier in an embodiment of the present invention;
fig. 14 is a simulation graph of input power-gain of a Doherty power amplifier in an embodiment of the invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
Referring to fig. 1, the invention discloses a Doherty power amplifier, which includes an input unit, a front-stage die, an inter-stage unit, a back-stage die and an output unit, where the back-stage die includes a carrier amplifier die and a peak amplifier die;
the input unit comprises a first input matching circuit, and the first input matching circuit is used for matching the input impedance of the previous-stage die to a first impedance threshold value;
the interstage unit comprises a first output matching circuit, a second input matching circuit and a third input matching circuit, wherein the first output matching circuit is used for matching the output impedance of the front-stage die to a first impedance threshold value, the second input matching circuit is used for matching the input impedance of the carrier amplifier die to a second impedance threshold value, and the third input matching circuit is used for matching the input impedance of the peaking amplifier die to a third impedance threshold value;
the output unit comprises a second output matching circuit and a third output matching circuit, the second output matching circuit is used for matching the output impedance of the carrier amplifier die to a second impedance threshold, and the third output matching circuit is used for matching the output impedance of the peaking amplifier die to a third impedance threshold.
Furthermore, the interstage unit further comprises a power divider and a phase compensation line, wherein the input end of the power divider is connected with the first output matching circuit, the first output end of the power divider is directly connected with the second input matching circuit, and the second output end of the power divider is connected with the third input matching circuit through the phase tuning line.
Furthermore, the output unit further comprises a first transmission cancellation line, a second transmission cancellation line and an impedance transformation line, the first transmission cancellation line is connected with the second output matching circuit, the second transmission cancellation line is connected with the third output matching circuit, and the impedance transformation line is connected with the first transmission cancellation line and the second transmission cancellation line.
The carrier amplifier in the invention is in AB class working state, the peak amplifier is in C class working state, the Doherty power amplifier includes saturation state and backspacing state, wherein:
in a saturation state, the carrier amplifier and the peak amplifier work normally, and the matching impedance of the first transmission cancellation line and the matching impedance of the second transmission cancellation line are both a first rated impedance value;
in a backspacing state, the carrier amplifier normally works, the peak amplifier does not work, the matching impedance of the first transmission cancellation line and the matching impedance of the second transmission cancellation line are respectively a second rated impedance value and an open-circuit high impedance value, and the second rated impedance value is 1/2 of the first rated impedance value.
Preferably, the front-stage die and the rear-stage die are GaN power dies; the first impedance threshold, the second impedance threshold, and the third impedance threshold are equal.
Preferably, the input unit, the inter-stage unit and the output unit are integrated passive devices formed based on an IPD technology, the integrated passive devices include a substrate and a plurality of dielectric layers and metal layers on a surface of the substrate, the metal layers are connected to each other through metallized via holes, and an inductor (formed by winding a microstrip line), a capacitor and the like are formed on the integrated passive devices.
Referring to fig. 2, the integrated passive device in this embodiment includes a GaAs substrate, and a plurality of SiN dielectric layers and Metal layers on the surface of the GaAs substrate, Metal0 is a back Metal layer, Metal1, Metal2, and Metal3 are Metal layers of a drawing circuit, and SiN1 and SiN2 are SiN dielectric layers between the Metal layers.
The present embodiment is further described below with reference to die selection, die impedance acquisition, matching circuit design, and layout design.
In this embodiment, the first impedance threshold, the second impedance threshold, and the third impedance threshold are all 50 ohms, the first rated impedance value is 50 ohms, and the second rated impedance value is 25 ohms.
Die select
The first step for power amplifier design is to select the appropriate die. Currently, the power density of a 28VGaN die is generally about 4.5W/mm, where mm is a unit of the gate width of the die, and the larger the gate width of the die, the higher the power that can be provided.
The peak output power of the power amplifier in this embodiment is 30W, the backoff is 6dB, and the power ratio of the carrier amplifier to the peak amplifier is 1: 1, namely the grid width of the two dies is consistent, each die outputs more than 15W of power, so that the die selects the die with the grid width of 4 mm. And the GaN tube core has higher efficiency, so that the later stage selects a tube core with the gate width of 6mm for design. 30dB gain needs two-stage power amplifier cascade to realize, calculates according to single-stage power amplifier 15dB gain, and preceding stage power amplifier reaches that 2W should satisfy the requirement, therefore selects the die of 0.5mm grid width as the preceding stage.
Second, obtaining the die impedance
And introducing a tube core and an IPD model into ads software, setting the gate width of the tube core to be 4mm, and setting the single finger gate width of the tube core to be 250 mu m considering that the working frequency is 4.8-5 GHz.
2.1 static operating Point acquisition
Performing dc offset simulation on the set post-stage dies (carrier amplifier die and peak amplifier die) in ads software to obtain the simulation result shown in fig. 4, and performing gate offset V from top to bottom corresponding to the curveGSAre respectively-1.6V, -1.7V, -1.8V, -1.9V, -2.0V, -2.1V, -2.2V, -2.3V, -2.4V, -2.5V and-2.6V, and the saturated drain current I can be seenDSSAbout 0.6A. The working state of the carrier amplifier is AB, so that the static working point is selected as IDSS0.3A, a corresponding gate bias V can be obtainedGS-2.3V; the working state of the peak amplifier is C type, so that the static working point is selected to be in a pinch-off state, and the corresponding grid bias V can be obtainedGS＝-5V。
Because the die processes are consistent, the previous-stage die can also select the working point for simulation.
2.2 acquisition of output impedance
LoadPull simulation is carried out on the set back-stage die (carrier amplifier die and peak amplifier die) and the front-stage die in ads software, the direct-current operating point is set according to the value obtained by 2.1, the frequency is set to be 4.9GHz, and the output impedance points of the back-stage die (carrier amplifier die and peak amplifier die) and the front-stage die are obtained and shown in table 1.
TABLE 1 output impedance of the back-level die and the front-level die
| Output impedance | |
| Carrier amplifier die | 6.3-j*8.8 |
| Peak amplifier die | 6-j*8.5 |
| Front level die | 61-j*52 |
2.3 acquisition of input impedance
SourcePull simulation is carried out on the set back-stage die (the carrier amplifier die and the peak amplifier die) and the front-stage die in ads software, the direct-current operating point is set according to the value obtained by 2.1, the output impedance is set to be the impedance in the table 1, the frequency is set to be 4.9GHz, and the input impedance points of the back-stage die (the carrier amplifier die and the peak amplifier die) and the front-stage die are obtained and shown in the table 2.
TABLE 2 input impedance of the back-level die and the front-level die
| Input impedance | |
| Carrier amplifier die | 6-j*3.8 |
| Peak amplifier die | 5.6-j*4.5 |
| Front level die | 20- |
Design of matching circuit
Referring to fig. 1 in combination with fig. 3, the main components of the Doherty power amplifier include a carrier amplifier, a peak amplifier, a transmission cancellation line, a phase compensation line, a power divider, and an impedance transformation line, where the carrier amplifier is in an AB class operating state, the peak amplifier is in a C class operating state, and the transmission cancellation line and the phase compensation line are microstrip lines with 50 ohm characteristic impedance for adjusting the output impedance and phase of the amplifier.
When the Doherty power amplifier is operated, there are mainly two operating states: a saturation state and a back-off state. In a saturation state, the carrier amplifier and the peak amplifier both work normally, the impedance is 50 ohms when viewed from the position R1 to two sides, the impedance is converted into 50 ohms through an impedance conversion line after being combined, and the impedances at the positions R2 and R3 are also 50 ohms. In a backspacing state, the peak amplifier is in a pinch-off state due to the direct-current operating point, and the R1 is high impedance seen by the peak amplifier and is approximately equal to non-conduction; when looking into the carrier amplifier, 50/2-25 ohm is obtained, and the impedance at the position R2 is high impedance due to transmission cancellation lines, so that the working efficiency of the carrier amplifier in the backspacing process is improved.
3.1 output matching
The frequency band of the power amplifier is narrow, and the output impedance of the front-stage and rear-stage dies is relatively high, so that the output matching circuits (the first output matching circuit, the second output matching circuit and the third output matching circuit) of the dies all adopt a topological structure of L1 (series connection) -C1 (parallel connection), and a schematic diagram is shown in fig. 5, wherein the inductance L is not easy to realize in a winding mode, and the power amplifier is replaced by a microstrip line. Two ends of the inductor L1 are respectively connected between the first port T1 and the second port T2, two ends of the capacitor C1 are respectively connected between the second port T2 and GND, the first port T1 is a port connected to the die, and the second port T2 is a port connected to a later-stage circuit.
The die output matching circuit is simulated and optimized to obtain the simulation results as shown in fig. 6a-6c, the insertion loss of the output matching of the carrier amplifier die and the peak amplifier die is within 0.1dB, and the insertion loss of the output matching of the previous-stage die is within 0.2 dB.
3.2 input matching
Also, since the frequency band of the power amplifier is narrow and the input impedance of the front-stage die and the rear-stage die is relatively high, the input matching circuits (the first input matching circuit, the second input matching circuit, and the third input matching circuit) also adopt an L2 (series) -C2 (parallel) topology, and the schematic diagram is shown in fig. 7. Two ends of the inductor L2 are connected between the third port T3 and the fourth port T4, respectively, two ends of the capacitor C2 are connected between the third port T3 and GND, respectively, the third port T3 is a port connected to a previous stage circuit, and the fourth port T4 is a port connected to a die.
The input matching circuit is simulated and optimized to obtain the simulation results as shown in fig. 8a-8c, and the insertion loss of the input matching of the carrier amplifier die, the peak amplifier die and the front-stage die is within 0.1 dB.
3.3 design of Transmission cancellation line
a design of first transmission cancellation line (carrier transmission cancellation line)
In designing the first transmission cancellation line, the change of the output impedance of the carrier amplifier in the saturation state and the back-off state is mainly considered, namely, the impedance at R1 (i.e., at T6) is 50 ohms in the saturation state, and the impedance at R1 (i.e., at T6) is 25 ohms in the back-off state. Fig. 9 is a simulation schematic diagram of the first transmission cancellation line, where Z1 is a matching impedance of the amplifier power in saturation, Z2 is a matching impedance of the amplifier efficiency in backoff, both the inductor L3 and the inductor L4 are 50 ohm lines, and are connected between the fifth port T5 and the sixth port T6, the output impedance in backoff is adjusted by L3, and L4 is fixed to 90 ° to perform high-low impedance conversion.
b design of second Transmission cancellation line (Peak Transmission cancellation line)
When designing the second transmission cancellation line, the change of the output impedance of the peak amplifier in the saturation state and the back-off state is also mainly considered, namely, the impedance at R1 (i.e. at T8) in the saturation state is 50 ohms, and the impedance at R1 (i.e. at T8) in the back-off state is high impedance which is similar to an open circuit. Fig. 10 is a simulation diagram of a second transmission cancellation line, where Z3 is the matched impedance of the amplifier power in saturation, Z4 is the matched impedance of the amplifier efficiency in backoff, and the inductor L5 is a 50 ohm line connected between the seventh port T7 and the eighth port T8.
On the basis, the phase of the carrier amplifier is consistent in a saturation state, and the synthesis efficiency is improved as much as possible.
3.4 design of bias Circuit
In the radio frequency circuit, the bias circuit plays a role of supplying power to active devices (a front-stage die and a rear-stage die), and radio frequency signals of an operating frequency band need to be isolated. The design of the bias circuit belongs to the prior art, and is not described in detail here.
Layout design
4.1 layout Generation
Parameters obtained according to the schematic diagram are converted into an IPD layout for the preceding-stage input matching circuit, the inter-stage matching circuit and the subsequent-stage output matching circuit respectively, and the converted layout is shown in FIG. 11.
4.2 layout simulation
The layout and the set die are simulated in ads software, so that the output power in a saturation state, the working efficiency in a fallback state, and the gain in the fallback state can be obtained, which are shown in fig. 12 to 14, respectively.
From the simulation result of the layout, the working frequency band of the Doherty power amplifier is within 4.8-5 GHz, the power gain Gp is more than or equal to 25dB, the peak output power Psat is more than or equal to 45dBm (30W), and the working efficiency DE when the Doherty power amplifier backs off 6dB is more than or equal to 40%. Compared with the GaAs HBT amplifier which is applied more at present, the GaAs HBT power amplifier generally has the maximum output power of only 8W, and the working efficiency of the GaAs HBT power amplifier when the power amplifier backs by 8dB is generally 25% -30%, so that the power amplifier has remarkable advantages in performance.
Meanwhile, the size of the power amplifier can be controlled within 8mm by 4mm, and compared with the traditional discrete amplifier, the power amplifier has remarkable improvement in power magnitude. Meanwhile, as the matching circuit is arranged in the package, application personnel saves debugging work, and the method is more convenient and flexible.
In the invention, the active region adopts a GaN power tube core, and the passive circuit is realized by an IPD circuit. The IPD circuit can be topologically equivalent to a single chip circuit due to a multilayer structure, but the price is far lower than the tape-out cost of a GaN chip, the difference is that parasitic effect and the like can be brought during assembly, but the effect can be ignored or overcome in the working frequency band of a 5G macro base station or a small base station, so that a power amplifier with similar performance and lower cost can be realized.
According to the technical scheme, the invention has the following advantages:
the Doherty power amplifier has the advantages of large output power and high back-off efficiency, and has the characteristics of low cost and small volume.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it is to be understood that all embodiments may be combined as appropriate by one of ordinary skill in the art to form other embodiments as will be apparent to those of skill in the art from the description herein.
Claims (10)
1. The Doherty power amplifier is characterized by comprising an input unit, a front-stage tube core, an inter-stage unit, a rear-stage tube core and an output unit, wherein the rear-stage tube core comprises a carrier amplifier tube core and a peak amplifier tube core;
the input unit comprises a first input matching circuit, and the first input matching circuit is used for matching the input impedance of the previous-stage die to a first impedance threshold value;
the interstage unit comprises a first output matching circuit, a second input matching circuit and a third input matching circuit, wherein the first output matching circuit is used for matching the output impedance of a preceding stage die to a first impedance threshold value, the second input matching circuit is used for matching the input impedance of a carrier amplifier die to a second impedance threshold value, and the third input matching circuit is used for matching the input impedance of a peak amplifier die to a third impedance threshold value;
the output unit comprises a second output matching circuit and a third output matching circuit, the second output matching circuit is used for matching the output impedance of the carrier amplifier tube core to a second impedance threshold value, and the third output matching circuit is used for matching the output impedance of the peak amplifier tube core to a third impedance threshold value.
2. The Doherty power amplifier of claim 1 wherein the inter-stage unit further comprises a power divider and a phase compensation line, the input of the power divider is connected to the first output matching circuit, the first output is directly connected to the second input matching circuit, and the second output is connected to the third input matching circuit through the phase tuning line.
3. The Doherty power amplifier of claim 2 wherein the output unit further comprises a first transmission cancellation line, a second transmission cancellation line and an impedance transformation line, the first transmission cancellation line being connected to the second output matching circuit, the second transmission cancellation line being connected to the third output matching circuit, the impedance transformation line being connected to the first transmission cancellation line and the second transmission cancellation line.
4. The Doherty power amplifier of claim 2 wherein the first input matching circuit, the second input matching circuit, the third input matching circuit, the first output matching circuit, the second output matching circuit and the third output matching circuit are all topologies comprising series inductors and parallel capacitors for adjusting input impedance or output impedance, wherein the inductors are formed by microstrip line windings.
5. The Doherty power amplifier of claim 3 wherein the first transmission cancellation line and the second transmission cancellation line are both topologies containing a plurality of series inductors for adjusting output impedance and phase, wherein the inductors are formed by microstrip line windings.
6. The Doherty power amplifier of claim 3 wherein the carrier amplifier is in class AB operation, the peaking amplifier is in class C operation, and the Doherty power amplifier includes a saturation state and a back-off state, and wherein:
in a saturation state, the carrier amplifier and the peak amplifier work normally, and the matching impedance of the first transmission cancellation line and the matching impedance of the second transmission cancellation line are both a first rated impedance value;
in a backspacing state, the carrier amplifier normally works, the peak amplifier does not work, the matching impedance of the first transmission cancellation line and the matching impedance of the second transmission cancellation line are respectively a second rated impedance value and an open-circuit high impedance value, and the second rated impedance value is 1/2 of the first rated impedance value.
7. The Doherty power amplifier of claim 1, further comprising a plurality of bias circuits for powering the front-stage die and the back-stage die and isolating rf signals in an operating band.
8. The Doherty power amplifier of claim 1, wherein the input unit, the inter-stage unit and the output unit are integrated passive devices formed based on IPD technology, the integrated passive devices comprise a substrate and a plurality of dielectric layers and metal layers positioned on the surface of the substrate, and the metal layers are connected with each other through metallized through holes.
9. The Doherty power amplifier of claim 1, wherein the operating frequency band of the Doherty power amplifier is 4.8-5 GHz, the power gain Gp is greater than or equal to 25dB, the peak output power Psat is greater than or equal to 45dBm, and the operating efficiency DE at 6dB backoff is greater than or equal to 40%.
10. The Doherty power amplifier of claim 1 wherein the front-stage die and the back-stage die are GaN power dies; and/or the first impedance threshold, the second impedance threshold, and the third impedance threshold are equal.
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| CN202210320427.4A CN114629443A (en) | 2022-03-29 | 2022-03-29 | Doherty power amplifier |
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| CN202210320427.4A CN114629443A (en) | 2022-03-29 | 2022-03-29 | Doherty power amplifier |
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