CN114629098B - Solid-state switch based on sectional type gapless lightning arrester and utilization rate improving method thereof - Google Patents
Solid-state switch based on sectional type gapless lightning arrester and utilization rate improving method thereof Download PDFInfo
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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Abstract
The invention belongs to the field of high-efficiency solid-state switches, and particularly relates to a solid-state switch based on a sectional type gapless arrester and a utilization rate improving method thereof, aiming at solving the problem of how to improve the utilization rate of devices through the gapless arrester on the premise of low cost. The invention includes: the main branch circuit is composed of a semiconductor component T0 and realizes the current circulation of the system at two sides; the energy absorption branch circuit is composed of an arrester MOV1, an arrester MOV2 and a semiconductor component S1, the arrester MOV1 and the arrester MOV2 are connected in series, the semiconductor component S1 is connected in parallel with two ends of the arrester MOV1, and the energy absorption branch circuit is used for absorbing fault current and energy when a system fails; the buffer branch buffers voltage and current stress to which the semiconductor component is subjected during switching. The invention effectively improves the voltage utilization rate of the main branch device of the solid-state switch and ensures the scene life of the solid-state switch on the premise of only increasing a little volume and cost.
Description
Technical Field
The invention belongs to the field of high-efficiency solid-state switches, and particularly relates to a solid-state switch based on a sectional type gapless arrester and a utilization rate improving method thereof.
Background
The mechanical switch is not suitable for a future smart grid due to the defects of electric arcs, inconsistent characteristics, low breaking speed, short service life and the like existing in the breaking process, and a Solid State Circuit Breaker (SSCB) formed based on high-power electronic devices has the advantages of high breaking speed (microsecond level), accurately controllable switching time, no electric arc generation in the breaking process and the like, and is a future trend of direct-current fault breaking. At present, solid-state circuit breaker solutions implemented on the basis of different semiconductor devices have been extensively studied and partially applied.
FIG. 1 shows a characteristic curve diagram of a lightning arrester, V res Representing the transient maximum voltage, V, of the arrester clamp Clamping voltage, V, representative of lightning arrester ref Reference voltage, V, representing lightning arrester rat The system rated Voltage of the lightning arrester is represented, small current area is a current cut-off region, voltage limiting area represents a Voltage clamping region, overload area represents a breakdown region, and the utilization rate of the device is lower in two points: firstly, the maximum voltage of the device is usually greater than Vres of the lightning arrester, when the device is turned off, the maximum value of fault current flows through the lightning arrester, so that the instantaneous voltage of the lightning arrester is higher, although the instantaneous maximum voltage value of a single lightning arrester can be improved to a certain extent by connecting the lightning arresters in parallel, the cost and the volume are obviously increased by adding the lightning arrester; secondly, the voltage VDC = Vrat of the system where the solid-state switch is located, and Vrat needs to be smaller than Vref (50% -90%), otherwise, when the device is turned off, the system voltage VDC is applied to the lightning arrester, the service life of the lightning arrester is affected, and the leakage current is large in a static state. The non-linear nature of the arresters therefore leads to a generally poor utilization of the components in solid state circuit breakers, typically only 40% -50%. For example, 4.5kV devices are generally used in dc power networks with 2kV voltage class, while for 1kV/1MW application scenarios, 2.5kV devices are required.
Some techniques improve the characteristic curve of a lightning arrester (MOV) by adopting other methods, mainly including: (1) Transient Voltage Suppression (TVS) diodes are used instead of MOVs, but this solution is particularly costly; (2) This approach multiplies the system size and cost by paralleling multiple MOVs so that the maximum current of a single MOV is reduced, thereby reducing the value of Vres; (3) The characteristic curve of the arrester (MOV) is improved by using the gapped arrester and the gapless arrester in series in a mixed mode [1], but the gapped arrester is large in size, discrete in characteristics and uncertain in service life.
The following documents are background information related to the present invention:
[1] zhang Yu, liu Ke Xin, zi Jie, ma Hui Yuan, high voltage solid semiconductor switch device and the method and application for improving the voltage utilization rate, 2021-08-24, CN113783173A.
Disclosure of Invention
In order to solve the above problems in the prior art, namely how to realize the improvement of the utilization rate of the device through the gapless arrester on the premise of low cost, the invention provides a solid-state switch based on a sectional type gapless arrester, which comprises a main branch, an energy absorption branch and a buffer branch;
the main branch comprises a semiconductor component T0 used for realizing current circulation in systems on two sides of the main branch;
the energy absorption branch comprises an arrester MOV1, an arrester MOV2 and a semiconductor component S1 and is used for absorbing fault current and energy when a system is in fault;
the buffer branch is used for buffering voltage and current stress to which the semiconductor component is subjected during switching.
In some preferred embodiments, the solid-state switch has a connection relationship of:
the first connection end of the semiconductor component T0 is connected to the connection point a, and the second connection end of the semiconductor component T0 is connected to the connection point b;
the first connection end of the arrester MOV1 and the first connection end of the semiconductor component S1 are connected to a connection point a, the second connection end of the arrester MOV1, the second connection end of the semiconductor component S1 and the first connection end of the arrester MOV2 are connected to a connection point c, and the second connection end of the arrester MOV2 is connected to a connection point b;
the first connecting end of the buffering branch is connected to the connecting point a, and the second connecting end of the buffering branch is connected to the connecting point b.
In some preferred embodiments, the semiconductor device T0 is a unidirectional topology formed by connecting one or more semi-controlled devices or fully-controlled devices in series, or a bidirectional topology formed by connecting one or more semi-controlled device groups or fully-controlled device groups in series;
the half-control device group is formed by reversely connecting two half-control devices in parallel, and the full-control device group is formed by reversely connecting two full-control devices in series.
In some preferred embodiments, when the semiconductor device T0 is a unidirectional topology, the semiconductor device S1 is a unidirectional topology composed of one or more semi-controlled devices or fully-controlled devices connected in series; when the semiconductor component T0 is in a bidirectional topological structure, the semiconductor component S1 is in the bidirectional topological structure formed by connecting one or more half-control component groups or full-control component groups in series;
the semi-controlled device group is formed by reversely connecting two semi-controlled devices in parallel, and the fully-controlled device group is formed by reversely connecting two fully-controlled devices in series.
In some preferred embodiments, the buffer branch is a capacitive buffer circuit C, a capacitive-resistor series buffer circuit RC, or a resistance-capacitor diode buffer circuit RCD.
In another aspect of the present invention, a method for increasing the utilization rate of a semiconductor device of a solid state switch based on a segmented gapless arrester is provided, based on the solid state switch based on the segmented gapless arrester, the method includes:
step S10, when the semiconductor component T0 of the main branch is in an off stable state, and the semiconductor component S1 is in an off state, leakage current flows through an arrester MOV1 and an arrester MOV2, and the arrester MOV1 and the arrester MOV2 jointly bear the voltage applied to two ends of the device by the system;
step S20, when the semiconductor component T0 of the main branch circuit is conducted, conducting current directly flows through the semiconductor component T0, and the whole solid-state switch does not bear system voltage;
step S30, when the semiconductor component T0 of the main branch circuit needs to be converted into a transient state from a conducting state to a switching-off state, after the semiconductor component S1 is switched on, the semiconductor component T0 is switched off, and conducting current flows through the semiconductor component S1 and the arrester MOV2;
step S40, the voltage at the two ends of the MOV2 of the arrester is rapidly increased, the current energy on the system inductor is absorbed, and the current of the MOV2 of the arrester is decreased;
and step S50, when the current of the arrester MOV2 is reduced to 0, the semiconductor component S1 is closed, the semiconductor component T0 is recovered to be in a turn-off stable state, and the arrester MOV1 and the arrester MOV2 jointly bear the voltage applied to two ends of the device by the system.
In some preferred embodiments, if the semiconductor device S1 is a half-controlled device, the semiconductor device S1 automatically turns off when the current of the arrester MOV2 decreases to 0; if the semiconductor device S1 is a fully controlled device, the semiconductor device S1 is turned off under the control of the control circuit.
In a third aspect of the present invention, an apparatus is provided, which includes:
at least one processor; and
a memory communicatively coupled to at least one of the processors; wherein the content of the first and second substances,
the memory stores instructions executable by the processor for execution by the processor to implement the above-described method of semiconductor device utilization enhancement for a segmented gapless arrester-based solid state switch.
In a fourth aspect of the present invention, a computer readable storage medium is provided, which stores computer instructions for execution by the computer to implement the above-mentioned semiconductor device utilization improvement method of the segmented gapless arrester-based solid-state switch.
The invention has the beneficial effects that:
(1) The solid-state switch based on the sectional type gapless arrester adopts the gapless arrester, effectively improves the voltage utilization rate of a main branch device of the solid-state switch on the premise of only increasing little volume and cost and ensures the scene service life of the solid-state switch in order to avoid the defects that the gapless arrester has discrete characteristics and large volume and is used for indefinite scene service life of the solid-state switch.
(2) According to the solid-state switch based on the sectional type gapless arrester, when a main branch semiconductor assembly T0 is switched off in a steady state, the arrester MOV1 and the arrester MOV2 of the energy absorption branch are jointly subjected to pressure bearing, and when the main branch semiconductor assembly T0 is in a transient state, only the arrester MOV2 of the energy absorption branch absorbs residual energy of system inductance, so that the ratio of transient peak voltage to steady-state voltage is lower, and the voltage utilization rate of the main branch is higher.
(3) The invention is based on the solid-state switch of the sectional type gapless arrester, the arrester MOV1 of the energy absorption branch only bears the pressure, does not absorb the energy, the volume can be very small. Compared with the main branch semiconductor assembly T0, the energy absorption branch semiconductor assembly S1 has low voltage resistance, only needs to flow large current for a short time, does not need a heat dissipation device, has no requirement on loss, and has small volume and low cost. Compare traditional solid state switch based on single arrester MOV1, this application only needs to increase that the volume is less, with lower costs and arrester MOV2 of arrester MOV1 series connection, parallelly connected semiconductor component on arrester MOV1 simultaneously, control arrester MOV1 and arrester MOV2 in the different stages of system alone or collaborative work, under small, with low costs prerequisite, effectively promoted solid state switch's main branch device's voltage utilization ratio.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a characteristic graph of a lightning arrester;
fig. 2 is a schematic structural view of a solid-state switch based on a sectional type gapless lightning arrester according to the invention;
FIG. 3 is a schematic view of several bi-directional solid state switches of an embodiment of the sectional type gapless arrester based solid state switch of the present invention;
FIG. 4 is a schematic diagram of a multi-device series and series-parallel solid state switch according to an embodiment of the present invention based on a segmented gapless arrester solid state switch;
fig. 5 is a comparison of the present invention and the semiconductor device utilization improvement method of the conventional art for one embodiment of the solid state switch based on the sectional type gapless arrester of the present invention.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.
It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
The invention relates to a solid-state switch based on a sectional type gapless lightning arrester, which comprises a main branch, an energy absorption branch and a buffering branch;
the main branch comprises a semiconductor component T0 used for realizing current circulation in systems on two sides of the main branch;
the energy absorption branch comprises an arrester MOV1, an arrester MOV2 and a semiconductor component S1, and is used for absorbing fault current and energy when a system is in fault;
the buffer branch is used for buffering voltage and current stress to which the semiconductor component is subjected during switching.
In order to more clearly describe the solid-state switch based on the sectional type gapless arrester, the modules in the embodiment of the invention are described in detail with reference to fig. 2.
The solid-state switch based on the sectional type gapless lightning arrester comprises a main branch, an energy absorption branch and a buffering branch, wherein the modules are described in detail as follows:
the main branch comprises a semiconductor component T0 for enabling current flow in the system on both sides of the main branch.
The first connection terminal of the semiconductor device T0 is connected to the connection point a, and the second connection terminal of the semiconductor device T0 is connected to the connection point b.
The semiconductor component T0 is a unidirectional topological structure formed by connecting more than one semi-control type device or fully-control type device in series, or a bidirectional topological structure formed by connecting more than one semi-control type device group or fully-control type device group in series.
The energy absorption branch comprises an arrester MOV1, an arrester MOV2 and a semiconductor component S1 and is used for absorbing fault current and energy when a system is in fault.
The first connection end of the arrester MOV1 and the first connection end of the semiconductor component S1 are connected to the connection point a, the second connection end of the arrester MOV1, the second connection end of the semiconductor component S1 and the first connection end of the arrester MOV2 are connected to the connection point c, and the second connection end of the arrester MOV2 is connected to the connection point b.
When the semiconductor component T0 is in a unidirectional topological structure, the semiconductor component S1 is in a unidirectional topological structure formed by connecting more than one semi-control type device or fully-control type device in series; when the semiconductor device T0 is a bidirectional topology, the semiconductor device S1 is a bidirectional topology formed by connecting one or more half-controlled device groups or full-controlled device groups in series.
Fig. 2 shows a schematic diagram of a solid-state switch structure when a semiconductor component T0 and a semiconductor component S1 are in a unidirectional topology structure, as shown in fig. 3, several schematic diagrams of a bidirectional solid-state switch structure of an embodiment of the solid-state switch based on the sectional type gapless arrester of the present invention are shown, S11 and S12 in fig. 3 (a) are connected in reverse in parallel to form the semiconductor component S1, T01 and T02 are connected in reverse in series to form the semiconductor component T0, and T01 and T02 are respectively formed by an IGBT and an anti-parallel diode thereof, S11 and S12 in fig. 3 (b) are connected in reverse in parallel to form the semiconductor component S1, and T01 and T02 are connected in reverse in parallel to form the semiconductor component T0, and fig. 3 (c) and fig. 3 (d) show two structures which can be used as the semiconductor component T0 or the semiconductor component S1, respectively. In other embodiments, the semiconductor device may be adjusted to other structures as needed, and the present invention is not described in detail herein.
The semi-controlled device group in the semiconductor component T0 and the semi-controlled device group in the semiconductor component S1 are formed by reversely connecting two semi-controlled devices in parallel, and the fully-controlled device group is formed by reversely connecting two fully-controlled devices in series.
The buffer branch is used for buffering voltage and current stress to which the semiconductor component is subjected during switching.
The first connecting end of the buffering branch is connected to the connecting point a, and the second connecting end of the buffering branch is connected to the connecting point b.
The buffer branch circuit is a capacitor buffer circuit C, or a capacitor resistor series buffer circuit RC, or a resistor-capacitor diode buffer circuit RCD.
The semiconductor module T0 and the semiconductor module S1 may be a hybrid topology in which a plurality of devices are connected in series, in addition to the unidirectional topology and the bidirectional topology described above.
Referring to fig. 4, a schematic diagram of a multi-device serial and parallel solid-state switch structure of an embodiment of the solid-state switch based on the sectional gapless arrester of the present invention is shown, wherein a semiconductor device S1 is composed of S11, S12, \8230;, S1n in series, and illustrated by taking S11 as an example, the structures thereof are S111 and S121 in reverse parallel, and by analogy, S12, \8230;, S1n structures, a semiconductor device T0 is composed of T01, \8230;, T0n, T0x in series, and illustrated by taking T01 as an example, the structures thereof are T011 and T021 in reverse parallel, and by analogy, T02, \\,8230, T0n structures, and T0x is composed of T0x1 and T0x2 in reverse series, and T0x1 and T0x2 are respectively composed of an IGBT and an anti-parallel diode thereof. In other embodiments, the semiconductor device may be adjusted to other structures as needed, and the present invention is not described in detail herein.
The method for improving the utilization rate of the semiconductor device of the solid-state switch based on the sectional type gapless arrester of the second embodiment of the invention is shown in fig. 5, which is a comparison graph of the invention based on one embodiment of the solid-state switch based on the sectional type gapless arrester of the invention and the method for improving the utilization rate of the semiconductor device of the prior art, and the method based on the solid-state switch based on the sectional type gapless arrester comprises the following steps:
step S10, when the semiconductor component T0 of the main branch is in an off stable state, and the semiconductor component S1 is in an off state, leakage current flows through an arrester MOV1 and an arrester MOV2, and the arrester MOV1 and the arrester MOV2 jointly bear the voltage applied to two ends of the device by the system;
step S20, when the semiconductor component T0 of the main branch circuit is conducted, conducting current directly flows through the semiconductor component T0, and the whole solid-state switch does not bear system voltage;
step S30, when the semiconductor component T0 of the main branch circuit needs to be converted into a transient state from a conducting state to a switching-off state, after the semiconductor component S1 is switched on, the semiconductor component T0 is switched off, and conducting current flows through the semiconductor component S1 and the arrester MOV2;
step S40, rapidly increasing the voltage at two ends of the MOV2 of the arrester, absorbing the current energy on the system inductor, and reducing the current of the MOV2 of the arrester;
and step S50, when the current of the arrester MOV2 is reduced to 0, the semiconductor component S1 is closed, the semiconductor component T0 is recovered to be in a turn-off stable state, and the arrester MOV1 and the arrester MOV2 jointly bear the voltage applied to two ends of the device by the system.
When the current of the arrester MOV2 is reduced to 0, the state of the semiconductor component S1 adopts different control methods according to the types of the components:
if the semiconductor component S1 is a semi-controlled device, the semiconductor component S1 is automatically closed when the current of the MOV2 of the arrester is reduced to 0; if the semiconductor device S1 is a fully controlled device, the semiconductor device S1 is turned off under the control of the control circuit.
Comparing the characteristic curves of MOV in fig. 5, it can be seen that, under the condition that the transient peak Voltage (VMAX) is the same, the same MOV1 is needed to be used in the present invention scheme and the conventional scheme, but when the system is in the off-steady state, the system voltage of the present invention scheme is shared by MOV1 and MOV2 (VMOV 1+ VMOV 2), which is much greater than the system voltage VDC of the conventional scheme, and is increased by a lot compared with the original VDC/VMAX ratio, thereby improving the utilization rate of the device, and the arrester MOV1 only bears pressure, does not absorb energy, and has very small volume and low cost.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process and related descriptions of the method described above may refer to the corresponding process in the foregoing system embodiment, and are not described herein again.
It should be noted that, the solid-state switch based on the segmented gapless arrester and the utilization rate improving method thereof provided by the above embodiments are only exemplified by the division of the above functional modules, and in practical applications, the above functions may be allocated to different functional modules according to needs, that is, the modules or steps in the embodiments of the present invention are further decomposed or combined, for example, the modules in the embodiments may be combined into one module, or may be further split into a plurality of sub-modules, so as to complete all or part of the above described functions. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not to be construed as unduly limiting the present invention.
An apparatus of a third embodiment of the invention comprises:
at least one processor; and
a memory communicatively coupled to at least one of the processors; wherein, the first and the second end of the pipe are connected with each other,
the memory stores instructions executable by the processor for execution by the processor to implement the semiconductor device utilization boosting method for a segmented gapless arrester-based solid state switch described above.
A computer readable storage medium of a fourth embodiment of the present invention stores computer instructions for execution by the computer to implement the above-mentioned method for improving the utilization rate of semiconductor devices of a solid state switch based on a segmented arrester without gap.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes and related descriptions of the storage device and the processing device described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Those of skill in the art would appreciate that the various illustrative modules, method steps, and modules described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that programs corresponding to the software modules, method steps may be located in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. To clearly illustrate this interchangeability of electronic hardware and software, various illustrative components and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as electronic hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing or implying a particular order or sequence.
The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is apparent to those skilled in the art that the scope of the present invention is not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can be within the protection scope of the invention.
Claims (6)
1. A solid-state switch based on a sectional type gapless arrester is characterized by comprising a main branch, an energy absorption branch and a buffer branch;
the main branch comprises a semiconductor component T0 used for realizing current circulation in systems on two sides of the main branch;
the energy absorption branch comprises an arrester MOV1, an arrester MOV2 and a semiconductor component S1, and is used for absorbing fault current and energy when a system is in fault;
the buffer branch is used for buffering voltage and current stress suffered by the semiconductor component during switching;
the solid-state switch based on the sectional type gapless arrester comprises the following semiconductor devices, wherein the utilization rate of the semiconductor devices is improved by the following method:
step S10, when the semiconductor component T0 of the main branch is in an off stable state, and the semiconductor component S1 is in an off state, leakage current flows through an arrester MOV1 and an arrester MOV2, and the arrester MOV1 and the arrester MOV2 jointly bear the voltage applied to two ends of the device by the system;
step S20, when the semiconductor component T0 of the main branch circuit is conducted, conducting current directly flows through the semiconductor component T0, and the whole solid-state switch does not bear system voltage;
step S30, when the semiconductor component T0 of the main branch needs to be converted into a transient state from a conduction state to an off state, after the semiconductor component S1 is turned on, the semiconductor component T0 is turned off, and conduction current flows through the semiconductor component S1 and an arrester MOV2;
step S40, the voltage at the two ends of the MOV2 of the arrester is rapidly increased, the current energy on the system inductor is absorbed, and the current of the MOV2 of the arrester is decreased;
step S50, when the current of the arrester MOV2 is reduced to 0, the semiconductor component S1 is closed, the semiconductor component T0 is recovered to be in a turn-off stable state, and the arrester MOV1 and the arrester MOV2 jointly bear the voltage applied to the two ends of the device by the system;
wherein, arrester MOV1 bears the voltage that the system applyed at the device both ends jointly with arrester MOV2, increases the ratio of VDC/VMAX, and arrester MOV1 does not absorb the energy, promotes semiconductor device's utilization ratio, and VDC is the system voltage, and VMAX is the voltage peak value.
2. The segmented gapless lightning arrester-based solid state switch of claim 1 wherein the solid state switch is connected in a relationship of:
the first connecting end of the semiconductor component T0 is connected to the connecting point a, and the second connecting end of the semiconductor component T0 is connected to the connecting point b;
the first connection end of the arrester MOV1 and the first connection end of the semiconductor component S1 are connected to a connection point a, the second connection end of the arrester MOV1, the second connection end of the semiconductor component S1 and the first connection end of the arrester MOV2 are connected to a connection point c, and the second connection end of the arrester MOV2 is connected to a connection point b;
the first connecting end of the buffering branch is connected to the connecting point a, and the second connecting end of the buffering branch is connected to the connecting point b.
3. The segmented gapless arrester-based solid state switch according to claim 1 or 2, wherein the semiconductor assembly T0 is a unidirectional topology consisting of one or more semi-controlled devices or fully-controlled devices connected in series, or a bidirectional topology consisting of one or more semi-controlled device groups or fully-controlled device groups connected in series;
the half-control device group is formed by reversely connecting two half-control devices in parallel, and the full-control device group is formed by reversely connecting two full-control devices in series.
4. The segmented gapless arrester-based solid state switch of claim 3 wherein when the semiconductor assembly T0 is a unidirectional topology, the semiconductor assembly S1 is a unidirectional topology consisting of one or more semi-controlled devices or fully-controlled devices connected in series; when the semiconductor component T0 is a bidirectional topological structure, the semiconductor component S1 is a bidirectional topological structure formed by connecting one or more half-control-type device groups or full-control-type device groups in series;
the half-control device group is formed by reversely connecting two half-control devices in parallel, and the full-control device group is formed by reversely connecting two full-control devices in series.
5. The segmented gapless lightning arrester-based solid state switch according to claim 1 or 2, wherein the snubber branch is a capacitive snubber circuit C, or a capacitive-resistive-series snubber circuit RC, or a resistive-capacitive-diode snubber circuit RCD.
6. The segmented gapless arrester based solid state switch according to claim 1, wherein if the semiconductor component S1 is a semi-controlled device, the semiconductor component S1 is automatically turned off when the arrester MOV2 current drops to 0; if the semiconductor device S1 is a fully controlled device, the semiconductor device S1 is turned off under the control of the control circuit.
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