CN114615445B

CN114615445B - Phototransistor and photosensitive method thereof

Info

Publication number: CN114615445B
Application number: CN202210259636.2A
Authority: CN
Inventors: 张盛东; 彭志超; 廖聪维; 梁键; 邱赫梓; 安军军
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2020-11-05
Filing date: 2020-11-05
Publication date: 2024-05-31
Anticipated expiration: 2040-11-05
Also published as: CN112511769B; CN112511769A; CN114615445A

Abstract

The invention relates to a photoelectric transistor with photoelectric response, which comprises a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer and a top gate electrode which are stacked layer by layer; wherein the active layer comprises a semiconductor material with an optical memory function, and a channel and a source drain region are included in the active layer; wherein during the illumination phase and the integration phase, the bottom gate electrode and the top gate electrode of the phototransistor are at different voltages and the phototransistor is in an off-state operating region; the integration stage at least comprises a first preset time period after exposure is finished; wherein the semiconductor material with the optical memory function comprises a metal oxide semiconductor. The invention also relates to a method for using the double-gate phototransistor for photosensitivity, wherein the active layer material of the double-gate phototransistor comprises a material having an optical memory function. The invention also relates to an image sensor array.

Description

Phototransistor and photosensitive method thereof

Technical Field

The invention relates to the field of photoelectric imaging of display technology, in particular to a photoelectric transistor with photoelectric response.

Background

In recent years, the thin film transistor (Thin Film Transistor, TFT) technology has made tremendous progress. The TFT is very suitable for manufacturing an active matrix flat-panel imager with high performance, low power consumption and low cost due to the characteristics of large-area mass production, array processing and the like. Currently, the mainstream X-ray digital imaging (X-RAY DIGITAL Radiography, X-ray DR) system is mainly divided into two types, i.e., direct type X-ray digital imaging and indirect type X-ray digital imaging. In a typical direct-type X-ray digital imaging scheme, amorphous selenium (Amorphous Selemium, a-Se) is used as a photosensitive unit, and amorphous silicon (Amorphous Silicon, a-Si) TFTs are used to make a switch array for reading photoelectric signals (hereinafter, the detector is referred to as a direct-type a-Se flat panel detector). The working principle is that the incident X-ray makes the selenium layer generate electron hole pairs, and under the action of the externally applied bias electric field, the electron and the hole move in opposite directions to form current, and the stored charge is formed on the node capacitance inside the pixel circuit. Corresponding to the dose of the incident X-ray, each detection pixel has a corresponding stored charge quantity, and the charge quantity of each pixel point can be known through a reading circuit, so that the corresponding X-ray dose of each pixel point is further ascertained. For an indirect X-ray detection system, a PIN photodiode (PIN diode) is used as a photosensitive unit, and a switch array is manufactured by adopting an a-Si TFT to read photoelectric signals. The structure of the indirect X-ray imager comprises a scintillation crystal layer, and an array layer consisting of PIN diodes and a-Si TFTs. The working process is divided into two steps, firstly, X-ray is converted into visible light through a scintillation crystal layer, then the visible light is converted into an electric signal through PIN diode, and the electric signal is read through an a-Si TFT array (hereinafter, the detector is called an indirect a-Si flat panel detector for short). In the two schemes, the direct type a-Se flat panel detector is used for directly detecting the X-ray dose, the a-Se layer and the a-Si TFT layer are of a three-dimensional stacked structure, high voltage of kilovolts is required to be applied when the a-Se layer normally works, and the conditions are severe, so that the direct type a-Se flat panel detector has high requirements on working environment, short service life and high failure rate, and the maintenance cost is far greater than that of an indirect type a-Si flat panel detector. In contrast, indirect a-Si flat panel detectors are used in a wider range of applications.

Whether in a direct or indirect type scheme, high quality flat panel imagers are always independent of TFT technology. With the continuous development of large-area flat-panel imaging panels, the requirements are continuously improved, and the a-Si TFT is not suitable for flat-panel imaging technologies with high resolution, high refresh frame rate and the like. For a direct type a-Se flat panel detector, the normal operation of an a-Si TFT array is not facilitated under the ultra-high voltage working environment, and the principle structure has limitation on the application of TFT technology; in addition, a-Si TFTs have the disadvantages of unstable electrical properties, low mobility and the like, and many performance improvements are limited for indirect a-Si flat panel detectors. First, in terms of technology, a-Si TFT adopts a thin film transistor technology, and two independent and serial technologies are adopted as the manufacturing technology of PIN diode. The special-shaped integrated image sensing panel has the defects of high process complexity, high manufacturing cost, high mass production difficulty, low yield and the like. Second, studies have shown that although the presence of an indirect a-Si flat panel detector, the presence of an intermediate layer scintillation crystal, loses some of the detection quantum efficiency (Detection of Quantum Efficiency, DQE), the limit DQE of a direct a-Se flat panel detector is still lower than that of an indirect a-Si flat panel detector in general, and there is also an increase in DQE of a photosensor a-Se or PIN diode that might attempt to break through from a new photosensor, since the level of the direct a-Se flat panel detector DQE depends on the ability of the a-Se layer to generate charge. Furthermore, the mobility of a-Si TFTs is relatively low, on the order of 1 cm ²/(V.s), and a-Si TFTs are required to have a large size (i.e., a large width-to-length ratio W/L value of the device) in order to maintain a certain driving capability. The larger size of the a-Si TFT thus limits further improvement in the spatial resolution of the X-ray imaging panel. For example, the difficulty of a single pixel area of a conventional indirect a-Si flat panel detector is higher than 100 μm by 100 μm. As the spatial resolution increases, the number of rows of the panel increases, and the readout time of each row needs to be shortened at a certain refresh frame rate. However, low a-Si TFT mobility also makes it more and more difficult to shorten the readout time per row, and thus the refresh frame rate (> 30 Hz) is difficult to increase.

As the metal oxide thin film transistor (Metallic Oxide Thin Film Transistor, MOTFT) is being studied intensively and the low temperature polysilicon oxide (Low Temperature Polycrystalline Oxide, LTPO) process level is being greatly improved, related studies have found and experimental tests show that MOTFT with higher mobility has the same better photoelectric response characteristics. Here, the more typical metal Oxide thin film transistor includes amorphous indium gallium Zinc Oxide (Amorphous InGaZnO, a-IGZO), zinc Tin Oxide (ZTO), and the like. And MOTFT itself is based on the same planar thin film process as the readout array TFT, so that the MOTFT technology has the possibility of manufacturing a photoelectric sensor, and the MOTFT technology and the readout array TFT are combined to form a set of flat panel detector with all TFTs, so that the MOTFT has feasibility and development potential. Compared with the indirect a-Si flat panel detection technology, the MOTFT is adopted as the photoelectric sensor, so that the process complexity, difficulty and cost are reduced, and the yield is improved. It should be noted, however, that if a thin film transistor is used to fabricate the photoelectric converter, several problems may be introduced.

The first problem is that the thin film transistor has three PINs compared to the above-mentioned a-Se or PIN diode, and a single pixel needs to be introduced with one more signal line compared to the former two. Considering the layout, the increase of pixel signal lines can further reduce the effective utilization space of pixel areas, which is not beneficial to the improvement of the spatial resolution of the detector.

The second problem is that the preparation of the photo cell TFT and the readout array TFT is done by the same set of thin film processes, i.e. the preparation process of the photo cell and the readout array is parallel. The photosensitive cell TFT and the readout array TFT are two-dimensional structures in the same plane, and compared with the above conventional scheme, the photosensitive cell a-Se or PIN diode and the readout array TFT are three-dimensional structures stacked one above the other, whether they are indirect or direct. From this point of view, the photo cell TFT as a photoelectric converter cannot completely fill the entire pixel area, and the fill factor is not as high as in the conventional structural scheme.

The third problem is that the MOTFT has a high photo-electric response and at the same time, often has a continuous photoconductive effect (PERSISTENT PHOTOCONDUCTIVITY, PPC), i.e. the response of the photosensor should be quickly restored to the state before receiving the light with the light being removed, and no response is output at the stage after the light is applied. The PPC effect can enable the photosensitive unit to still maintain photoelectric response when receiving illumination at a stage after the illumination is removed. Specifically, taking MOTFT as an example, under the bias of a certain gate electrode and source electrode voltage, when the MOTFT is not exposed, the current between the drain electrode and the source electrode is extremely small, the resistance is extremely large and is approximately turned off at the magnitude of 10 ^-12 A A. When exposed under the bias, the current between the drain electrode and the source electrode is rapidly increased, the current is maintained at the level of 10 ^-6 A, and the resistance is reduced, however, after the illumination is removed, the device is not restored to the state of small current and large resistance immediately before, and the current is continued for a period of time. Therefore, based on the traditional direct a-Se scheme or the indirect a-Si scheme, the photoelectric converter cannot be simply replaced by a-Se or PIN diode to be MOTFT directly, because when the illumination is removed, the PPC effect can continuously change the induced photo-generated charge, the collected photoelectric signals can be influenced by the historical state to cause distortion, and thus the function of the whole pixel circuit is invalid and needs to be redesigned.

In summary, for the photoelectric characteristics of the oxide TFT or the low-temperature polysilicon oxide TFT, a new image sensing pixel circuit and a readout method thereof are needed to be newly conceived, so as to improve the resolution and sensitivity of the flat panel image sensing array, thereby reducing the X-ray irradiation dose or realizing image sensing in the case of lower intensity of input light. However, no pixel circuit or pixel array designed for oxide TFTs is currently available in the prior art.

Disclosure of Invention

The application provides a photoelectric transistor with photoelectric response, which comprises a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer and a top gate electrode which are stacked layer by layer; wherein the active layer comprises a semiconductor material with an optical memory function, and a channel and a source drain region are included in the active layer; wherein during the illumination phase and the integration phase, the bottom gate electrode and the top gate electrode of the phototransistor are at different voltages and the phototransistor is in an off-state operating region; the integration stage at least comprises a first preset time period after exposure is finished; wherein the semiconductor material with the optical memory function comprises a metal oxide semiconductor.

In particular, during the reset phase, the voltages of the bottom gate electrode and the top gate electrode of the phototransistor are such that the phototransistor is in an on-state operating region.

In particular, the phototransistor further includes a passivation layer at least on the top gate electrode, and a scintillator over the passivation layer and the source drain region.

The application also provides a method for using the double-gate phototransistor to sense light, wherein an active layer material of the double-gate phototransistor comprises a material having an optical memory function, the method comprising: exposing the double-gate phototransistor in an illumination stage, canceling illumination in a subsequent integration stage, respectively applying different potentials to a bottom gate electrode and a top gate electrode of the double-gate phototransistor in the entire illumination stage and the integration stage, and enabling the double-gate phototransistor to be in an off-state operation region, wherein the integration stage at least comprises a first preset time after the exposure is finished, and the semiconductor material with the optical memory function comprises a metal oxide semiconductor.

In particular, the method further comprises the step of applying voltages to the bottom gate electrode and the top gate electrode of the double-gate photoelectric transistor in a reset stage to enable the double-gate photoelectric transistor to be in an on-state working area.

The application also provides an image sensor array comprising a readout circuit, a gate drive circuit and a bias circuit, and a pixel array coupled thereto comprising a phototransistor as defined in any preceding claim.

Drawings

FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application;

FIG. 2 is a graph showing the integrated current variation of the row driving signal and the photosensitive cell in one frame period;

FIG. 3 is a schematic diagram of a pixel circuit according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a pixel array according to an embodiment of the application;

FIG. 5 is a schematic diagram of a pixel array according to another embodiment of the application;

FIG. 6 is a schematic diagram of a pixel circuit structure for X-ray imaging based on LTPO TFT process;

FIG. 7 is a schematic diagram of the driving signal timing sequence of each row of the pixel array and each corresponding working stage according to the embodiment of the present application;

FIG. 8 is a schematic diagram illustrating the effect of each row of driving pulses on each row of pixel circuits of a pixel array according to an embodiment of the present application;

FIG. 9 is a timing diagram of a pixel array according to an embodiment of the application;

FIG. 10 is a schematic diagram of the operation timing of a pixel array without employing an embodiment of the application;

FIG. 11 is a cross-sectional view of a pixel circuit according to an embodiment of the application;

FIG. 12 is a schematic diagram of the pixel circuit connection relationship shown in FIG. 6;

fig. 13 is a waveform diagram of transient output during simulation of a pixel circuit according to an embodiment of the application.

Detailed Description

The application will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, related operations of the present application have not been shown or described in the specification in order to avoid obscuring the core portions of the present application, and may be unnecessary to persons skilled in the art from a detailed description of the related operations, which may be presented in the description and general knowledge of one skilled in the art.

Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.

The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning.

The transistor in the application at least comprises three terminals, wherein the three terminals are a control electrode, a first electrode and a second electrode. The transistor may be a bipolar transistor, a field effect transistor, or the like. For example, when the transistor is a bipolar transistor, the control electrode refers to the base electrode of the bipolar transistor, the first electrode may be the collector or the emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or the collector of the bipolar transistor; when the transistor is a field effect transistor, the control electrode refers to the gate electrode of the field effect transistor, the first electrode may be the drain electrode or the source electrode of the field effect transistor, and the corresponding second electrode may be the source electrode or the drain electrode of the field effect transistor.

The present application provides a pixel circuit including a photosensitive cell, that is, a phototransistor having a photoelectric response, which is characterized in that a photoelectric signal (e.g., a photo-generated current) of a corresponding intensity is generated after receiving an incident light exposure, and the photosensitive cell has a memory (storage) function, and the photo-generated current is maintained in the photosensitive cell even after the incident light is removed. At the same time, the memory effect of the phototransistor can be erased by applying high gate voltage pulses. The pixel circuit further comprises a storage unit coupled to the photosensitive unit and configured to convert a photo-generated current generated by the photosensitive unit into a first electrical signal (specifically, photo-generated charge or photo-generated voltage) and store or hold the first electrical signal in an integration phase, wherein the integration phase at least comprises a preset time period after the end of the exposure phase. The photosensor pixel also includes a readout unit coupled to the memory unit for transferring, during a signal readout phase, photogenerated charge stored by the memory unit during an integration phase to an off-chip system and for further readout processing by coordinated control of the signal lines.

Furthermore, the photosensitive unit of the application adopts a transistor with photoelectric response to replace the traditional photodiode, and the structure of the image sensing array is improved through the emerging low-temperature polysilicon oxide (LTPO) process, so that the novel image sensing pixel and array have faster response speed, higher imaging resolution and larger dynamic range. Compared with the imaging array with the combination of the traditional photodiode and the thin film transistor structure, the pixel circuit provided by the application has the advantages that the manufacturing of the photosensitive unit and the switch array is completed at one time by the same set of thin film technology, and the pixel circuit has more mature technology compatibility, lower cost and greater development potential.

The application provides a pixel array, wherein the same type of driving signal lines of a plurality of pixel circuits in the same row in the array are connected to an input signal line, and a plurality of pixel circuits in adjacent rows multiplex a row scanning line to simultaneously receive driving signals, so that the photoelectric signal integration stage, the reading stage and the clearing, storing and memorizing stage of pixels in different rows can be parallelized, and meanwhile, the hardware layout space is saved. The output ends of the pixel circuits in the same column are connected together to output the first electric signal at the same time, so that the output efficiency is improved.

Embodiment one:

Referring to fig. 1, the present embodiment provides an image sensor pixel circuit, as shown in fig. 1, which includes a photosensitive unit 21, a storage unit 22 and a readout unit 23.

Wherein the photosensitive unit 21 is configured to receive exposure of incident light to generate a photoelectric signal, and the photoelectric signal generated by the photosensitive unit after the exposure is removed can still be maintained for a first preset time; the storage unit 22 is coupled to the photosensitive unit 21, and the storage unit 22 is configured to store the photoelectric signal to obtain the first electrical signal in an integration phase, where the integration phase at least includes a first preset time after the exposure is completed. The read-out unit 23 is coupled to the memory unit 22, the read-out unit 23 being adapted to output the first electrical signal stored by the memory unit 22. Wherein, a working period of the pixel circuit can be divided into four working phases, namely: a reset phase, a light phase, an integration phase and a readout phase. The photosensitive unit 21 has the function that the off-state current of the device changes under illumination intensity, the conductivity of the device changes under illumination and is maintained for a period of time, and the change of the electrical characteristics is detected and utilized to realize the conversion from an optical signal to an electrical signal; the function of the memory cell 22 is to store the photoelectric signal to obtain a first electrical signal, for example, the change of the charge on the capacitor plate of the memory cell 22 or the jump of the voltage signal stored in the memory cell 22; the readout unit 23 reads out the first electrical signal stored in the storage unit 22, where the first electrical signal may be a voltage signal or a current signal converted from a voltage signal changing on a capacitor.

Wherein, the photosensitive unit 22 is modulated by a reset signal, and the reset signal of the photosensitive unit 22 is a non-enabling potential in the stage of receiving incident light; and enters a reset phase, the reset signal of the photosensitive cell 22 is at an enable level.

The readout unit of the present embodiment includes a first transistor TN-1 and a second transistor TN; the photosensitive cell includes a third transistor tn+1 and the memory cell includes a storage capacitor Cs. The first pole of the third transistor is connected with a preset bias voltage Vref, the second pole of the third transistor is connected with the first pole of the first transistor TN-1, the second pole of the first transistor is connected with the first pole of the second transistor, and the second pole of the second transistor is an output end and is used for outputting a first electric signal stored in the memory cell; the control electrode of the third transistor is connected with the second electrode of the first transistor through a storage capacitor. The third transistor tn+1 is a transistor with photoelectric response, and includes devices such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Thin Film Transistor (TFT), and the third transistor generates a photoelectric signal (specifically, a photo-generated current) in a stage of receiving incident light exposure, and has a memory function, that is, the photoelectric signal is still maintained for a first preset time in a stage of removing the incident light, the conductivity of the photosensitive unit 21 is obviously changed after receiving light, and the off-state current of the third transistor tn+1 is still larger than the off-state current before light.

The storage unit 22 is coupled to the photosensitive unit 21 and is configured to convert the photoelectric signal (i.e. photo-generated current) into photo-generated charge or photo-generated voltage and store or hold the photo-generated charge or photo-generated voltage during an integration phase, wherein the integration phase comprises at least a first preset time period after the end of the exposure phase. The readout unit 23 is coupled to the memory unit 22, and in the signal readout stage, the photo-generated charges stored in the memory unit 22 in the integration stage are transferred to the off-chip system for further processing and readout through the cooperation control of the signal lines.

The present application provides a photosensor pixel circuit comprising a photosensitive unit 21, the photosensitive unit 21 being said to be a transistor having a photoelectric response which functions to generate a photo-generated current of a corresponding intensity upon receiving an incident light exposure and has a memory function, the photo-generated current being maintained in the photosensitive unit 21 even after the incident light is removed; at the same time, the memory effect of the phototransistor can be erased by applying high gate voltage pulses. The photosensor pixel circuit further includes a storage unit 22 coupled to the photosensitive unit 21 and operative to convert the photo-generated current to photo-generated charge or photo-generated voltage and store or hold it during an integration phase, wherein the integration phase includes a first predetermined period of time after the end of the exposure phase. The photosensor pixel circuit further includes a readout unit 23 coupled to the memory unit 22 for transferring the photogenerated charge stored by the memory unit 22 during the integration stage to the off-chip system and performing further readout processing by cooperative control of the signal lines during the signal readout stage.

The control electrode of the first transistor TN-1 is connected with a first driving signal line G [ N-1], and the first driving signal line G [ N-1] is used for receiving a corresponding control signal to turn on the first transistor TN-1, so that the first transistor TN-1 and the third transistor TN+1 are conducted through a storage capacitor Cs, and the storage capacitor Cs integrates the photoelectric signal to obtain a first electric signal. The control electrode of the second transistor TN is connected with a second driving signal line G [ N ], and the G [ N ] is used for receiving a corresponding control signal to turn on the second transistor TN and outputting a first electric signal on the storage capacitor from the second electrode of the second transistor TN. The control electrode of the third transistor is connected with a third driving signal line Gn+1, and the Gn+1 is used for receiving a corresponding control signal to eliminate a photoelectric signal generated when the third transistor TN+1 is exposed so as to restore the photoelectric signal to a conductive state when the third transistor TN+1 is not exposed to light.

Further, the readout unit 23 further includes an operational amplifier D1, a first capacitor C1, and a first switch S1; the second pole of the second transistor TN is connected with the negative input end of the operational amplifier, and the positive input end of the operational amplifier D1 is connected with a preset reference level; one end of the first capacitor C1 is connected with the negative input end of the operational amplifier D1, and the other end of the first capacitor C1 is connected with the output end of the operational amplifier D1; one end of the first switch S1 is connected with the negative input end of the operational amplifier D1, and the other end of the first switch S1 is connected with the output end of the operational amplifier D1; the output terminal of the operational amplifier D1 is used for outputting the first electrical signal on the memory cell 2. The present embodiment utilizes the performance of the operational amplifier D1 that is virtually short and virtually broken to perform an integrating operation on the photo-generated current/charge.

In one embodiment, the first transistor TN-1 and the second transistor TN are field effect thin film transistors; the third transistor tn+1 is a metal oxide semiconductor field effect transistor or a thin film transistor.

In one embodiment, as shown in FIG. 3, the first transistor TN-1, the second transistor TN, and the third transistor TN+1 are all double gate oxide thin film transistors. Wherein, two grid electrodes of the first transistor TN-1 are short-circuited, two grid electrodes of the second transistor TN are short-circuited, one grid electrode of the third transistor TN+1 is used for receiving illumination signals, and the other grid electrode is a control electrode thereof and is connected with the second electrode of the first transistor TN-1 through a storage capacitor TN+1. Wherein, two grid electrodes of the first transistor TN-1 and the second transistor TN are in short circuit together, can promote its switching performance. The two gates of the third transistor TN+1 as the photodetection are individually biased, and the photoelectric conversion efficiency of the third transistor TN+1 can be maximized by proper biasing of the additional gate C [ N-1 ]. More preferably, C N-1 is taken as a pulse signal with high voltage VC and low voltage VGL; g [ N-1] is a pulse signal of high voltage VGH and low voltage VGL, wherein VGL < VC < VGH, VC-VGL is approximately equal to VTH0, and VTH0 is the threshold voltage of the double-gate oxide thin film transistor.

In one embodiment, the first transistor and the second transistor are field effect thin film transistors and the third transistor is a metal oxide semiconductor field effect transistor; as shown in fig. 11, in one embodiment, the second transistor and the third transistor are integrally manufactured by adopting a LTPO process, where the second transistor includes a substrate 1101, a buffer layer 1102, a polysilicon layer 1103, a first gate electrode layer 1105, a first source drain electrode layer 1111, a second source drain electrode layer 1112, and a first insulating medium layer 1107; a buffer layer 1102 is formed on the substrate 1101, a polysilicon layer 1103 is disposed on the buffer layer 1102, a first gate electrode layer 1105 is disposed on the polysilicon layer 1103 and insulated from the polysilicon layer 1103, a first insulating dielectric layer 1107 is disposed on the first gate electrode layer 1105, and a first source drain electrode layer 1111 and a second source drain electrode layer 1112 are disposed on both sides of the gate electrode layer 1105 and insulated from the gate electrode layer 1105 by the first insulating dielectric layer 1107; the third transistor includes a first insulating dielectric layer 1109, a second insulating dielectric layer 1104, a second gate electrode layer 1106, a third gate electrode layer 1108, a metal oxide layer 1110, a third source/drain electrode layer 1113, and a fourth source/drain electrode layer 1114, the second insulating dielectric layer 1104 is disposed on the buffer layer 1102, the second gate electrode layer 1106 is disposed on the second insulating dielectric layer 1104, the third gate electrode layer 1108 is disposed on the second gate electrode layer 1106 through the first insulating dielectric layer 1107 and insulated from the second gate electrode layer 1106, the first insulating dielectric layer 1109 is disposed on the third gate electrode layer 1108, the metal oxide layer 1110 is disposed on the first insulating dielectric layer 1109, and the third source/drain electrode layer 1113 and the fourth source/drain electrode layer 1114 are disposed on two sides of the metal oxide layer 1110, respectively. The polysilicon layer 1103, the first gate electrode 1105, the first source-drain electrode layer 1111, the second source-drain electrode layer 1112, and the second insulating dielectric layer 1104 together form a low-temperature polysilicon thin film transistor device 1115. The metal oxide 1110, the third gate electrode layer 1108, the fourth source-drain electrode layer 1114, and the first insulating dielectric layer 1109 collectively constitute a metal oxide thin film transistor device 1116. The second gate electrode layer 1106, the third gate electrode layer 1108 and the first insulating dielectric layer 1107 together form a Metal-Insulator-Metal (MIM) capacitor 1117, where the upper plate of the capacitor 1117 and the third gate electrode layer 1108 of the MOTFT are the same Metal, and the second gate electrode layer 1106 is connected to the LTPS TFT through the second source-drain electrode layer 1112, so as to complete the electrical connection relationship between the source-drain electrode of the LTPS TFT with the structure shown in fig. 6 and the gate of the MOTFT through the capacitor.

In another embodiment, the fabrication of the second transistor and the third transistor is not limited to LTPO (polysilicon and oxide) processes, and in practice, hybrid TFT integration processes may be employed. For example, a hybrid integration process of LTPS (polysilicon) TFT and MO-TFT (metal oxide thin film transistor) may be used, or a hybrid integration process of LTPS-TFT and a-Si TFT may be used, or a hybrid integration process of LTPS (polysilicon) TFT and organic TFT may be used. For example, the mixed integration process of LTPS TFT and a-Si TFT has better photoelectric effect due to amorphous silicon TFT, and the LTPS TFT and the a-Si TFT are based on a silicon material system, so that the process has higher compatibility.

The image sensing array of the present invention is realized by a hybrid TFT integrated circuit process, which is not limited to LTPO processes, i.e., not necessarily by metal oxide TFTs for photo-sensing TFTs. Besides the scheme of using LTPS TFT as a charge amplifying and reading device and using metal oxide as a photosensitive device, the LTPS TFT can be used as a charge amplifying and reading device, an amorphous silicon TFT as a photosensitive device, or a LTPS TFT as a charge amplifying and reading device, an organic TFT as a photosensitive device, etc. The reasons for using LTPS TFT as charge amplifying and reading device and amorphous silicon TFT as photosensitive device include that amorphous silicon has better photoelectric effect, and the material system and process compatibility of amorphous silicon TFT and LTPS TFT are higher.

Fig. 12 illustrates a circuit connection relationship between LTPS TFT, cs and MOTFT portions of the structure shown in fig. 6, and corresponds to the schematic cross-sectional view of fig. 11, LTPS TFT1201 corresponds to LTPS TFT (thin film transistor device) 1115 of fig. 11, MOTFT1203 corresponds to MOTFT1116 of fig. 11, and capacitor Cs1202 corresponds to capacitor Cs1117 of fig. 11. Comparing fig. 11 and 12, it is worth noting that since LTPS TFTs have relatively high mobility, their device size can be relatively small; the mobility of the metal oxide TFT is relatively low, the size of the device is generally large, and the occupied layout area is large. In addition, the capacitance in the image sensing pixel circuit is generally larger, otherwise, enough photo-generated charge is not easy to collect in a limited exposure time. Therefore, the capacitor occupies a larger layout area. The design of this embodiment has the advantage that a metal oxide TFT is used as the photo-sensor, so that the larger the area of the metal oxide TFT, the higher the fill factor of the photo-sensor pixel circuit. Meanwhile, the capacitor is formed at the bottom of the metal oxide TFT, and follows the larger area of the metal oxide TFT, the value of the capacitor can naturally be made larger. Thus, in summary, the mixed TFT integrated pixel circuit of the polysilicon-metal oxide has better photoelectric conversion capability, and can realize an image sensor with higher spatial resolution.

Compared with the imaging array with the combination of the traditional photodiode and the thin film transistor structure, the pixel circuit provided by the application has the advantages that the same set of thin film technology is adopted, the photosensitive unit 21 and the switch array are manufactured at one time, and the process compatibility is more mature, the cost is lower, and the development potential is wide.

Example two

As shown in fig. 6, the present embodiment provides an image sensor pixel circuit for X-ray imaging based on LTPO TFT process. The pixel circuit comprises a photosensitive unit, a storage unit and a reading unit; wherein the photosensitive cell includes a photoelectric conversion device tn+1, the storage cell includes an integration switching device TN-1, the readout cell includes a readout switching device TN and an integration capacitor CS, the photoelectric conversion device tn+1 is an N-type device, and is composed of a metal oxide TFT, for example, an IZO TFT (oxide thin film transistor); the integration switching device TN-1 and the readout switching device TN are P-type devices and are composed of LTPS TFTs; the first terminal of the integrating capacitor CS is connected to the gate of TN+1 and the second terminal is connected to the source of TN-1. The gate of TN+1 is connected to the exposure control signal Gph, the drain thereof is connected to the reference voltage source Vref, and the source thereof is connected to the drain of TN-1. The gate of TN-1 is connected to the integral control signal Gint and its source is connected to the drain of TN. The gate of TN is connected to the read control signal Gread, and the source thereof is connected to an external amplifier.

The advantage of the X-ray pixel circuit LTPO TFT as shown in fig. 6 provided by this embodiment is that:

1) The photoelectric sensitivity of the metal oxide TFT is obviously higher than that of the LTPS TFT, especially in the blue-violet band; and LTPS TFT has higher mobility and higher device reliability. Therefore, the circuit can not only exert the advantages of high photoelectric sensitivity and low leakage current of the metal oxide TFT, but also exert the advantages of strong driving capability and high response speed of the LTPS TFT. Such an image sensor may be used for X-ray imaging to reduce the dose of X-rays considerably. In other words, the peripheral light input intensity is well imaged even though it is weak, so it has unique advantages for high resolution imaging of weak light inputs.

2) LTPO is a three-dimensional integrated X-ray sensitive panel structure, after completing the process integration of LTPS TFTs and capacitive elements, metal oxide TFTs for photosensitivity are formed and integrated over the LTPS TFT array using a lower processing temperature. Thus, almost the entire pixel has an X-ray sensitive function. This is favorable to reducing the irradiation dose of X ray, promotes photoelectric conversion's efficiency. Meanwhile, due to the three-dimensional integrated structure, the spatial resolution of the X-ray image sensing array is high, and the size of unit pixels can be small.

Example III

The present embodiment provides an image sensing array, as shown in fig. 4, where the pixel array includes a plurality of pixel circuits as provided in the first embodiment, and the plurality of pixel circuits are arranged in four rows and four columns, that is, the plurality of pixel circuits form a 4X4 pixel array. The plurality of pixel circuits of the present embodiment are connected in the form of multiplexed scanning lines to reduce the circuit arrangement of the whole pixel array. Wherein the first driving signal lines G [ N-1] of the plurality of pixel circuits in each row are connected with the first input signal lines to input the same driving signals, and the second driving signal lines G [ N ] of the plurality of pixel circuits in each row are connected with the second input signal lines to input the same driving signals; the third driving signal lines G [ n+1] of the plurality of pixel circuits in each row are connected to the third input signal lines to input the same driving signals.

Wherein the second poles of the second transistors of the plurality of pixel circuits in each column are connected to the same signal output line for outputting the first electric signal of each pixel circuit; wherein, the driving signals input on the first input signal lines connected on the pixel circuits of each next row are the same as the driving signals input on the second input signal lines in the previous row; the driving signal input on the second input signal line connected to the plurality of pixel circuits in each next row is the same as the driving signal input on the third input signal line in the previous row.

Further, as shown in fig. 5, the pixel array further includes a readout circuit, a gate driving circuit, and a bias circuit. The readout circuit is connected with signal output lines of a plurality of pixel circuits in each column; the grid driving circuit is respectively connected with the first driving signal line, the second driving signal line and the third driving signal line of each row of pixel circuits through a plurality of row scanning lines; the first poles of the third transistors of the plurality of pixel circuits of each column are connected to the bias circuit for uniformly inputting the same bias voltage through column scanning lines. As can be seen from fig. 4, the pixel array of this embodiment shares a set of gate driving circuits, and the gn signals are multiplexed among the N-1 row, the N-th row and the n+1 row, which has a simple structure without increasing the complexity of the peripheral driving circuits. Wherein the gate driving circuit can be formed by using the same oxide TFT (thin film transistor) as in the image sensor array without adding additional overhead of the gate driving IC design. The bias circuit provides a Vref voltage to the drain of the phototransistor in each pixel. Considering that the leakage current of each pixel and the photo-generated current of the same row of pixels during simultaneous photosensitive readout can be larger, the bias circuit should have stronger voltage stabilizing capability.

The specific operation phases of the pixel array are divided into a reset phase, an illumination phase, an integration and a readout phase. The high level state of all the row driving signals is VH, the low level state is VL, and the reference level of the non-inverting input terminal of the operational amplifier and the bias of the initial level of the on-chip pixel circuit are Vref.

As shown in fig. 2, during the reset phase of T1, both the photosensitive cell 21 and the readout cell 23 are in an on state, i.e., the first transistor TN-1, the second transistor TN, and the third transistor tn+1 are all in an on state, and the storage capacitor Cs of the storage cell 22 is biased to an initial state, and stores a charge of Q ₀.

Q₀＝C_s·(V_ref-VH)

T2 is the illumination/exposure phase: upon illumination, the conductivity of the third transistor tn+1 of the photosensitive cell 21 changes and this state can be maintained until the next high level of the gate voltage comes.

The integration and readout phase includes a high level pulse phase as shown by i-xi in fig. 2, as shown in fig. 2, when a high level pulse arrives from the gate driving line of the i phase G0 row, the TN-1 tube of the first row is opened, because the conductance of the tn+1 tube of the row of photosensitive cells is changed, the light intensity information is stored, the TN-1 tube is opened, vref passes through the TN-1 and tn+1 tubes, and corresponding current flows, as shown by Iph 1 in the i phase, which charges and discharges the memory cell 22 to change the charge quantity Q' on Cs, and after this phase, the charge quantity on Cs is Q1.

Q₁＝Q₀-Q′

In the ii phase, when the high level pulse of the gate driving line of the row G1 arrives, the TN tube of the readout unit 23 of the first row is opened, and the charge on Cs of the memory cell 22 is transferred out through the TN tube and the external ROIC, and the charge on Cs after this phase is Q2.

Q₂＝C_s·(V_ref-VL)

The amount of charge transferred out is Δq.

ΔQ＝Q₂-Q₁＝C_s·(VH-VL)+Q′

At the same time, in phase ii, the high pulse on the gate drive line of row G1 opens the TN-1 tubes of the second row, forming an integral path for the second row Vref, TN+1, TN-1 tubes, and current flows through, changing the charge stored on Cs of the memory cells 22 of the second row as shown in phase ii by Iph 2. In stage iii, the high level pulse of the G2 row gate drive line (i.e., row scan line) arrives to transfer the charge from the second row of memory cells 22 similarly to the first row, and at the same time, the high level pulse of the G2 row gate drive line integrates the next row (third row) as shown in stage iii Iph 3, and also eliminates the TN+1 stored photo information of the previous row (first row) of photo-sensing cells 21. In the same way, in the v stage, the high level of the G [ N-1] grid line eliminates the photoelectric information stored in the photosensitive unit 21 of the N-2 row, transfers and reads the photoelectric integral of the reading unit 23 of the N-1 row, and integrates the storage unit 22 of the N row; in stage vi, the high level of gate line G [ N ] eliminates the photoelectric information stored in photosensitive unit 21 of N-1 row, transfers and reads the photoelectric integral of reading unit 23 of N row, transfers and transfers the photoelectric signal … … of storage unit 22 of N+1 row in turn, and converts the light intensity information sensed by the whole panel into electric charge (voltage) information for reading.

After being illuminated, the conductivity of the photosensitive element 21 (i.e., the phototransistor) in this embodiment is changed and maintained for a period of time, so that the photo information generated by the photosensitive element 21 is used to describe it (this is also called the persistent photoconductive effect, PERSISTENT PHOTO-conduct PPC), and a long period of time is required for the conductivity of the phototransistor to return to its original state, or a positive voltage pulse is applied to the gate of the phototransistor, so that the conductivity state of the phototransistor returns to the state where the phototransistor was not illuminated. Referring to FIGS. 4, 7 and 8, the G [ N ] row pulse of the present embodiment is used to eliminate the photo signal stored in the photo-sensing unit 21 of the N-1 row, where the photo signal is different from the capacitance of the memory unit 22, and is two different signals. The action of the G [ N-1] row pulse signals is three, and the first G [ N-1] row pulse signal resets the conductivity state of the phototransistor of the N-2 row (the photosensitive cell TN+1 transistor of the N-2 row); second, G [ N-1] line pulse signals turn on the transistors (the readout tubes TN of the N-1 th line) of the readout units 23 of the present line (the N-1 th line), and output the first electric signals stored on the storage capacitors Cs of the present line (the N-1 th line) to the peripheral readout units 23; third, the G [ N-1] row pulse signal is used to turn on the transistor (TN-1) of the next row (N-th row), a path is formed between the storage capacitor Cs and the photosensitive cell 21 (TN+1), and the charge on Cs is integrated by utilizing the photoconductive change of the photosensitive cell 21, so as to form the conversion from the light intensity signal to the voltage signal, thereby obtaining the first electric signal. Namely: the action of the G [ N ] row pulse signals is three, and the first G [ N ] row pulse signal resets the conductivity state of the phototransistor of the N-1 row (the light sensitive cell TN+1 transistor of the N-1 row); second, the row G [ N ] pulse signal turns on the read cell transistor (read tube TN of the N-th row) of the row (N-th row), and reads out the voltage information stored in the memory cell 22 of the row (N-th row) in combination with the peripheral read cell 23; third, the G [ N ] row pulse signal turns on the transistor (TN-1) of the next row (n+1th row), a path is formed between the memory cell 22 and the photoconductive cell 21, and the charge on Cs is integrated by the photoconductive change of the photoconductive cell, resulting in conversion of the light intensity signal into the voltage signal. Similarly, the action of the G [ n+1] row pulse signals is three, and the first G [ n+1] row pulse signal resets the conductivity state of the phototransistor of the N line (the photosensitive cell TN+1 transistor of the N line); secondly, the G [ n+1] row pulse signal turns on the transistor (transistor TN of the (n+1) th row) of the readout unit 23 of the present row (n+1) th row), and reads out the voltage information stored in the memory unit Cs of the present row (n+1) th row in combination with the peripheral readout unit 23; third, the G [ n+1] row pulse signal turns on the transistor (TN-1) of the next row (n+2 row), a path is formed between the memory cell 22 and the photoconductive cell 21, and the charge on Cs is integrated by the change of the photoconductive cell 21, forming a conversion from the light intensity signal to the voltage signal, thereby obtaining the first electric signal.

Fig. 2 is a timing chart of row driving signals and a change of integration currents of transistors of the corresponding photosensitive cells 21 in a frame period of the M rows of pixel arrays. Where I _ph I denotes the integrated current of the transistor of the photosensitive cell 21 of the I-th row in one frame detection period. G [ i ] represents the row driving signal of the transistor of the readout unit 23 of the i-th row. T1 represents an initial reset phase within one frame detection period. T2 denotes an exposure phase within one frame detection period. I, ii, iii· … ·xi, and so on after T2 are read out phases for each row.

Referring to fig. 7, a timing sequence of row driving signals G [ N ], G [ n+1], G [ n+2] of the N-th row, the n+1-th row and the n+2-th row of the pixel array with the parallelization pipeline structure according to the present application is shown, T _N represents a readout phase of the N-th row pixel circuit, and Treset _N represents a reset phase of the N-th row pixel circuit after the N-th row pixel circuit is completely read out.

Fig. 8 illustrates the function and state transition of the pixel array of the parallelized pipeline structure according to the present application, and in conjunction with fig. 7, three pulses of adjacent gate driving signals G [ N ], G [ n+1], G [ n+2] respectively bear the actions of integrating the photoelectric signals, reading out the photoelectric signals, and eliminating the photoelectric memory effect of the n+1th row pixel circuit, so as to fulfill the above functional requirements of the n+1th row pixel circuit in time periods. In the longitudinal direction, a single gate driving signal G [ N ] pulse simultaneously completes the photoelectric memory elimination action of the N-1 row pixel circuit, the photoelectric signal reading action of the N row pixel circuit and the photoelectric signal integration action of the N+1 row pixel circuit, and simultaneously completes the functional requirements of the three adjacent rows of pixel circuits in space.

The advantage of the application of the parallelized pipelined readout driving timing shown in fig. 8 to the inventive pixel circuit structure is that:

1) When MO-TFT (metal oxide thin film transistor) is used for photoelectric detection, if MO-TFT is used for integrating photoelectric signals in the illumination receiving stage, PPC effect is negatively affected, and some structures are needed for interference cancellation, which requires adding a set of additional timing control. This also requires additional timing control if the photo signal integration is performed using the PPC effect of the MO-TFT after the illumination is removed. In the application, the image sensing pixel circuit utilizes the PPC effect to carry out photoelectric integration so as to enhance the photoelectric conversion efficiency, and through the novel pipeline structure, only one group of grid driving signals are needed under the condition of not increasing the complexity of peripheral driving, and a series of functions of photoelectric signal integration, reading and resetting can be well realized through the principle of time division multiplexing. From the viewpoint of image sensing array layout realization, the multiplexing structure of the row and row driving signal lines enables the number of the signal lines to be small, and is beneficial to improving the filling factor of the image sensing pixel array.

2) The parallelization pipeline structure can timely reset the photosensitive units of the previous row while reading out the photoelectric signals of each row, and the operation of time-sharing reset avoids the global reset of extra clock cycles, thereby being beneficial to shortening the frame time and improving the frame rate. The image sensing array is reset in a line-dividing and time-sharing mode, so that global reset of the whole image sensing array in the same period is avoided, the condition of large current possibly generated by global reset is avoided, and the robustness of the image sensing array is improved.

FIG. 9 illustrates a simplified timing diagram of the parallelization pipeline architecture of the present application. Wherein i is the initialization reset phase, ii is the exposure phase, iii is the readout phase, iv is the exposure phase of the next frame, and v is the readout phase of the next frame. I.e., T ₁、T₂ is one frame period, so on in the exposure-readout-exposure-readout … ….

FIG. 10 illustrates a timing scenario where a parallelized pipeline structure is not employed. Wherein i is the initialization reset phase, ii is the exposure phase, iii is the readout phase, iv is the PPC effect reset phase, v is the exposure phase of the next frame, vi is the readout phase of the next frame, iv is the PPC effect reset phase of the next frame. I.e., T ₁、T₂ is one frame period, repeating as exposure-read-PPC effect reset-exposure-read-PPC effect reset … …. As can be seen from comparison of FIG. 9, the parallel pipeline structure has one PPC reset phase less than the period of the common sequence without design, which is beneficial to improving the frame rate.

FIG. 13 illustrates a SPICE simulation waveform of a transient output of an embodiment of an electro-optic pixel circuit, in this example a 12X1 pixel array, where each pulse is an output of a corresponding row of pixel circuits, and the output pulses are different in size, corresponding to the different photo-generated currents generated by different illumination experienced by different rows of pixels. In the simulation, the parameters iol of the off-state current in the TFT SPICE model are modified to simulate the currents with different magnitudes and the corresponding changes of the conductivities of the phototransistors in the photoelectric sensing unit under different illumination intensities. The parameters of the phototransistors iol in the pixel array of 12X1 of the simulation example gradually increase from the first row to the twelfth row, the illumination intensity of the pixels in the row from the first row to the twelfth row is simulated to be gradually increased from the dark state to the light intensity, and the simulation output waveforms respectively correspond to the output responses of the columns under the condition of exposure from the first row without illumination to the twelfth row with gradually increased illumination intensity from left to right. According to the principle analysis described above, after each frame reset is completed, the initial charge amount is held on the charge of the memory cell, and the charge amount on the capacitor is restored to the initial charge amount after the readout. In the middle, the amount of charge on the capacitor is changed. Wherein the integrated charge variation produced during the integration phase is positively correlated with the illumination intensity; the amount of transferred charge sensed during the sensing phase is proportional to the amplitude of the transition of the output signal. Because the initial and final state voltage differences of the process capacitor are equal, the sum of the integrated charge variation positively correlated with the illumination intensity and the readout transferred charge amount is zero, and therefore the jump amplitude of the output signal is inversely correlated with the input photocurrent magnitude, i.e. the illuminated intensity magnitude. From the simulation result, the jump amplitude of the output signal voltage is sequentially reduced from left to right, and the corresponding conditions are that the photocurrent generated by the pixels in the column is gradually increased line by line and the illumination intensity received by the pixels in the column is gradually increased line by line. The simulation result shows that the voltage jump amplitude of the output signal is inversely related to the intensity of the simulated irradiation light, and the structure meets the expected working principle. If the voltage amplitude is distinguished according to the light intensity, the light intensity signal can be converted into an electric signal by subsequent analysis and processing. Therefore, the simulation result can prove that the pixel structure of the embodiment can work normally and accurately and is used for photoelectric image reading.

The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be limiting. Several simple deductions, modifications or substitutions may also be made by a person skilled in the art to which the invention pertains, based on the idea of the invention.

Claims

1. A phototransistor having a photoelectric response, comprising:

a second gate electrode layer, a first insulating dielectric layer, a metal oxide layer, a second insulating dielectric layer, a third gate electrode layer, a third source-drain electrode layer, and a fourth source-drain electrode layer;

Wherein during the illumination phase and the integration phase, the second gate electrode layer and the third gate electrode layer of the phototransistor are individually biased and the phototransistor is placed in an off-state operating region; the integration stage at least comprises a first preset time period after exposure is finished;

Wherein the third gate electrode layer bias voltage ranges between a low voltage VGL and a high voltage VC; the second gate electrode layer bias voltage ranges between a low voltage VGL and a high voltage VGH, wherein VGL < VC < VGH, and VC-VGL is approximately equal to VTH0, VTH0 being a threshold voltage of the phototransistor.

2. The phototransistor of claim 1 wherein the voltages of the second gate electrode layer and the third gate electrode layer of the phototransistor cause the phototransistor to be in an on-state operating region during a reset phase.

3. A method of using a double gate phototransistor for light sensing, comprising:

Exposing the double-gate phototransistor in an illumination stage, canceling illumination in a subsequent integration stage, individually biasing the second gate electrode layer and the third gate electrode layer of the double-gate phototransistor in the entire illumination stage and the integration stage, and placing the double-gate phototransistor in an off-state operating region, wherein the integration stage at least comprises a first preset time period after the end of the exposure;

4. A method as in claim 3, further comprising:

And in a reset stage, applying voltages to the second gate electrode layer and the third gate electrode layer of the double-gate phototransistor to enable the double-gate phototransistor to be in an on-state working region.

5. An image sensor pixel circuit comprises a photosensitive unit, a storage unit and a readout unit;

The photosensitive unit is used for receiving incident light exposure to generate photoelectric signals, and the photoelectric signals generated by the photosensitive unit can still be kept for a first preset time after the light is removed;

The storage unit is coupled with the photosensitive unit and is used for storing the photoelectric signal in an integration stage to obtain a first electric signal, and the integration stage at least comprises a first preset time after exposure is finished;

The reading unit is coupled with the storage unit and is used for outputting a first electric signal stored by the storage unit;

the photosensitive unit, the storage unit and the reading unit are prepared by the same type of transistor technology;

the readout unit includes a first transistor and a second transistor; the photosensitive unit comprises a third transistor, and the storage unit comprises a storage capacitor;

A first pole of the third transistor is connected with a preset bias voltage Vref, a second pole of the third transistor is connected with the first pole of the first transistor, a second pole of the first transistor is connected with the first pole of the second transistor, and the second pole of the second transistor is an output end and is used for outputting a first electric signal stored by the storage unit; the control electrode of the third transistor is connected with the second electrode of the first transistor through the storage capacitor;

wherein the third transistor is a phototransistor comprising: a second gate electrode layer, a first insulating dielectric layer, a metal oxide layer, a second insulating dielectric layer, a third gate electrode layer, a third source-drain electrode layer, and a fourth source-drain electrode layer;

Wherein during the illumination phase and the integration phase, the second gate electrode layer and the third gate electrode layer of the third transistor are individually biased and the third transistor is placed in an off-state operating region; the integration phase comprises at least the first preset time after the light is removed;

Wherein the third gate electrode layer bias voltage ranges between a low voltage VGL and a high voltage VC; the second gate electrode layer bias voltage ranges between a low voltage VGL and a high voltage VGH, wherein VGL < VC < VGH, and VC-VGL is approximately equal to VTH0, VTH0 being a threshold voltage of the third transistor.

6. An image sensor array comprising a readout circuit, a gate drive circuit and a bias circuit, and coupled thereto a pixel array comprising a phototransistor according to claim 1 or 2, or an image sensor pixel circuit array according to claim 5.