CN108769499B - Photosensitive chip, camera module and electronic equipment - Google Patents
Photosensitive chip, camera module and electronic equipment Download PDFInfo
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- CN108769499B CN108769499B CN201810967264.2A CN201810967264A CN108769499B CN 108769499 B CN108769499 B CN 108769499B CN 201810967264 A CN201810967264 A CN 201810967264A CN 108769499 B CN108769499 B CN 108769499B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/45—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract
The embodiment of the application discloses a photosensitive chip, a camera module and electronic equipment. The light sensing chip comprises an integrated circuit and at least two pixel arrays, wherein the integrated circuit is positioned on a substrate, and the light sensing chip is characterized in that the integrated circuit comprises a column reading circuit, and the at least two pixel arrays multiplex the column reading circuit. According to the embodiment of the application, the same wafer is used as the substrate, the photosensitive chip of the multi-camera system is designed and formed on the substrate, the position calibration of the photosensitive area of the multi-camera system is realized in the stage of manufacturing the photosensitive chip on the semiconductor, and the assembly precision of the multi-camera system is improved. In addition, the photosensitive chip is provided with a plurality of pixel arrays required by a multi-camera system, and at least two pixel arrays multiplex the column reading circuits, so that the circuits on the substrate are reduced, and the sizes of the photosensitive chip and the camera module can be reduced. Or, the area of the photosensitive area is increased on the basis of keeping the size of the photosensitive chip unchanged, so that the quality of a photographed image can be improved.
Description
Technical Field
The embodiment of the application relates to the technical field of mobile terminals, in particular to a photosensitive chip, a camera module and electronic equipment.
Background
Electronic equipment with a plurality of camera modules can control different cameras respectively and carry out different functions to make the picture of catching through the camera have more content and more clear, the formation of image is more exquisite, the color is more bright-colored.
The imaging process of the camera is mainly an optical signal digitizing process, which is mainly completed by a camera module, and the camera module generally consists of a lens component and a photosensitive chip. Currently, in the related art, a multi-camera system having a plurality of camera modules is generally assembled by a bracket. However, the circuit in the camera module is complex, the distance between the camera modules is large, and the module level assembly mode cannot meet the position production and calibration precision requirements between the modules. For example, in the case of binocular ranging, image fusion, etc., small deviations in distance or angle may cause large deviations in the final result.
Disclosure of Invention
The embodiment of the application provides a photosensitive chip, a camera module and electronic equipment, which can optimize the design scheme of a multi-camera system in the related technology.
In a first aspect, embodiments of the present application provide a photosensitive chip, including an integrated circuit and at least two pixel arrays on a substrate, where the integrated circuit includes a column read circuit, and the at least two pixel arrays multiplex the column read circuit.
In a second aspect, an embodiment of the present application provides a camera module, including the photosensitive chip provided in any embodiment of the present invention.
In a third aspect, an embodiment of the present application provides an electronic device, where the electronic device has a camera module provided by any embodiment of the present invention.
The embodiment of the application provides a photosensitive chip. By adopting the scheme, the same wafer is used as the substrate, the photosensitive chip of the multi-camera system is designed and formed on the substrate, the position calibration of the photosensitive area of the multi-camera system is realized in the stage of manufacturing the photosensitive chip on the semiconductor, and the assembly precision of the multi-camera system is improved. In addition, the photosensitive chip is provided with a plurality of pixel arrays required by a multi-camera system, and at least two pixel arrays multiplex the column reading circuits, so that the circuits on the substrate are reduced, and the sizes of the photosensitive chip and the camera module can be reduced. Or, the area of the photosensitive area is increased on the basis of keeping the size of the photosensitive chip unchanged, so that the quality of a photographed image can be improved.
Drawings
FIG. 1 is a schematic diagram of a conventional dual camera system;
FIG. 2 is a block diagram of a photosensitive chip according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of a further embodiment of a photosensitive chip;
FIG. 4 is a block diagram of a further embodiment of a photosensitive chip;
FIG. 5 is a block diagram of a further embodiment of a photosensitive chip;
FIG. 6 is a schematic circuit diagram of a classical correlated double sampling circuit in the related art;
FIG. 7 is a timing diagram of the operation of the correlated double sampling circuit;
fig. 8 is a schematic structural diagram of a camera module according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solution of the present application is further described below by means of specific embodiments in conjunction with the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a conventional dual-camera system. The first camera module 10 and the second camera module 20 are assembled into a multi-camera system by the bracket 130. Each camera module comprises a photosensitive chip (140, 150) and a lens assembly (110, 120), wherein the lens assembly (110, 120) comprises a lens, a lens seat and a motor. The photosensitive chips (140, 150) are soldered on the circuit board 160, and the imaging areas (141, 151) on the photosensitive chips (140, 150) are located in the vertical projection areas of the lenses (110, 120).
It should be noted that, due to the continuous improvement of the semiconductor technology and the technological level, the Image Sensor (Image Sensor) is used as a basic device for obtaining visual information, and has wider and wider application because it can realize the obtaining, conversion and expansion of visual functions of information, and gives visual Image information with visual, multi-level and rich content. The most widely used solid-state image sensors in the related art mainly include Charge Coupled Device (CCD) image sensors and Complementary Metal Oxide Semiconductor (CMOS) image sensors. The photosensitive chip of the embodiment of the present application may be the above-described two types of image sensors.
The semiconductor substrate of the photosensitive chip is provided with at least two pixel arrays and an integrated circuit which is arranged around the pixel arrays to realize the function of the photosensitive chip. The integrated circuit comprises a column read circuit, said at least two pixel arrays multiplexing said column read circuit. It should be noted that, in the embodiment of the present application, at least two pixel arrays are sequentially read according to a set time sequence, and a line-by-line scanning and column-by-column reading manner is adopted for each pixel array, so that it is ensured that the pixel signals in the second pixel array are read after the pixel signals corresponding to all the pixel units in the first pixel array are read. The pixel signal is output to an analog signal amplifying circuit for signal amplification and then output to an analog-to-digital converter. It should be noted that, the pixel array is an imaging region of an image, and includes x×y (row×column) imaging pixel units, each pixel unit has a light sensing capability, and can convert an optical signal into a corresponding analog electronic signal. The pixel array is provided with a row bus and a column bus, and the pixel units are connected to the corresponding row bus and column bus.
The integrated circuit comprises a line scanning circuit, a line bus is electrically connected with the line scanning circuit through a switch unit (triode or field effect transistor), and the line scanning circuit outputs a line scanning signal to the pixel array. It is understood that the number of the line scan circuits may be the same as the number of the pixel arrays, the first line scan circuit is electrically connected to the first pixel array, the second line scan circuit is electrically connected to the second pixel array, … …, and the nth line scan circuit is electrically connected to the nth pixel array, where the value of n is determined by the number of camera modules in the multi-camera system. Optionally, the at least two line scanning circuits output line scanning signals according to a serial working mode, so as to realize sequential scanning of the at least two pixel arrays. The integrated circuit also comprises a column selection circuit and a column reading circuit, wherein the column selection circuit is connected with the control end of a switch unit (triode or field effect transistor), one of the other two ends of the switch unit is connected with a column bus, and the other end of the switch unit is connected with the column reading circuit, so that the column bus to be read is communicated with the column reading circuit.
It should be noted that, a plurality of photosensitive chips may be formed on the same wafer by using the semiconductor device manufacturing process, and dicing may be performed one by one. The photosensitive chip comprises at least two pixel arrays and corresponding integrated circuits. The problem that the multi-camera system module in the related art is difficult to assemble and debug can be avoided. In the related art, the camera module of the multi-camera system is a plurality of photosensitive chips corresponding to a plurality of lenses, each camera has independent functions, and has no function sharing part, and as the chips are respectively positioned on the circuit boards, the placement angle and the inclination of each chip are different, and the difficulty of subsequent equipment and debugging can be increased.
For ease of understanding, the structure of the photosensitive chip will be described by taking a CMOS image sensor as an example. Fig. 2 is a block diagram of a photosensitive chip according to an embodiment of the present application. The photosensitive chip shown in fig. 2 includes a first pixel array 202, a second pixel array 206, and an integrated circuit, wherein the integrated circuit includes a first row scanning circuit 201 electrically connected to the first pixel array 202, a second row scanning circuit 205 electrically connected to the second pixel array 206, and a column reading circuit 203 electrically connected to the first pixel array 202 and the second pixel array 206, respectively, and a column selecting circuit 204 electrically connected to the column reading circuit 203 through a switching unit. Wherein the column bus 216 of the second pixel array 206 is formed by extending the column bus 216 of the first pixel array 202 downward. The column select circuit 204 is connected to the control terminal (the terminal numbered 1) of the switching unit, and the column bus 216 and the column read circuit 203 are respectively connected to the remaining terminals (the terminals numbered 2 and 3, respectively) of the switching unit. The integrated circuit further includes a first analog signal amplifier 207 and a second analog signal amplifier 208 respectively connected to the column read circuit 203, a first analog-to-digital converter 209 connected to an output terminal of the first analog signal amplifier 207, a second analog-to-digital converter 210 connected to the second analog signal amplifier 208, a first image processor 211 connected to the first analog-to-digital converter 209, a second image processor 212 connected to the second analog-to-digital converter 210, and a first input/output interface circuit 213 connected to the first image processor 211, and a second input/output interface circuit 214 connected to the second image processor 212.
When the camera on command is detected, the processor (e.g., CPU) outputs a control signal to the timing control circuit of the photosensitive chip, so that the timing control circuit sequentially outputs a scan control pulse to each row scan circuit, and outputs a column selection control signal to the column selection circuit 204. The first row scanning circuit 201 outputs row scanning signals to the first pixel array 202 row by row in accordance with the scanning control pulse. The column select circuit 204 gates the column bus 216 of the column to be read and the column read circuit 203 in accordance with the column select control signal. The scan control pulse is used to control the first row scan circuit 201 to output a row scan signal to a first row of the first pixel array in a first period of time, so as to realize that the switch units electrically connected to the pixels of the first row are turned on, and the column selection control signal is used to control the column selection circuit 204 to output a turn-on signal to the switch units between the column bus and the column reading circuit 203 in the first period of time, so as to respectively turn on each switch unit, realize that the pixel signals on the column bus are read one by one, and output the pixel signals to the first analog signal amplifier 207. After the pixel signals of the last column of pixels in the first row are read, scanning signals are output to the second row to realize the conduction of field effect transistors electrically connected with the pixels in the second row, and the pixel signals on the column bus are read one by one. And so on until the pixel signals of the last row and the last column of pixels in the first pixel array are read.
After the pixel signals of the last row and the last column of pixels in the first pixel array are read, the timing control circuit outputs a scan control pulse to the second row scanning circuit 205, and outputs a column selection control signal to the column selection circuit 204. The second line scanning circuit 205 outputs line scanning signals to the second pixel array 206 line by line in accordance with the scanning control pulse. The column select circuit 204 gates the column bus 216 and the column read circuit 203 of a column of pixel cells to be read according to the column select control signal. The scan control pulse is used to control the second row scan circuit 205 to output a row scan signal to the first row of the second pixel array in a second period of time, so as to realize the conduction of the switch units electrically connected to the pixels of the first row, and during the second period of time, the column selection control signal controls the column selection circuit 204 to output a conduction signal to the switch units between the column bus and the column reading circuit 203, so as to respectively turn on the switch units, realize the reading of the pixel signals on the column bus one by one, and output the pixel signals to the second analog signal amplifier 208. After the pixel signals of the last column of pixels in the first row are read, scanning signals are output to the second row, so that the switch units electrically connected with the pixels in the second row are conducted, and the pixel signals on the column bus are read one by one. And so on until the pixel signals of the last row and the last column of pixels in the second pixel array are read.
Alternatively, the column read array 203 sends the pixel signals to the first analog signal amplifier 207 or the second analog signal amplifier 208 according to the parity of the number of times the pixel signals are read, and the column read array 203 sends the pixel signals read an odd number of times to the first analog signal amplifier 207 and sends the pixel signals read an even number of times to the second analog signal amplifier 208 to realize sequential reading of the pixel signals on the column bus in the two pixel arrays. When the number of pixel arrays is greater than 2, the multiplexed column read array 203 may determine the correspondence between the pixel signals and the analog amplifiers with the number of pixel arrays as a period.
The first analog signal amplifier 207 amplifies the pixel signal read by the first pixel array and outputs the amplified pixel signal to the first analog-to-digital converter 209.
The second analog signal amplifier 208 amplifies the pixel signals read by the second pixel array and outputs the amplified pixel signals to the second analog-to-digital converter 210.
The first analog-to-digital converter 209 converts the amplified pixel signal output from the first analog signal amplifier 207 into a digital signal and outputs the digital signal to the first image processor 211.
The second analog-to-digital converter 210 converts the amplified pixel signal output from the second analog signal amplifier 208 into a digital signal and outputs the digital signal to the second image processor 212.
The first image processor 211 receives the digital signal output by the first analog-to-digital converter 209, performs a preset process on the digital signal according to a chip definition function of the photosensitive chip to obtain image data, and adds an array identifier to the image data according to a source of the pixel signal. Note that the preset processing of the digital signal includes processing of AEC (automatic exposure control), AGC (automatic gain control), AWB (automatic White balance), color correction, lens Shading correction, gamma correction, dead pixel removal, auto Black Level correction, auto White Level correction, and the like. It should be noted that, since the first image processor 211 is electrically connected to the output terminal of the first analog-to-digital converter 209, the first analog-to-digital converter 209 obtains the digitized pixel signal, and the pixel signal is read by the first pixel array, so that the source of the pixel signal is known as the first pixel array.
The second image processor 212 receives the digital signal output by the second analog-to-digital converter 210, performs a preset process on the digital signal according to the chip definition function of the photosensitive chip to obtain image data, and adds an array identifier to the image data according to the source of the pixel signal. It should be noted that, since the second image processor 212 is electrically connected to the output terminal of the second analog-to-digital converter 210, the second analog-to-digital converter 210 obtains the digitized pixel signal, and the pixel signal is read by the second pixel array, so that the source of the pixel signal is known as the second pixel array.
The first input/output interface circuit 213 obtains the image data output by the first image processor 211, and adjusts the format of the image data of each pixel array according to the set format, and adds an array identifier at a preset position of the image data after the format adjustment, and outputs the image data to the back-end platform for use in the subsequent steps. Correspondingly, the second input/output interface circuit 214 obtains the image data output by the second image processor 212, and respectively adjusts the format of the image data of each pixel array according to the set format, adds an array identifier at a preset position of the image data after the format adjustment, and outputs the image data to the back-end platform. The preset position may be selected in various ways, and embodiments of the present application are not limited in particular. For example, an array identifier may be added to the header of the formatted image data. For another example, an array identifier may be added at the tail of the formatted image data.
In this embodiment, the number of analog signal amplifiers, analog-to-digital converters, line scan circuits, image processors, and input/output interfaces is the same as the number of pixel arrays, and the pixel signals of each pixel array are processed respectively without affecting each other.
The technical scheme of the embodiment of the application provides a photosensitive chip, which comprises a substrate, wherein the substrate comprises at least two pixel arrays and an integrated circuit, the integrated circuit comprises a column bus which adopts an etching process to enable the at least two pixel arrays to be correspondingly and electrically connected, and the column bus is respectively and electrically connected with a column selection circuit and a column reading circuit through a switch unit, so that the two pixel arrays share the column selection circuit and the column reading circuit. According to the technical scheme, the same wafer is used as the substrate, the photosensitive chip of the multi-camera system is designed and formed on the substrate, the position calibration of the photosensitive area of the multi-camera system is realized in the stage of manufacturing the photosensitive chip on the semiconductor, and the assembly precision of the multi-camera system is improved. In addition, the photosensitive chip is provided with a plurality of pixel arrays required by a multi-camera system, and at least two pixel arrays multiplex the column reading circuits, so that the circuits on the substrate are reduced, and the sizes of the photosensitive chip and the camera module can be reduced. Or, the area of the photosensitive area is increased on the basis of keeping the size of the photosensitive chip unchanged, so that the quality of a photographed image can be improved.
Fig. 3 is a block diagram of still another embodiment of a photo-sensing chip, which includes a column selection circuit 204, a column reading circuit 203, an analog signal amplifier 301, at least two analog-to-digital converters (209, 210), at least two image processors (211, 212), and an input/output interface circuit 215. The input of the analog signal amplifier 301 is electrically connected to the output of the column read circuit 203. The first analog-to-digital converter 209 and the second analog-to-digital converter 210 are electrically connected with the analog signal amplifier 301, and a first switch circuit 302 is connected in series between the first analog-to-digital converter 209 and the analog signal amplifier 301, and a second switch circuit 303 is connected in series between the second analog-to-digital converter 210 and the analog signal amplifier 301. The remaining circuits are similar to the above embodiments and will not be described here again.
The timing control circuit is electrically connected to the first switch circuit 302 and the second switch circuit 303. The timing control circuit generates a switching pulse based on a read order of at least two pixel arrays and a read time of each pixel array, outputs the switching pulse to the first switching circuit 302 and the second switching circuit 303, and controls the switching circuit (including the first switching circuit 302 and the second switching circuit 303) to turn on or off an analog-to-digital converter connected to the analog signal amplifier 301 based on the switching pulse.
For example, the timing control circuit generates the switching pulse according to the reading sequence of the first pixel array 202 and the second pixel array 206 and the reading time after reading each pixel array. If the first pixel array 202 is read first, the switch pulse is output to turn on the first switch circuit 302 and turn off the second switch circuit 303, so as to input the amplified pixel signal to the first analog-to-digital converter 209. When the second pixel array 206 is read, the output switching pulse turns on the second switching circuit 303 and turns off the first switching circuit 302 to input the amplified pixel signal to the second analog-to-digital converter 210. The first analog-to-digital converter 209 converts the pixel signal into a corresponding digital signal, and outputs the digital signal to the first image processor 211. The first image processor 211 performs a preset operation on the digital signal to obtain image data, adds an array identifier representing the first pixel array to the image data, and outputs the image data carrying the array identifier to the input/output interface circuit 215, so as to output the image data carrying the array identifier in accordance with a preset format or specification. Similarly, the second adc 210 converts the pixel signal into a corresponding digital signal, and outputs the digital signal to the second image processor 212. The second image processor 212 performs a preset operation on the digital signal to obtain image data, adds an array identifier representing the second pixel array to the image data, and outputs the image data carrying the array identifier to the input/output interface circuit 215, so as to output the image data carrying the array identifier in accordance with a preset format or specification.
The technical scheme of the embodiment of the application provides a photosensitive chip, which reduces circuits on a substrate by sharing a column selection circuit, a column reading circuit, an analog signal amplifier and an input/output interface by two pixel arrays, thereby reducing the sizes of the photosensitive chip and a camera module. Or, the area of the photosensitive area is increased on the basis of keeping the size of the photosensitive chip unchanged, so that the quality of a photographed image can be improved.
It should be noted that, the input/output interface circuit 215 in fig. 3 may be replaced by a first input/output interface circuit 213 and a second input/output interface circuit 214, where the first input/output interface circuit 213 is electrically connected to the first image processor 211, and the second input/output interface circuit 214 is electrically connected to the second image processor 212.
Fig. 4 is a block diagram of still another embodiment of a photosensitive chip. The photo-sensing chip comprises a column selection circuit 204, a column reading circuit 203, an analog signal amplifier 301, an analog-to-digital converter 401, an image processor 402 and an input/output interface circuit 215. The input end of the analog signal amplifier 301 is electrically connected to the output end of the column read circuit 203, the output end of the analog signal amplifier 301 is electrically connected to the input end of the analog-to-digital converter 401, the output end of the analog-to-digital converter 401 is electrically connected to the image processor 402, and the output end of the image processor 402 is electrically connected to the input/output interface circuit 215.
When the camera on command is detected, the processor (e.g., CPU) outputs a control signal to the timing control circuit of the photosensitive chip, so that the timing control circuit sequentially outputs a scan control pulse to each row scanning circuit, and outputs a column selection control signal to the column selection circuit 204, so as to sequentially read the pixel signals in each pixel array by the column reading circuit 203. The column reading circuit 203 outputs a pixel signal to the analog signal amplifier 301 to perform amplification processing, and obtains an amplified pixel signal, which is input to the analog-to-digital converter 401. The analog-to-digital converter 401 converts the amplified pixel signal into a corresponding digital signal, and outputs the digital signal to the image processor 402. The image processor 402 records the number of received digital signals and compares the number to a predetermined threshold. If the number of digital signals received by the image processor 402 is equal to the preset threshold, it is determined that the next read digital signal belongs to the next pixel array, a first array identifier in the preset identifier set is obtained, and the first array identifier is added to the image data. Then, the count value is cleared, and the read digital signal is counted again. The preset threshold may be a set of at least two positive integers arranged in sequence, and the value is determined by the reading sequence of the pixel array and the number of pixel units included in the pixel array. Taking two pixel arrays of 3×4 as an example, a first pixel array is read first, which includes 12 pixel units, and the first number in the set corresponding to the preset threshold is 12, and since the second pixel array also includes 12 pixel units, the second number is also 12. The predetermined threshold is [12,12], and the image processor 402 is operative to obtain a first value as the predetermined threshold, and to use a second value as the predetermined threshold when the number of recorded pixel signals is equal to the first value. The array identifiers in the preset identifier set are determined according to the reading sequence of each pixel array, and the array identifiers can be identifiers for uniquely determining the pixel arrays.
The image processor 402 outputs the image data carrying the array identifier to the input/output interface circuit 215, and the input/output interface circuit 215 performs format adjustment on the image data of each pixel array according to a set format sequence and outputs the image data with the format adjusted and the array identifier.
The technical scheme of the embodiment of the application provides a photosensitive chip, which further reduces the circuits on the substrate by sharing a column selection circuit, a column reading circuit, an analog signal amplifier, an analog-to-digital converter, an image processor and an input-output interface circuit by two pixel arrays, thereby saving the space occupied by the chip in a camera module.
In some embodiments, the integrated circuit of the photosensitive chip further includes a correlated double sampling circuit, and fig. 5 is a block diagram of still another structure of the photosensitive chip according to an embodiment of the present application. The correlated double sampling circuit comprises a first reset control circuit and a second reset control circuit, and is used for respectively resetting the pixels in the first pixel array and the pixels in the second pixel array after receiving reset signals. The design has the advantages that the reset of the pixels and the integrated signals after pixel integration are collected, the difference value between the integrated signals and the reset signals is calculated and output to an analog signal amplifier, and the fixed pattern noise (including column fixed pattern operation and pixel fixed pattern noise) is eliminated through a correlated double sampling technology. In this case, due to the limitation of the accuracy of the manufacturing process, the pixel signal read out by each column readout circuit has a certain error offset, which is called column fixed pattern noise. In addition, there is also a difference between pixels due to manufacturing process errors, which is called pixel fixed pattern noise.
Illustratively, the light sensing chip includes a first pixel array 202, a second pixel array 206, and an integrated circuit. The integrated circuit includes:
and the interface circuit is used for loading external control data to the memory register group of the chip. 9
And the time sequence control circuit is used for generating internal time sequence signals such as integral reading, resetting and the like of the pixel units according to the data set by the internal register and outputting the internal time sequence signals to the corresponding circuits in the form of pulse signals.
The first row scanning circuit (including a first row address decoder and a first row shift register) is electrically connected to the timing control circuit and the first pixel array 202, respectively, and is configured to output a row scanning signal to the first pixel array 202 or output a reset control signal to the first reset control circuit under the control of the timing control circuit.
The second row scanning circuit (including a second row address decoder and a second row shift register) is electrically connected to the timing control circuit and the second pixel array 206, respectively, and is configured to output a row scanning signal to the second pixel array 206 or output a reset control signal to the second reset control circuit under the control of the timing control circuit.
The first reset control circuit is electrically connected to the first pixel array 202, and is configured to perform a reset process on the pixels in the current row according to a reset control signal output by the first row reset circuit (including the first row address decoder and the first row shift register). Wherein the current row is the row to be read in the current pixel array.
The second reset control circuit is electrically connected to the second pixel array 206, and is configured to perform a reset process on the pixels in the current row according to a reset control signal output by the second row reset circuit (including the second row address decoder and the second row shift register).
For ease of understanding, a classical correlated double sampling circuit is used to sample and reset a pixel cell, illustrating the manner in which fixed pattern noise is eliminated by correlated double sampling techniques. Fig. 6 is a schematic circuit diagram of a classical correlated double sampling circuit in the related art. As shown in fig. 6, the photodiode included in the pixel unit is equivalently simulated by a current source Iph, a capacitor Cd, and a resistor Rd, and the reset switch is an NMOS transistor MR. NMOS tubes MLN and MIN form a source follower amplifier, PMOS tubes MSR and MSHS are two signal transmission gates, capacitors CR and Cs form two sampling capacitors, and NMOS tubes MS1 and MS2 are used for resetting the sampling capacitors.
FIG. 7 is a timing diagram illustrating the operation of the correlated double sampling circuit. As shown in fig. 7, the related double sampling circuit works as follows:
(1) Sampling a reset signal Vr: in the process of time t from 0 to t0, the reset switching tube MR is conducted under the control of the reset control signal VR, the n-point potential becomes high level, and VX and VLN keep high level; at time t0, the photosensitive chip starts exposure, and n-point voltage is sampled to the capacitor CR through the source follower and the transmission gate MSR, and the output reset signal Vr.
(2) Sampling the integrated signal Vs: in the process from t1 to t2, the two transmission gates are disconnected, no signal sampling is performed, and the integral voltage at the n point gradually drops due to the action of the photocurrent Iph. At time t2, the transmission gate MSHS is turned on, and the n-point voltage is sampled onto the capacitor CS by the source follower and the transmission gate, and the output integrated voltage signal Vs.
(3) At time t3, the signals Vr and Vs on the two sampling capacitors are differenced, and the difference is outputted as an effective signal through the column bus.
The remaining circuits such as the analog signal amplifier and the analog-to-digital converter are similar to those of the above embodiments, and will not be repeated here.
The technical scheme of the embodiment of the application provides a photosensitive chip, which further comprises a correlated double sampling circuit, wherein the correlated double sampling circuit is used for collecting integral signals and reset signals of pixels in the pixel array, calculating the difference value between the integral signals and the reset signals, and outputting the difference value to the analog signal amplifier, so that fixed mode noise can be effectively eliminated.
The embodiment of the application also provides a camera module, which comprises the photosensitive chip provided by the embodiment, and a multi-camera system is formed by one photosensitive chip with at least two pixel arrays. The camera module may include a plurality of rear camera modules and/or a plurality of front camera modules having the photosensitive chip provided in the above embodiments. The camera module comprises:
the photosensitive chip with the structure described in the above embodiment is soldered on the circuit board. The precision of the semiconductor manufacturing process is far higher than that of the module manufacturing process, and two or more pixel arrays are prepared on the same substrate to form a plurality of photosensitive areas, so that the flatness of the chip, the relative deviation of at least two photosensitive areas, the relative inclination angle and other angles can be improved from millimeter level to micrometer level.
And the number of the lenses is consistent with that of the pixel arrays of the photosensitive chip. The lenses are fixed through the lens base to form a lens, the lens base and the voice coil motor form a lens assembly, and the lens assembly is fixed on the circuit board through the bracket to form a multi-camera system. It should be noted that the multi-camera system may be a camera system formed by a plurality of rear camera modules and/or a plurality of front camera modules.
Fig. 8 is a schematic structural diagram of a camera module according to an embodiment of the present application. As shown in fig. 8, the camera module includes: the first lens assembly 810, the second lens assembly 820, the bracket 830 and the photosensitive chip 840. The first lens assembly 810 includes a first lens, a first lens base and a first motor, so that the first lens slides in the first lens barrel under the driving of the first motor to adjust a focal length; the second lens assembly 820 comprises a second lens, a second lens base and a second motor, so that the second lens slides in the second lens barrel under the drive of the second motor to adjust the focal length. The photosensitive chip 840 includes a first pixel array 841 and a second pixel array 842, and the circuit structure thereof is shown in the above embodiment and will not be described herein. And the photosensitive chip 840 is welded on the circuit board 850, the size of the circuit board 850 is larger than that of the photosensitive chip 840, and the bracket 830 is fixedly connected with the circuit board 850 to form a packaging structure of the camera module.
Optionally, the first lens assembly 810 further includes a first infrared filter for filtering infrared light signals collected by the first lens. The second lens assembly 820 further comprises a second infrared filter for filtering infrared light signals collected by the second lens.
Alternatively, the first infrared filter may be disposed separately from the first lens assembly 810, and the second infrared filter may be disposed separately from the second lens assembly 820.
Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The camera module provided by the embodiment of the application is provided. The electronic device may be a terminal with a camera, such as a smart phone, a PAD (tablet personal computer), a notebook computer, and an intelligent wearable device. Taking a smart phone as an example of a structure of an electronic device, fig. 9 is a block diagram of the structure of the smart phone according to an embodiment of the present application. As shown in fig. 9, the smart phone may include: a housing (not shown), a memory 901, a central processing unit (Central Processing Unit, CPU) 902 (also referred to as a processor, hereinafter CPU), a peripheral interface 903, an RF (Radio Frequency) circuit 905, an audio circuit 906, a speaker 911, a touch screen 912, a multi-camera system 913, a power management chip 908, an input/output (I/O) subsystem 909, other input/control devices 910, and an external port 904, which communicate via one or more communication buses or signal lines 907.
Memory 901, which memory 901 may be accessed by CPU902, peripheral interface 903, etc., which memory 901 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, or other volatile solid state storage devices.
A peripheral interface 903, said peripheral interface 903 may connect input and output peripherals of the device to the CPU902 and the memory 901.
I/O subsystem 909, which I/O subsystem 909 can connect input and output peripherals on the device, such as touch screen 912 and other input/control devices 910, to peripheral interface 903. The I/O subsystem 909 may include a display controller 9091 and one or more input controllers 9092 for controlling other input/control devices 910. Wherein one or more input controllers 9092 receive electrical signals from other input/control devices 910 or send electrical signals to other input/control devices 910, other input/control devices 910 may include physical buttons (push buttons, rocker buttons, etc.), dials, slider switches, joysticks, click wheels. It should be noted that the input controller 9092 may be connected to any of the following: a keyboard, an infrared port, a USB interface, and a pointing device such as a mouse.
A touch screen 912, the touch screen 912 being an input interface and an output interface between the user's mobile terminal and the user, displays visual output to the user, which may include graphics, text, icons, video, and the like.
The display controller 9091 in the I/O subsystem 909 receives electrical signals from the touch screen 912 or transmits electrical signals to the touch screen 912. The touch screen 912 detects a contact on the touch screen, and the display controller 9091 converts the detected contact into an interaction with a user interface object displayed on the touch screen 912, i.e., to implement a man-machine interaction, the user interface object displayed on the touch screen 912 may be an icon running a game, an icon networked to a corresponding network, or the like. It is noted that the device may also include a light mouse, which is a touch sensitive surface that does not display a visual output, or an extension of a touch sensitive surface formed by a touch screen.
The RF circuit 905 is mainly used for establishing communication between the mobile phone and a wireless network (i.e. a network side), so as to realize data receiving and sending between the mobile phone and the wireless network. Such as sending and receiving short messages, emails, etc. Specifically, the RF circuit 905 receives and transmits an RF signal, which is also referred to as an electromagnetic signal, and the RF circuit 905 converts an electric signal into an electromagnetic signal or converts an electromagnetic signal into an electric signal and communicates with a communication network and other devices through the electromagnetic signal. RF circuitry 905 may include known circuitry for performing these functions including, but not limited to, an antenna system, an RF transceiver, one or more amplifiers, a tuner, one or more oscillators, a digital signal processor, a CODEC (COder-DECoder) chipset, a subscriber identity module (Subscriber Identity Module, SIM), and so forth.
Audio circuitry 906 is operative to receive audio data from the peripheral interface 903, convert the audio data into electrical signals, and transmit the electrical signals to the speaker 911.
A speaker 911 for reproducing a voice signal received from the wireless network through the RF circuit 905 by the mobile phone into sound and playing the sound to the user.
The power management chip 908 is used for supplying power and managing power for the hardware connected with the CPU902, the I/O subsystem and the peripheral interfaces.
The information encryption device, the storage medium and the mobile terminal provided in the above embodiments can execute the information encryption method provided in any embodiment of the present application, and have the corresponding functional modules and beneficial effects of executing the method. Technical details not described in detail in the above embodiments may be found in the information encryption method provided in any embodiment of the present application.
Note that the above is only a preferred embodiment of the present application and the technical principle applied. Those skilled in the art will appreciate that the present application is not limited to the particular embodiments described herein, but is capable of numerous obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the present application. Therefore, while the present application has been described in connection with the above embodiments, the present application is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the present application, the scope of which is defined by the scope of the appended claims.
Claims (8)
1. The integrated circuit comprises a column reading circuit, a column selecting circuit, an analog signal amplifier, an analog-to-digital converter, an image processor and an input-output interface circuit, wherein the column reading circuit and the column selecting circuit are multiplexed by the at least two pixel arrays;
the column buses of at least two pixel arrays are correspondingly and electrically connected by adopting an etching process;
the column reading circuit is electrically connected with column buses of the at least two pixel arrays and is used for sequentially reading pixel signals on the column buses of the at least two pixel arrays and transmitting the read pixel signals to the analog signal amplifier;
the column selection circuit is electrically connected with column buses of the at least two pixel arrays and is used for gating the column buses of the columns to be read and the column reading circuit according to column selection control signals;
the analog-to-digital converter converts the amplified pixel signal output by the analog signal amplifier into a digital signal and outputs the digital signal to the image processor;
the image processor performs preset processing on the digital signals according to the chip definition function of the photosensitive chip to obtain image data, and adds an array identifier for the image data according to the source of pixel signals;
the image processor transmits the processed image data to the input/output interface circuit;
the input/output interface circuit respectively carries out format adjustment on the image data of each pixel array according to a set format, adds an array identifier at a preset position of the image data after format adjustment, and outputs the array identifier to the back-end platform;
the integrated circuit further comprises at least two line scanning circuits, wherein the at least two line scanning circuits output line scanning signals according to a serial working mode, and at least two pixel arrays are scanned sequentially.
2. The light-sensing chip according to claim 1, wherein the number of analog signal amplifiers is the same as the number of pixel arrays;
and the at least two analog signal amplifiers are respectively and electrically connected with the column reading circuits and are used for respectively amplifying pixel signals on column buses in the corresponding pixel arrays.
3. The light-sensing chip of claim 1, wherein the number of analog signal amplifiers is the same as the number of column read circuits, and the at least two pixel arrays multiplex the analog signal amplifiers.
4. A photo chip as claimed in claim 2 or 3, wherein the column read circuit comprises a correlated double sampling circuit for collecting an integrated signal and a reset signal of a pixel in any pixel array, calculating a difference between the integrated signal and the reset signal, and outputting the difference to the analog signal amplifier.
5. A photo-sensing chip according to claim 2 or 3, wherein the integrated circuit further comprises a switching circuit;
the input end of the switching circuit is electrically connected with the analog signal amplifier, and the output end of the switching circuit is electrically connected with the analog-to-digital converter and is used for switching the analog-to-digital converter connected with the analog signal amplifier.
6. The light-sensing chip of claim 5, wherein the integrated circuit further comprises a timing control circuit electrically connected to the switching circuit for generating switching pulses based on a scanning order of at least two pixel arrays and a scanning time of each pixel array, and outputting the switching pulses to the switching circuit, respectively, to control the switching circuit to be turned on or off.
7. A camera module comprising the photosensitive chip according to any one of claims 1 to 6.
8. An electronic device having the camera module of claim 7.
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| CN109842768B (en) * | 2019-01-29 | 2020-05-15 | 上海芯仑光电科技有限公司 | Pixel acquisition circuit and image sensor |
| CN110690238A (en) * | 2019-09-30 | 2020-01-14 | 芯盟科技有限公司 | Image sensor module |
| CN112399111B (en) * | 2020-10-09 | 2022-04-08 | 电子科技大学中山学院 | Shift register and CMOS solid-state imaging sensor |
| CN114615445B (en) * | 2020-11-05 | 2024-05-31 | 北京大学深圳研究生院 | Phototransistor and photosensitive method thereof |
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