CN114614808B - Power tube driving circuit - Google Patents

Power tube driving circuit Download PDF

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Publication number
CN114614808B
CN114614808B CN202210262234.8A CN202210262234A CN114614808B CN 114614808 B CN114614808 B CN 114614808B CN 202210262234 A CN202210262234 A CN 202210262234A CN 114614808 B CN114614808 B CN 114614808B
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driving
tube
control signal
module
pmos
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CN114614808A (en
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夏虎
刘桂芝
王冬峰
何云
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Wuxi Linju Semiconductor Technology Co ltd
Shanghai Nanlin Integrated Circuit Co ltd
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Wuxi Linju Semiconductor Technology Co ltd
Shanghai Nanlin Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides a power tube driving circuit, comprising: the device comprises a control module, a driving module and a comparison module, wherein the comparison module is connected to the output end of the driving module; the control module is connected to the output end of the comparison module, receives the driving control signal and outputs a first control signal and a second control signal; the driving module is connected to the output end of the control module and generates a driving signal. The power tube driving circuit can drive an NPN power tube and an NMOS power tube, and has wide use scenes; the power tube driving circuit has the advantages of simple structure, less used components, capability of being integrated in a chip and convenience for integrated application.

Description

Power tube driving circuit
Technical Field
The invention relates to the field of integrated circuit design and application, in particular to a power tube driving circuit.
Background
NPN-type power transistors and NMOS-type power transistors are 2 commonly used power semiconductor devices. Are commonly used in power supply circuits.
The NPN type power tube belongs to a triode and is a current control type device; the NMOS type power tube belongs to a metal oxide field effect tube and is a voltage control type device. The two power tubes have different characteristics and different requirements on the driving circuit. The driving circuit suitable for the NPN type power transistor cannot be generally applied to driving the NMOS type power transistor because: the parasitic capacitance of the grid electrode of the NMOS type power tube is large, and the driving circuit is required to output large current to obtain high switching speed. The output current of the driving circuit suitable for the NPN-type power transistor is generally not enough to rapidly drive the NMOS-type power transistor. The driving circuit suitable for the NMOS type power transistor generally cannot be applied to drive the NPN type power transistor because: the output current is generally large, and when the power transistor is used for driving an NPN-type power transistor, an excessive power loss is generated in a diode between a base and an emitter of the NPN-type power transistor.
Therefore, it is necessary to provide a new power transistor driving circuit, which can drive both NPN power transistors and NMOS power transistors.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a power transistor driving circuit for solving the problem that the driving circuit in the prior art cannot drive an NPN power transistor and an NMOS power transistor simultaneously.
To achieve the above and other related objects, the present invention provides a power transistor driving circuit, which at least includes: the device comprises a control module, a driving module and a comparison module;
the comparison module is connected to the output end of the drive module, compares a reference signal with a drive signal output by the drive module and outputs a comparison result;
the control module is connected to the output end of the comparison module, receives a driving control signal, and generates an effective first control signal when the driving control signal is at a first level and is smaller than the reference signal; when the driving control signal is at a first level and the driving signal is greater than the reference signal, generating an effective second control signal;
the driving module is connected to the output end of the control module and generates a driving signal based on the driving control signal, the first control signal and the second control signal; when the driving control signal is at a first level and the first control signal is effective, the driving signal is used for driving the NPN power tube to be conducted; when the driving control signal is at a first level and the second control signal is effective, the driving signal is used for driving the NMOS power tube to be conducted; when the driving control signal is at a second level, the driving signal is used for controlling the power tube to be turned off;
wherein the first level is configured to control the power tube to be turned on, and the second level is configured to control the power tube to be turned off.
Optionally, the voltage of the reference signal has a value range of [0.7V,1.5V ].
Optionally, the first level is a high level, and the second level is a low level.
Optionally, the power tube driving circuit further includes: a first inverter and a second inverter, wherein: the first inverter receives the driving control signal and outputs an inverse signal of the driving control signal; the second phase inverter is connected to the output end of the first phase inverter and provides the driving control signal for the driving module.
Optionally, the comparison module comprises a comparator, wherein: the non-inverting input end of the comparator is connected with the reference voltage, and the inverting input end of the comparator is connected with the driving signal.
Optionally, the control module comprises: first PMOS pipe, second PMOS pipe, third PMOS pipe, first NMOS pipe, second NMOS pipe and NOR gate, wherein: the source electrode of the first PMOS tube is connected with a power supply voltage, and the grid electrode of the first PMOS tube receives the driving control signal; the source electrode of the second PMOS tube is connected with a power supply voltage, and the grid electrode of the second PMOS tube receives an inverse signal of the driving control signal; the source electrode of the third PMOS tube is connected to the drain electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube and outputs the first control signal; the drain electrode of the first NMOS tube is connected to the drain electrode of the third PMOS tube, and the grid electrode of the first NMOS tube receives the driving control signal; the drain electrode of the second NMOS tube is connected to the source electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected to the reference ground, and the grid electrode of the second NMOS tube is connected with the grid electrode of the third PMOS tube and receives the comparison result; the input end of the NOR gate receives the comparison result and the inverse signal of the driving control signal respectively, and the output end of the NOR gate generates the second control signal.
Optionally, the driving module comprises: fourth PMOS pipe, fifth PMOS pipe, sixth PMOS pipe, third NMOS pipe, fourth NMOS pipe, current source, pull-up module and pull-down module, wherein: the pull-up module receives the driving control signal; the source electrode of the fourth PMOS tube is connected with a power supply voltage, and the grid electrode of the fourth PMOS tube is connected with the pull-up module; the source electrode of the fifth PMOS tube is connected with a power supply voltage, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the drain electrode of the fifth PMOS tube outputs the driving signal; the source electrode of the sixth PMOS tube is connected to the drain electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube receives the first control signal, and the drain electrode of the sixth PMOS tube is connected with the grid electrode of the fourth PMOS tube; the drain electrode of the third NMOS tube is connected to the drain electrode of the sixth PMOS tube, the grid electrode of the third NMOS tube receives the driving control signal, and the source electrode of the third NMOS tube is connected with the reference ground through the current source; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fourth NMOS tube receives a reverse signal of the driving control signal, and the source electrode of the fourth NMOS tube is connected with the reference ground; the pull-down module is connected between a reference ground and the grid electrode of the fourth PMOS tube, and the control end of the pull-down module is connected with the second control signal; when the driving control signal is at a first level and the first control signal is effective, the pull-up module and the pull-down module are both turned off to ensure that the driving signal drives the NPN power tube; when the driving control signal is at a first level and the second control signal is effective, the pull-up module is turned off and the pull-down module works to ensure that the driving signal drives the NMOS power tube; when the driving control signal is at a second level, the pull-up module works, and the pull-down module is turned off to ensure that the driving signal is turned off.
Optionally, the ratio of the width-to-length ratio of the fourth PMOS transistor to the fifth PMOS transistor is 1: and N is a natural number which is more than or equal to 2.
Optionally, the pull-up module comprises: a seventh PMOS transistor, wherein: and the source electrode of the seventh PMOS tube is connected with a power supply voltage, the grid electrode of the seventh PMOS tube receives the driving control signal, and the drain electrode of the seventh PMOS tube is connected with the grid electrode of the fourth PMOS tube.
Optionally, the pull-down module includes: a fifth NMOS transistor, wherein: and the drain electrode of the fifth NMOS tube is connected with the grid electrode of the fourth PMOS tube, the grid electrode receives the second control signal, and the source electrode is connected with the reference ground.
As described above, the power transistor driving circuit according to the present invention has the following advantages:
1) The power tube driving circuit can drive an NPN power tube and an NMOS power tube, and has wide use scenes.
2) The power tube driving circuit has the advantages of simple structure, less used components, capability of being integrated in a chip and convenience for integrated application.
Drawings
Fig. 1 is a schematic diagram of an exemplary NPN power transistor driving circuit according to the present invention.
Fig. 2 is a schematic diagram of an exemplary NMOS power transistor driving circuit according to the present invention.
Fig. 3 is a schematic diagram of a power transistor driving circuit according to an embodiment of the present disclosure.
Fig. 4 is a graph comparing the driving signal output by the power transistor driving circuit according to the embodiment of the present application with the comparison result.
Description of the element reference numerals
100. Control module
200. Drive module
201. Pull-up module
202. Pull-down module
300. Comparison module
301. Comparator with a comparator circuit
Detailed Description
The embodiments of the present invention are described below with specific examples, and other advantages and effects of the present invention will be apparent to those skilled in the art from the disclosure of the present invention. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Fig. 1 shows a driving circuit suitable for an NPN power transistor, and the operating principle thereof is as follows:
as shown in fig. 1, when the input signal input is at a high level, the output signal ng11 of the inverter inv11 (inv 11 for short) is at a low level, and the NMOS transistor N11 (N11 for short) is turned off.
As shown in fig. 1, when the input signal input is at a high level, the NMOS transistor N12 (abbreviated as N12) is turned on, and the current passing through the PMOS transistor P12 (abbreviated as P12) is equal to the current value I11 output by the current source I11. The PMOS transistors P11 (P11 for short) and P12 form a current mirror, and the ratio of the width-to-length ratios of the P11 to the P12 is m:1, so that the drain current of the P11 is m multiplied by I11, wherein m is a natural number which is more than or equal to 2, and the drain current of the P11 does not change along with the change of the voltage value of the supply voltage VDD.
As shown in fig. 1, the drain current of P11 enters the base of NPN power transistor Q1 (Q1 for short), turning on Q1.
As shown in fig. 1, when Q1 is on, the base voltage is generally about 0.7V, which is the voltage when the diode between the base and emitter is on in the forward direction.
As shown in fig. 1, when the input signal input is low, N12 is turned off, the current passing through P12 is 0, and the leakage current of P11 is 0. The output signal ng11 of inv11 is high, N11 is on, the base of Q1 is pulled down to 0, and Q1 is off.
As shown in fig. 1, the P11 drain current is used to drive Q1. In design, the P11 drain output current needs to be limited, because a large base current brings large power loss, which on one hand results in a reduction in system efficiency, and on the other hand results in an increase in heat generation, possibly burning out Q1.
However, the driving circuit suitable for the NPN power transistor shown in fig. 1 cannot be generally applied to driving an NMOS power transistor because the gate parasitic capacitance of the NMOS power transistor is large, and the driving circuit is required to output a large current to obtain a fast switching speed. The output current of the driving circuit suitable for the NPN power tube is generally not enough to rapidly drive the NMOS power tube.
Fig. 2 shows a driving circuit suitable for an NMOS power transistor, which works according to the following principle:
as shown in fig. 2, when the input signal input is at a high level, the output signal ng22 of the inverter inv22 (inv 22 for short) is at a low level, and the NMOS transistor N22 (N22 for short) is turned off; the output signal pg22 of the inverter inv21 (referred to as inv21 for short) is at low level, and the PMOS transistor P21 (referred to as P21 for short) is turned on. The NMOS power transistor N21 (abbreviated as N21) is turned on, and its gate voltage is pulled up to be equal to the supply voltage VDD. When P21 is turned on, the gate signal pg22 is pulled down to 0, and the voltage difference between the source and the gate is equal to the supply voltage VDD, so that a large current can be output to rapidly drive N21.
As shown in fig. 2, when the input signal input is low, ng22 is high, and N22 is turned on; pg22 is high and P21 is off. N21 is turned off and its gate voltage is pulled down to 0.
However, the driving circuit for NMOS power transistor shown in fig. 2 cannot be generally applied to driving NPN power transistor, because when P21 is turned on, its gate signal pg22 is pulled down to 0, its output current is generally large, and when driving NPN power transistor, it will generate excessive power loss on the diode between the base and emitter of NPN power transistor. When the P21 is turned on, the gate voltage is pulled down to 0, and the current output by the P21 will change along with the voltage change of the supply voltage VDD, so that the base current is not limited along with the change of the supply voltage VDD, and the NPN power tube is burnt.
Therefore, the present invention provides a power transistor driving circuit, which comprises:
as shown in fig. 3, the present embodiment provides a power transistor driving circuit, which includes: a control module 100, a driving module 200 and a comparing module 300.
As shown in fig. 3, the comparing module 100 is connected to the output end of the driving module 200, and compares the reference signal Vr with the driving signal output from the driving module 200 and outputs a comparison result cmp31.
Specifically, as an example, as shown in fig. 3, the comparing module 300 includes a comparator 301, wherein: the non-inverting input terminal of the comparator 301 is connected to the reference voltage Vr, and the inverting input terminal is connected to the driving signal output. It should be noted that the non-inverting input terminal and the inverting input terminal of the comparator 301 should be set in consideration of an actual use scenario, and are not limited to this embodiment.
Specifically, as shown in fig. 4, as an example, the voltage value range of the reference signal Vr is [0.7V,1.5V ], it should be noted that when an NPN power tube is turned on, the base voltage thereof is the voltage when a diode between the base and the emitter is turned on in the forward direction, and is generally about 0.7V, and when the voltage value of the drive signal output exceeds the voltage value of the reference signal Vr, the comparison result cmp31 is turned from the high level to the low level; the threshold voltage of the NMOS power tube is generally 1.5V-2.5V. When the grid voltage is smaller than the threshold voltage, the NMOS power tube is turned off; when the grid voltage is larger than the threshold voltage, the NMOS power tube is conducted. When the NMOS power tube is conducted, the higher the grid voltage is, the smaller the conducting resistance is. In the process of the gate voltage rising, a large power loss is generated, so that the driving circuit needs to be ensured to output a large current during design, so that the gate rises quickly. Further, the voltage value range of the reference signal Vr includes but is not limited to [0.7v,1.5v ], which should be set according to the actual device and the usage scenario, and is not limited by this embodiment.
As shown in fig. 3, the control module 100 is connected to the output terminal of the comparison module 300, and receives a driving control signal input, and generates an active first control signal con1 when the driving control signal input is at a first level and the driving signal output is less than the reference signal Vr; when the driving control signal input is at the first level and the driving signal output is greater than the reference signal Vr, an active second control signal con2 is generated. Specifically, as an example, as shown in fig. 3, the first level is a high level, and the second level is a low level. The first level may be a low level, and the second level may be a high level, which should be set according to an actual usage scenario, but is not limited to this embodiment.
Specifically, as an example, as shown in fig. 3, the control module 100 includes: first PMOS pipe P1, second PMOS pipe P2, third PMOS pipe P3, first NMOS pipe N1, second NMOS pipe N2 and NOR gate Nor, wherein: the source electrode of the first PMOS tube P1 is connected with a power supply voltage VDD, and the grid electrode of the first PMOS tube P1 receives the driving control signal input; the source electrode of the second PMOS tube P2 is connected with a power supply voltage VDD, and the grid electrode of the second PMOS tube P2 receives a reverse signal input _ inv of the driving control signal; the source electrode of the third PMOS transistor P3 is connected to the drain electrode of the second PMOS transistor P2, and the drain electrode is connected to the drain electrode of the first PMOS transistor P1 and outputs the first control signal con1; the drain electrode of the first NMOS transistor N1 is connected to the drain electrode of the third PMOS transistor P3, and the gate electrode receives the drive control signal input; the drain electrode of the second NMOS tube N2 is connected to the source electrode of the first NMOS tube N1, the source electrode is connected with the reference ground, and the grid electrode of the second NMOS tube N2 is connected with the grid electrode of the third PMOS tube P3 and receives the comparison result cmp31; the Nor gate Nor has an input terminal receiving the comparison result cmp31 and the inverse signal input _ inv of the driving control signal, and an output terminal generating the second control signal con2.
Specifically, as shown in fig. 3, the power tube driving circuit further includes: a first inverter inv1 and a second inverter inv2, wherein: the first inverter inv1 receives the drive control signal input, and outputs an inverted signal input _ inv of the drive control signal; the second inverter inv2 is connected to the output end of the first inverter inv1, and provides the drive control signal input for the drive module. It should be noted that, whether the inverter is set or not and the number of the inverters should be determined according to the actual usage scenario, and is not limited to this embodiment.
Specifically, as shown in fig. 3, the driving module 200 includes, as an example: a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, a fourth NMOS transistor N4, a current source Ig, a pull-up module 201, and a pull-down module 202, wherein: the pull-up module 201 receives the driving control signal input; the source electrode of the fourth PMOS transistor P4 is connected to a supply voltage VDD, and the gate electrode is connected to the pull-up module 201; the source electrode of the fifth PMOS tube P5 is connected with a power supply voltage VDD, the grid electrode of the fifth PMOS tube P5 is connected with the grid electrode of the fourth PMOS tube P4, and the drain electrode of the fifth PMOS tube P5 outputs the driving signal output; the source electrode of the sixth PMOS transistor P6 is connected to the drain electrode of the fourth PMOS transistor P4, the gate electrode of the sixth PMOS transistor P6 receives the first control signal con1, and the drain electrode of the sixth PMOS transistor P6 is connected to the gate electrode of the fourth PMOS transistor P4; the drain of the third NMOS transistor N3 is connected to the drain of the sixth PMOS transistor P6, the gate receives the driving control signal input, and the source is connected to the ground through the current source Ig; the drain electrode of the fourth NMOS transistor N4 is connected to the drain electrode of the fifth PMOS transistor P5, the gate electrode receives the inverse signal input _ inv of the driving control signal, and the source electrode is connected to the reference ground; the pull-down module 202 is connected between a reference ground and the gate of the fourth PMOS transistor P4, and a control end is connected to the second control signal con2; when the driving control signal input is at a first level and the first control signal con1 is valid, the pull-up module 201 and the pull-down module 202 are both turned off to ensure that the driving signal output drives the NPN power transistor; when the driving control signal input is at a first level and the second control signal con2 is valid, the pull-up module 201 is turned off, and the pull-down module 202 operates to ensure that the driving signal output drives the NMOS power transistor; when the driving control signal input is at the second level, the pull-up module 201 operates, and the pull-down module 202 is turned off to ensure that the driving signal output is turned off.
More specifically, as shown in fig. 3, as an example, the ratio of the width-to-length ratio of the fourth PMOS transistor P4 to the fifth PMOS transistor P5 is 1: and N is a natural number which is more than or equal to 2. It should be noted that the current passing through the fourth PMOS transistor P4 is determined by the output current of the current source Ig, and when the NPN power transistor is driven by the driving signal output, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 form a current mirror, so that the drain current output by the fifth PMOS transistor P5 is nxig, and the drain current of the fifth PMOS transistor P5 does not change with the change of the voltage value of the power supply voltage VDD.
More specifically, as shown in fig. 3, by way of example, the pull-up module 201 includes: a seventh PMOS transistor P7, wherein: the source electrode of the seventh PMOS transistor P7 is connected to a supply voltage VDD, the gate electrode receives the driving control signal input, and the drain electrode is connected to the gate electrode of the fourth PMOS transistor P4. It should be noted that the arrangement manner of the pull-up module 201 includes, but is not limited to, the seventh PMOS transistor P7, and any module that performs a pull-up function is applicable, and is not limited to this embodiment.
More specifically, as an example, as shown in fig. 3, the pull-down module 202 includes: a fifth NMOS transistor N5, wherein: the drain of the fifth NMOS transistor N5 is connected to the gate of the fourth PMOS transistor P4, the gate receives the second control signal con2, and the source is connected to ground. It should be noted that the setting manner of the pull-down module 202 includes, but is not limited to, the fifth NMOS transistor N5, and any module that performs a pull-down function is applicable, which is not limited to this embodiment.
Further, as shown in fig. 3, for example, when the driving control signal input is at a high level and the comparison result cmp31 is at a high level, the first control signal con1 is at a low level (active) and the second control signal con2 is at a low level, so that the sixth PMOS transistor P6 is turned on, and the third NMOS transistor N3 is also turned on, so that the current output by the current source Ig passes through the fourth PMOS transistor P4, the sixth PMOS transistor P6 and the third NMOS transistor N3, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 form a current mirror, and the ratio of the width-to-length ratio of the fourth PMOS transistor P4 to the fifth PMOS transistor P5 is 1: n, the drain current passing through the fifth PMOS transistor P5 is nxig, the drain current of the fifth PMOS transistor P5 does not change with the voltage value change of the power supply voltage VDD, and the driving signal output drives the NPN power transistor. When the fifth PMOS transistor P5 is turned on and the fourth NMOS transistor N4 is turned off, the diode between the base and the emitter of the NPN power transistor is turned on, the driving signal output is clamped at about 0.7V, and the voltage of the driving signal output is lower than the reference voltage Vr at the non-inverting input terminal of the comparator 301, so that the comparison result cmp31 output by the comparator 301 maintains a high level.
As shown in fig. 3, when the driving control signal input is at a high level, the fifth PMOS transistor P5 is turned on. When the power transistor connected to the driving signal output terminal is an NMOS power transistor, the voltage of the driving signal output terminal is increased and greater than the reference voltage Vr at the non-inverting input terminal of the comparator 301, so that the comparison result cmp31 output by the comparator 301 becomes a low level. The first control signal con1 is at a high level, and the second control signal con2 is at a high level (active), so that the sixth PMOS transistor P6 is turned off, the fifth NMOS transistor N5 is turned on, and the gate voltage pg45 of the fifth PMOS transistor P5 is rapidly pulled down to a low level, so that the fifth PMOS transistor P5 is turned on and outputs a large current, and the voltage of the driving signal output is rapidly raised to the power supply voltage VDD to drive the NMOS power transistor.
As shown in fig. 3, when the driving control signal input is at a low level, the seventh PMOS transistor P7 is turned on, the fifth PMOS transistor P5 is turned off, and the fourth NMOS transistor N4 is turned on, so that the driving signal output is pulled down to a low level to turn off the NPN power transistor or the NMOS power transistor.
In summary, the present invention provides a power transistor driving circuit, which includes: the device comprises a control module, a driving module and a comparison module; the comparison module is connected to the output end of the drive module, compares a reference signal with a drive signal output by the drive module and outputs a comparison result; the control module is connected to the output end of the comparison module, receives a driving control signal, and generates an effective first control signal when the driving control signal is at a first level and is smaller than the reference signal; when the driving control signal is at a first level and the driving signal is greater than the reference signal, generating an effective second control signal; the driving module is connected to the output end of the control module and generates a driving signal based on the driving control signal, the first control signal and the second control signal; when the driving control signal is at a first level and the first control signal is effective, the driving signal is used for driving the NPN power tube to be conducted; when the driving control signal is at a first level and the second control signal is effective, the driving signal is used for driving the NMOS power tube to be conducted; when the driving control signal is at a second level, the driving signal is used for controlling the power tube to be turned off; wherein the first level is configured to control the power tube to be turned on, and the second level is configured to control the power tube to be turned off. The power tube driving circuit can drive an NPN power tube and an NMOS power tube, and is wide in use scene. The power tube driving circuit has the advantages of simple structure, less used components, capability of being integrated in a chip and convenience for integrated application. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (9)

1. A power tube driving circuit, characterized in that, the power tube driving circuit at least includes: the device comprises a control module, a driving module and a comparison module;
the comparison module is connected to the output end of the drive module, compares a reference signal with a drive signal output by the drive module and outputs a comparison result;
the control module is connected to the output end of the comparison module, receives a driving control signal, and generates an effective first control signal when the driving control signal is at a first level and is smaller than the reference signal; when the driving control signal is at a first level and the driving signal is greater than the reference signal, generating an effective second control signal, wherein the voltage value range of the reference signal is [0.7V,1.5V ];
the driving module is connected to the output end of the control module and generates a driving signal based on the driving control signal, the first control signal and the second control signal; when the driving control signal is at a first level and the first control signal is effective, the driving signal is used for driving the NPN power tube to be conducted; when the driving control signal is at a first level and the second control signal is effective, the driving signal is used for driving the NMOS power tube to be conducted; when the driving control signal is at a second level, the driving signal is used for controlling the power tube to be turned off;
wherein the first level is configured to control the power tube to be turned on, and the second level is configured to control the power tube to be turned off.
2. The power tube driving circuit according to claim 1, wherein: the first level is a high level and the second level is a low level.
3. The power transistor driving circuit of claim 1, wherein: the power tube driving circuit further comprises: a first inverter and a second inverter, wherein: the first inverter receives the driving control signal and outputs an inverse signal of the driving control signal; the second phase inverter is connected to the output end of the first phase inverter and provides the driving control signal for the driving module.
4. The power transistor driving circuit of claim 1, wherein: the comparison module comprises a comparator, wherein: the non-inverting input end of the comparator is connected with the reference signal, and the inverting input end of the comparator is connected with the driving signal.
5. The power tube driving circuit according to any one of claims 1-4, wherein: the control module includes: first PMOS pipe, second PMOS pipe, third PMOS pipe, first NMOS pipe, second NMOS pipe and NOR gate, wherein: the source electrode of the first PMOS tube is connected with a power supply voltage, and the grid electrode of the first PMOS tube receives the driving control signal; the source electrode of the second PMOS tube is connected with a power supply voltage, and the grid electrode of the second PMOS tube receives a reverse signal of the driving control signal; the source electrode of the third PMOS tube is connected to the drain electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube and outputs the first control signal; the drain electrode of the first NMOS tube is connected to the drain electrode of the third PMOS tube, and the grid electrode of the first NMOS tube receives the driving control signal; the drain electrode of the second NMOS tube is connected to the source electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected to the reference ground, and the grid electrode of the second NMOS tube is connected with the grid electrode of the third PMOS tube and receives the comparison result; the input end of the NOR gate receives the comparison result and the inverse signal of the driving control signal respectively, and the output end of the NOR gate generates the second control signal.
6. The power tube driving circuit according to any one of claims 1-4, wherein: the driving module includes: fourth PMOS pipe, fifth PMOS pipe, sixth PMOS pipe, third NMOS pipe, fourth NMOS pipe, current source, pull-up module and pull-down module, wherein: the pull-up module receives the drive control signal; the source electrode of the fourth PMOS tube is connected with a power supply voltage, and the grid electrode of the fourth PMOS tube is connected with the pull-up module; the source electrode of the fifth PMOS tube is connected with a power supply voltage, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the drain electrode of the fifth PMOS tube outputs the driving signal; the source electrode of the sixth PMOS tube is connected to the drain electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube receives the first control signal, and the drain electrode of the sixth PMOS tube is connected with the grid electrode of the fourth PMOS tube; the drain electrode of the third NMOS tube is connected to the drain electrode of the sixth PMOS tube, the grid electrode of the third NMOS tube receives the driving control signal, and the source electrode of the third NMOS tube is connected with the reference ground through the current source; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fourth NMOS tube receives a reverse signal of the driving control signal, and the source electrode of the fourth NMOS tube is connected with the reference ground; the pull-down module is connected between a reference ground and the grid electrode of the fourth PMOS tube, and the control end of the pull-down module is connected with the second control signal; when the driving control signal is a first level and the first control signal is valid, the pull-up module and the pull-down module are both turned off to ensure that the driving signal drives the NPN power tube; when the driving control signal is at a first level and the second control signal is effective, the pull-up module is turned off and the pull-down module works to ensure that the driving signal drives the NMOS power tube; when the driving control signal is at a second level, the pull-up module works, and the pull-down module is turned off to ensure that the driving signal is turned off.
7. The power transistor driving circuit of claim 6, wherein: the ratio of the width to length ratio of the fourth PMOS tube to the fifth PMOS tube is 1: and N is a natural number which is more than or equal to 2.
8. The power tube driving circuit according to claim 6, wherein: the drawing-up module includes: a seventh PMOS transistor, wherein: and the source electrode of the seventh PMOS tube is connected with a power supply voltage, the grid electrode of the seventh PMOS tube receives the driving control signal, and the drain electrode of the seventh PMOS tube is connected with the grid electrode of the fourth PMOS tube.
9. The power tube driving circuit according to claim 6, wherein: the pull-down module includes: a fifth NMOS transistor, wherein: and the drain electrode of the fifth NMOS tube is connected with the grid electrode of the fourth PMOS tube, the grid electrode receives the second control signal, and the source electrode is connected with the reference ground.
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