CN114597186A - 芯片模块，芯片模块的用途，测试布置和测试方法 - Google Patents

芯片模块，芯片模块的用途，测试布置和测试方法 Download PDF

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CN114597186A
CN114597186A CN202111458775.XA CN202111458775A CN114597186A CN 114597186 A CN114597186 A CN 114597186A CN 202111458775 A CN202111458775 A CN 202111458775A CN 114597186 A CN114597186 A CN 114597186A
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China
Prior art keywords
chip
contact layer
chip module
upper side
conductive adhesive
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CN202111458775.XA
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S.多布里茨
C.芬德森
M.皮耶谢尔
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First Sensor AG
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First Sensor AG
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Abstract

一种芯片模块包括：芯片(1)，具有前侧(11)和后侧(12)；芯片载体(2)，具有面向芯片(1)的上侧(21)；接触层(3)，由导电材料形成且在芯片(1)的后侧(12)和芯片载体(2)的上侧(21)之间布置在芯片载体(2)的上侧(21)上；以及导电粘合剂(4)，布置在接触层(3)的面向芯片(1)的上侧(321)上。导电粘合剂(4)连接接触层(3)的上侧(321)和芯片(1)的后侧(12)。接触层(3)具有多个区域(3A，3B)，多个区域彼此电隔离且各自通过导电粘合剂(4)电连接到芯片(1)。

Description

芯片模块，芯片模块的用途，测试布置和测试方法
技术领域
本申请涉及芯片模块、这样的芯片模块的用途、测试芯片模块的接触的测试布置，以及测试芯片模块的接触的测试方法。
背景技术
半导体部件通常使用晶片或芯片的前侧来布置导电有源元件。这些半导体部件安装在芯片载体上并且电接触芯片载体。许多这些半导体部件需要在芯片的后侧上制作导电接触件。为了确保良好的电接触，晶片背面通常被金属化，通常是通过具有最终金表面的金属夹层。
芯片和芯片载体之间的连接必须完成两个基本功能。在这种情况下，一方面，必须建立足够的机械连接以在部件的使用条件下确保强度，特别是粘合强度。此外，这种连接应确保在使用条件下稳定的电连接。这两种功能的结合对粘合连接或者焊接或烧结连接提出了很高的要求。
发明内容
一种芯片模块包括：芯片，具有前侧和后侧；芯片载体，具有面向芯片的上侧；接触层，由导电材料形成且在芯片的后侧和芯片载体的上侧之间布置在芯片载体的上侧上；以及导电粘合剂，布置在接触层的面向芯片的上侧上。导电粘合剂连接接触层的上侧和芯片的后侧。接触层具有多个区域，多个区域彼此电隔离且各自通过导电粘合剂电连接到芯片。
附图说明
现在将参照附图以举例的方式描述本发明，在附图中：
图1是根据实施例的芯片模块的示意性平面图；
图2是不具有芯片的图1的芯片模块的剖视侧视图；
图3是具有导电粘合剂的图2的芯片模块的剖视侧视图；
图4是具有芯片的图3的芯片模块的剖视侧视图；
图5是具有壳体的图4的芯片模块的剖视侧视图；
图6是具有焊球的图5的芯片模块的剖视侧视图；
图7是根据另一实施例的芯片模块的示意性平面图；
图8是不具有芯片的图7的芯片模块的剖视侧视图；
图9是具有导电粘合剂的图8的芯片模块的剖视侧视图；
图10是具有芯片的图9的芯片模块的剖视侧视图；
图11是具有壳体的图11的芯片模块的剖视侧视图；
图12是具有焊球的图12的芯片模块的剖视侧视图；
图13是根据另一实施例的芯片模块的示意性平面图；
图14是不具有芯片的图13的芯片模块的剖视侧视图；
图15是具有非导电粘合剂的图14的芯片模块的剖视侧视图；
图16是具有芯片的图15的芯片模块的剖视侧视图；
图17是具有导电粘合剂的图16的芯片模块的剖视侧视图；
图18是具有壳体的图17的芯片模块的剖视侧视图；
图19是根据实施例的具有芯片模块的测试布置的示意性剖视侧视图；
图20是根据另一实施例的具有芯片模块的测试布置的示意性剖视侧视图；
图21是根据另一实施例的具有芯片模块的测试布置的示意性剖视侧视图；以及
图22是根据另一实施例的具有芯片模块的测试布置的示意性剖视侧视图。
具体实施方式
下面将参考附图更详细地解释本发明。相同的部件具有相同的附图标记和相同的部件名称。此外，来自所示和描述的不同实施例的一些特征或特征的组合本身可以代表根据本发明的独立的解决方案。重复出现的特征具有相同的附图标记。
图1以平面图示出了芯片模块的示意图。芯片模块包括芯片1，其在图1中用虚线勾画出来并且透明地示出，以便揭示下面的结构。另外，芯片模块包括芯片载体2，在芯片载体2的上侧21布置有接触层3。接触层3是导电的。
接触层3包括至少三个，且在所示的实施例中为四个区域3A、3B、3C、3D，在所示的实施例中，它们彼此电隔离。在本示例中，彼此电隔离的区域3A至3D是矩形的。在其他示例中，这些区域3A至3D也可以具有其他形状，例如正方形、圆形、椭圆形或这些形状的组合。区域3A至3D均凸出超过芯片1。在其他实施例中，接触层3可以具有多于四个互相隔离的区域。彼此隔离的区域也可以称为接触区域。
在一个实施例中，芯片1的长度可以至少为1mm，至少1.5mm，或至少2mm。附加地或替代地，芯片1的长度至多为200mm，至多100mm，或至多50mm。然而，也可以处理具有更大尺寸的芯片1。在一个实施例中，芯片1的宽度可以至少为1mm，至少1.5mm，或至少2mm。附加地或替代地，芯片1的宽度可以至多为200mm，至多100mm，或至多50mm。
在图1所示的实施例中，芯片1具有8mm的宽度B1和15mm的长度L1。接触层3具有17mm的长度L3和10mm的宽度B3。彼此隔离的各个区域3A-3D具有相同的尺寸。每个区域3A至3D具有7.5mm的长度L3A和4mm的宽度B3A。
在本情形中，芯片1可以理解为意味着微电子部件，特别是半导体芯片或微***。芯片1具有前侧11和后侧12。前侧11通常承载有源半导体结构。芯片1可以在其后侧上具有电接触件，例如用于为集成在芯片中的电气部件或微***提供电压，和/或用于与电气部件和/或微***通信。附加地或替代地，芯片1可以在其前侧上具有另外的电气接触件。
在本示例中，芯片载体2包括FR4或其衍生物。FR4是印刷电路板基材，例如玻璃纤维增强环氧树脂层压材料。由陶瓷构成或包括陶瓷的实施例也是可能的。允许通孔镀覆件31的通孔设置在芯片载体2中。在每个相互绝缘的区域3A至3D中，接触层3具有镀覆通孔31，其将布置在芯片载体2的上侧21上的接触表面32连接到芯片载体2的底侧22。这可以具有以下优点：彼此隔离的每个区域3A至3D可以经由镀覆通孔31彼此独立地进行电控制。在芯片2的底侧上，接触层3在镀覆通孔31的下端具有焊接表面33，如图2所示。
在一个实施例中，芯片1和接触层3对中地布置，使得接触层3的上侧的表面中心点距芯片1的后侧12的表面中心点最小距离。接触层3包括彼此电隔离的区域3A-3D，使得接触层3的表面由彼此电隔离的区域的外边缘限定。以此方式限定的接触层3的表面的中心点因此位于彼此隔离的区域3A–3D之一中，也可以在位于彼此隔离的区域3A–3D之间的区域中。
导电粘合剂4布置在接触层3的上侧上-更确切地，在相应的接触表面32的上侧321中的每一个上。这在图3中示出，其基本上对应于图2，但是还示出了粘合剂4的布置。在图3中，可以看出，粘合剂4布置在接触表面32的上侧321上，使得彼此隔离的区域不会与粘合剂接触。在实施例中，导电银粘合剂被选择为导电粘合剂4。在本情形中，导电粘合剂4可以包括焊接连接或烧结层，或可以设计为焊接连接或烧结连接。
接触层4可以例如包括金和/或其他贵金属和/或其他金属。导电粘合剂4可以包括例如一种聚合物或几种聚合物，例如环氧树脂、丙烯酸酯、硅胶、聚氨酯和/或酯。导电粘合剂4可以包括银颗粒和/或一种或多种其他导电物质，例如石墨。导电物质可以特别地嵌入(多种)聚合物中。
图4示出了图2和图3的芯片模块的剖视图，芯片1也被示出。芯片1的后侧12搁置在导电粘合剂层4上。以此方式，彼此隔离的区域可以接触芯片的后侧12的不同区域。芯片1的布置在后侧12上的接触件因此可以经由导电粘合剂4电连接到接触表面32、镀覆通孔31和焊接表面33。
图5示出了图4的剖视图，壳体5也以灌封壳体的形式示出。在所示的示例中，壳体5包括基于环氧树脂的灌封。在其他示例中，壳体5可以包括其他材料，例如注射模制材料、油漆和涂层，以及模塑料。模塑料可以是塑料注射模制化合物的复合物。壳体5至少部分地，并且在实施例中完全地围封芯片1和接触层3，特别是接触层3的彼此电隔离的区域。壳体5可以特别地布置在芯片载体的上侧上。壳体5可以包括盖和/或框架和/或窗和/或窗玻璃。壳体5可以保护芯片1和接触层3免受污染和/或冲击。
如图5所示的壳体5具有光学窗口51。光学窗口51布置在芯片1的前侧11上，使得其可以例如用于LIDAR传感器中。LIDAR传感器用于光检测和测距，其中通过光来确定距离。壳体5可以例如包括一个或多个窗玻璃。另外，壳体5可以包括光源，例如辐射器、激光器芯片和/或另外的芯片，例如温度传感器。光源，例如以辐射器、激光器芯片和/或另外的芯片的形式，例如温度传感器，可以附加地或替代地安装在壳体5上。
在图6中，焊球34附加层地布置在焊接表面33上。在另一实施例中，焊球34可以布置为焊接表面33的替代物。这样的优点是，芯片模块可以布置在具有相应布置的接触件的电路板上，并且以简单的方式与这些接触件连接，例如通过将焊接表面33和/或焊球34与接触件融合，例如以形成所谓的球栅阵列。在较大的芯片或壳体边缘长度，不同的热膨胀会具有较大的影响。布置成矩阵的焊球或焊球阵列(BGA)可以用于减少热机应力。
芯片模块可以包括一个或多个另外的芯片1。关于芯片2之一描述的本申请的特征可以类似地应用于至少一个另外的芯片，或多个另外的芯片。在芯片模块包括多个芯片1的一个实施例中，芯片1可以具有不同的特性。例如，可以提供一个或多个传感器芯片、用于信号评估的ASIC、一个或多个温度传感器、和/或一个或多个LED作为光源。相同类型的芯片也可以内置在芯片模块中。
在一个实施例中，芯片模块可以包括钝化。芯片模块可以通过钝化保护免受环境影响。钝化可以是，例如，施加在整个表面或其一部分上的漆、保形涂层、灌封、球形顶部、底部填充物或模塑料。保形涂层适应下面的表面结构，球形顶部覆盖或完全包裹键合连接或芯片，并且可以由塑料材料形成。底部填充物是一种在芯片1和芯片载体之间流动并将它们结合在一起的聚合物；底部填充物可以作为额外的机械固定和/或用于填充腔。
图7示出了基本上对应于图1至图5的芯片模块，芯片1的横向尺寸大于接触层3的横向尺寸。因此，芯片1突出超过接触表面3的外边缘。图7-10示出了图6的截面图。芯片模块的结构对应于图1-5中的芯片模块的结构，使得图7-12中的实施例基本上对应于图2-5中的示例实施例，其中芯片1和接触表面32的横向尺寸不同于图1-5中的示例中的横向尺寸。芯片1和接触区域32的横向尺寸设计为使得芯片1突出超过接触区域3的边缘并覆盖它们。
图7-12所示的芯片1具有20mm的宽度B1和40mm的长度L1。接触层3具有20mm的长度L3和10mm的宽度B3。彼此隔离的各个区域3A-3D具有相同的尺寸。每个区域3A至3D具有8mm的长度L3A和4mm的宽度B3A。关于图8至图12的另外的特征，因此参考图2-6的附图描述，其中相同的附图标记指代相同的元件。
在非常小的芯片1的情况下(尤其是边缘长度小于2mm的芯片)，使接触层3大于芯片2可能在技术上更有利。另一方面，在非常大的芯片的情况下，可以有利地选择接触层边缘长度小于芯片边缘长度，使得不同的膨胀行为的影响较小。
图13至18以示意图示出了另外的实施例。在图13中，芯片模块以平面图示出。图14至18沿着剖面线A-A以剖视图示出了芯片模块，其中图14中仅示出了芯片载体2和具有镀覆通孔31’和焊接表面33’的接触层3’。图13至18的芯片模块基本上对应于图1至5的芯片模块，重复出现的特征具有相同的附图标记。
图13至18的接触层3’，和相互隔离的区域3A至3D、镀覆通孔31’和焊接表面33’，与前述实施例的接触层3的不同之处在于通道35的存在，特别是从接触层3’的上侧延伸到焊接表面33’的底侧的通孔的形式。
图15对应于图14，还示出了非导电粘合剂6。非导电粘合剂6布置在相互隔离的区域3A至3D的上侧上的子区域中。非导电粘合剂6形成基本矩形的层，其相对于芯片1和接触层3’居中。非导电粘合剂6布置在芯片1和接触层3之间。非导电粘合剂6的胶印图案的轮廓设计为使得同心通道35不被覆盖并且彼此不电连接。非导电粘合剂6可以例如由未填充或填充的聚合物构成，填充物是不导电的。这些填充物可以是无机的，例如氧化硅或氧化铝，或进而是聚合物。非导电粘合剂6可以特别是无气泡的，即没有空气夹杂物。
芯片1也在图16中示出。在图17中，导电粘合剂4布置在接触层3’上的区域中和通道35中。芯片模块的底侧，特别是芯片载体2的底侧22，因此经由焊接表面33’和经由电粘合剂4电连接到芯片后侧12。图18示出了图17的剖视图，芯片模块也具有壳体5。壳体5对应于先前的实施例的壳体5。
传感器可以包括根据上述实施例的芯片模块。根据前述实施例的芯片模块特别可以用于光学传感器，特别是LIDAR传感器。例如，这些可用于车辆信息或安全***，例如距离警告***，以及自动驾驶领域。
图19示出了测试布置，其具有布置在芯片载体2的上侧上的接触区域3。测试布置用于监测芯片1接触件和/或用于定位芯片1接触件中的缺陷。测试布置以剖视图示意性地示出。导电粘合剂4布置在接触表面3的上侧上。芯片1布置在导电粘合剂层4的上侧上，并且其横向尺寸小于凸出超过芯片1的接触表面3。接触层3被划分为彼此相互电隔离的四个区域3A、3B、3C、3D。电连接元件7-在所示的示例中为第一接触针71和第二接触针72-各自分别与区域3A和3B接触。接触针71和72连接到用于测量第一接触针71和第二接触针72之间的测试电流8的电流计A或电流测量装置。示出了测试电流8的流动。
图20示出了用于测量电连接元件7之间的测试电流的另一可能性。图20的测试布置包括根据图5的芯片模块。电连接元件7各自电连接到焊接表面33，使得测试电流8可以由电流计A发送和测量。
图21示出了根据先前附图的测试布置，测试布置包括根据图6的芯片模块。电连接元件7电连接到焊球3。
图22示出了基本上对应于先前附图的测试布置。芯片载体2还具有电接触元件10，其包括上接触表面101、镀覆通孔102和下焊接表面103。上接触表面101布置在芯片载体2的上侧21上。下焊接表面22布置在芯片载体2的底侧22上。镀覆通孔102布置在通道35中，特别是芯片载体2中的通孔中，并且将接触表面101电连接到焊接表面103。在芯片1的上侧上，芯片1的前侧接触件经由键合线9电连接到上接触表面101。电连接元件7分别经由焊球34和104电连接到焊接表面33或焊接表面103，使得测试电流8可以通过电流计A发送和测量。在这种情况下，到芯片后侧12的电流通过键合线9经由芯片1和经由前侧接触件测量。
应当注意的是，图20至22的测试布置示出了芯片模块，其镀覆通孔31未设置有对应于图13至18中所示的通道35的通道35。当然，所述的测试布置可以替代地包括根据图13-18的芯片模块。图19至22中芯片模块的图示不应被解释为限制性的，而是作为示例。
图19-22的每个测试布置包括电压源U。当然，先前的附图的任何测试布置也可以包括该电压源U。所示出的测试布置适于进行测试方式来监测芯片接触和/或用于定位芯片接触的缺陷，特别是芯片接触的缺陷区域。
首先，测量第一和第二连接元件7之间的测试电流8，例如第一和第二接触针71、72的测试电流8。测量的测试电流8然后可以与预定义的阈值进行比较。如果测量值大于阈值，则表明存在缺陷。可以在另外的连接元件7之前测量另外的测试电流8。测试电流8可以各自与阈值或与彼此进行比较。通过将测量值分配给接触层3的位置来定位缺陷。
可以规定在确定的平均值周围定义容差范围。可以规定，在容差范围之外的测试电流8表明存在缺陷。芯片1的局部区域可以分配给这些确定的测试电流8。警告信号可以指示芯片1的局部区域有缺陷接触件。
电阻可以首先从测量的测试电流8计算。可以将计算出的电阻与阈值进行比较。与阈值的偏差可以指示相应的接触件中的缺陷。可以向更高级别的***或用户输出警告信号。例如，限制为100Ω。
导电粘合剂4可以特别地具有在低欧姆范围内的阈值。在发生故障时，电接触件的阈值可以在兆欧或千兆欧范围内。芯片1的后侧上的电接触件的电阻通常在较低的欧姆范围内。根据后侧上的芯片面积，这些通常小于1ohm。
如果到芯片的后侧的连接故障，则电阻可以增加1000到1,000,000倍或更多。这种增加可以容易地通过电子方式检测到。当使用石墨或铝填充的粘合剂时，它们通常导电性较差。然后它们大多在千欧到兆欧范围内。阈值还可以取决于环境影响，例如湿度。
阈值因此可以是产品特定的。特别地，阈值可以至少为0.1Ω，至少0.5Ω，或至少1Ω。阈值可以小于100MΩ，小于100kΩ，或小于100Ω。
可以通过重复和比较测量来预测错误。为此，例如，可以将第一次测量的测试电流与在稍后时间点测量的第二测试电流进行比较。在相同的绝缘区域之间或相同的绝缘区域与芯片载体的电接触元件之间测量第一和第二测试电流。
测试方法尤其适用于芯片模块的制造过程中和/或之后的接触测试。在这种情况下，至少两个或更多个彼此绝缘的接触区域3A至3D的接触电阻可以通过电流-电压测量相互比较或与好/坏值进行比较。这种测量可以作为样品测量集成到制造过程中。还可以规定，在芯片模块的制造过程中，根据测试方法对所有接触件或几乎所有接触件进行检查。
测试程序可以作为芯片模块的质量控制的一部分进行。模块完成之后，在通常所称的最终测试中，至少两个或更多个绝缘接触表面的接触电阻可以相互比较或与例如以好/坏值的形式的至少一个阈值进行比较，通过使用合适的接触和测量装置的电流-电压测量，例如所描述的测试布置。这种测量可以作为样品测量集成到质量控制过程中。还可以规定，在芯片模块的质量控制过程中，根据测试方法对所有接触件或几乎所有接触件进行检查。
测试程序可以作为可靠性测试的一部分进行，以实现芯片模块的开发、更改、资格认证和质量保证。使用合适的接触和测量装置，特别是上述的测试布置，可以通过电流-电压测量来检测至少两个或更多个绝缘接触表面的接触电阻。这可以作为各种参数的函数发生，例如时间、温度、湿度等。测量值检测可以连续进行。
在实施例中，所描述的测试方法可以在使用芯片模块的同时应用，例如在LIDAR传感器中。测量值检测可以连续进行。如果高于或低于指定的阈值，则可以向更高级别的***发送警告。这对于安全相关***尤其有利，例如在车辆安全***中。例如，芯片模块的各个接触件的故障可以被检测和定位，优选是实时的，并且可以使用警告信号向用户或***发出某些接触件的故障或质量损失的信号。因此，除了芯片模块突然发生的故障外，测试方法还可以检测到芯片模块的早期故障。
本发明改善了芯片1和芯片载体之间连接的稳定性和可靠性，和/或创造了检查这种电气和机械连接的状态，特别是永久监控它的可能性。
芯片1的安全后侧接触的基本功能不仅可以在制造过程本身中进行测试，而且可以在应用中永久执行该测试-即，当芯片模块正在被使用时，例如在机动车辆或无人机中，以及再次，例如在LIDAR传感器中。特别是在安全关键应用的情况下，这可以提供在早期检测故障并做出相应反应的可能性。

Claims (13)

1.一种芯片模块，包括：
芯片(1)，具有前侧(11)和后侧(12)；
芯片载体(2)，具有面向所述芯片(1)的上侧(21)；
接触层(3)，由导电材料形成，且在所述芯片(1)的后侧(12)和所述芯片载体(2)的上侧(21)之间布置在所述芯片载体(2)的上侧(21)上；以及
导电粘合剂(4)，布置在所述接触层(3)的面向所述芯片(1)的上侧(321)上，所述导电粘合剂(4)连接所述接触层(3)的上侧(321)和所述芯片(1)的后侧(12)，所述接触层(3)具有多个区域(3A，3B)，所述多个区域彼此电隔离且各自通过所述导电粘合剂(4)电连接到所述芯片(1)。
2.如权利要求1所述的芯片模块，其中，所述多个区域(3A，3B，3C)是至少三个区域。
3.如权利要求1所述的芯片模块，其中，所述芯片(1)具有长度(L1)和/或宽度(B1)，所述长度(L1)小于所述接触层(3)的长度(L3)和/或所述宽度(B1)小于所述接触层(3)的宽度(B3)，且所述接触层(3)凸出超过所述芯片(1)。
4.如权利要求1所述的芯片模块，其中，所述芯片(1)具有长度(L1)和/或宽度(B1)，所述长度(L1)大于所述接触层(3)的长度(L3)和/或所述宽度(B1)大于所述接触层(3)的宽度(B3)，且所述芯片(1)覆盖所述接触层(3)。
5.如权利要求1所述的芯片模块，其中，所述芯片(1)与接触层(3)对中，其中所述接触层(3)的上侧(321)的表面中心点离所述芯片(1)的后侧(12)的表面中心点距离最小，所述接触层(3)的表面由所述多个区域(3A，3B)的多个外边缘限定。
6.如权利要求1所述的芯片模块，其中，所述多个区域(3A，3B)中的至少两个具有镀覆通孔(31)，所述镀覆通孔从所述芯片载体(2)的上侧(21)延伸到所述芯片载体(2)的底侧(22)。
7.如权利要求6所述的芯片模块，其中，所述镀覆通孔(31)在所述芯片载体(2)的底侧(22)上具有焊接表面(33)和/或焊球(34)。
8.如权利要求6所述的芯片模块，其中，所述镀覆通孔(31)具有延伸穿过所述镀覆通孔(31)的通道(35)。
9.如权利要求8所述的芯片模块，其中，所述导电粘合剂(4)布置在所述通道(35)中和/或在所述镀覆通孔(31)与所述芯片(1)的后侧(12)之间。
10.如权利要求1所述的芯片模块，还包括非导电粘合剂(6)，所述非导电粘合剂布置在所述芯片载体(2)和所述芯片(1)之间，并将所述芯片载体(2)的上侧(21)连接到所述芯片(1)的后侧(12)。
11.如权利要求1所述的芯片模块，还包括布置在所述芯片载体(2)的上侧(21)上的壳体(5)，所述壳体(5)围封所述芯片(1)和所述接触层(3)。
12.如权利要求11所述的芯片模块，其中，所述壳体(5)在所述芯片(1)的前侧(11)具有光学窗口(51)。
13.一种测试布置，包括：
芯片模块，包括芯片(1)，所述芯片具有前侧(11)和后侧(12)；芯片载体(2)，具有面向所述芯片(1)的上侧(21)；接触层(3)，由导电材料形成，且在所述芯片(1)的后侧(21)和所述芯片载体(2)的上侧(21)之间布置在所述芯片载体(2)的上侧(21)上；以及导电粘合剂(4)，布置在所述接触层(3)的面向所述芯片(1)的上侧(321)上，所述导电粘合剂(4)连接所述接触层(3)的上侧(321)和所述芯片(1)的后侧(12)，所述接触层(3)具有多个区域(3A，3B)，所述多个区域彼此电隔离且各自通过所述导电粘合剂(4)电连接到所述芯片(1)；
第一电连接元件(71)，与所述多个区域(3A，3B)中的第一区域(3A)电接触；
第二电连接元件(72)，与所述多个区域(3A，3B)中的第二区域(3B)电接触或与所述芯片载体(2)的电接触元件(10)电接触；以及
电流测量装置(A)，电连接到所述第一电连接元件(71)和所述第二电连接元件(72)，所述电流测量装置(A)测量所述第一电连接元件(71)和所述第二电连接元件(72)之间的测试电流(8)。
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