CN114596817B

CN114596817B - Shift register unit, gate driving circuit, display panel and display device

Info

Publication number: CN114596817B
Application number: CN202210289048.3A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-03-23
Filing date: 2022-03-23
Publication date: 2023-11-21
Anticipated expiration: 2042-03-23
Also published as: CN114596817A

Abstract

The present disclosure provides a shift register unit including: the shift register unit further comprises an auxiliary input circuit, wherein the auxiliary input circuit is connected with the first power supply end and the input enhancement node, and the auxiliary input circuit is configured to output an effective level signal provided by the first power supply end. The disclosure also provides a gate driving method, a gate driving circuit, a display panel and a display device.

Description

Shift register unit, gate driving circuit, display panel and display device

Technical Field

The present invention relates to the field of display, and in particular, to a shift register unit, a gate driving circuit, a display panel, and a display device.

Background

Active matrix organic light emitting diode panels (Active Matrix Organic Light Emitting Diode, abbreviated as AMOLED) are becoming increasingly popular. The pixel display device of the AMOLED is an Organic Light-Emitting Diode (OLED), and the AMOLED is capable of Emitting Light by driving a thin film transistor to generate a driving current in a saturated state, and the driving current drives the Light-Emitting device to emit Light.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a shift register unit, including:

the sensing control circuit is connected with the sensing signal input end, the random signal input end and the sensing control node and is configured to respond to the control of the effective level signal provided by the random signal input end to write the signal provided by the sensing signal input end into the sensing control node;

the sensing pre-charge preparation circuit is connected with the sensing control node, the clock control signal input end and the input enhancement node and is configured to respond to the control of an effective level signal at the sensing control node to output signals provided by the clock control signal input end;

a first sensing precharge circuit coupled to the clock control signal input, the input boost node, and a first pull-up node, configured to write a voltage at the input boost node to the first pull-up node in response to control of an active level signal provided by the clock control signal input;

the auxiliary input circuit is connected with the first power supply end and the input enhancement node and is configured to output an effective level signal provided by the first power supply end;

And the first driving output circuit is connected with the first pull-up node, the first driving clock signal input end and the first driving signal output end and is configured to respond to the control of the effective level signal at the first pull-up node to write the signal provided by the first driving clock signal input end into the first driving signal output end.

In some embodiments, the auxiliary input circuit comprises: a fourth transistor;

the control electrode of the fourth transistor is connected with the first power supply end, the first electrode of the fourth transistor is connected with the first power supply end, and the second electrode of the fourth transistor is connected with the input enhancement node.

In some embodiments, the auxiliary input circuit further comprises: a sixth transistor located between the fourth transistor and the input enhancement node, a second diode of the fourth transistor being connected to the input enhancement node through the sixth transistor;

the control electrode of the sixth transistor is connected with the first power supply end, the first electrode of the sixth transistor is connected with the second electrode of the fourth transistor, and the second electrode of the sixth transistor is connected with the input enhancement node.

In some embodiments, the sense pre-charge preparation circuit includes: a second transistor;

the control electrode of the second transistor is connected with the sensing control node, the first electrode of the second transistor is connected with the clock control signal input end, and the second electrode of the second transistor is connected with the input enhancement node.

In some embodiments, the sense pre-charge preparation circuit further comprises: an eighth transistor located between the second transistor and the input enhancement node, a second pole of the second transistor being connected to the input enhancement node through the eighth transistor;

the control electrode of the eighth transistor is connected with the clock control signal input end, the first electrode of the eighth transistor is connected with the second electrode of the second transistor, and the second electrode of the eighth transistor is connected with the input enhancement node.

In some embodiments, further comprising:

a first display precharge circuit connected to a display signal input terminal, a third power supply terminal, and a first pull-up node, configured to write a non-valid level signal provided by the third power supply terminal to the first pull-up node in response to control of a valid level signal provided by the display signal input terminal;

And the second driving output circuit is connected with the first pull-up node, the second driving clock signal input end and the second driving signal output end and is configured to respond to the control of the effective level signal at the first pull-up node to write the signal provided by the second driving clock signal input end into the second driving signal output end.

In some embodiments, the first display precharge circuit includes: a ninth transistor;

the control electrode of the ninth transistor is connected with the display signal input end, the first electrode of the ninth transistor is connected with the third power supply end, and the second electrode of the ninth transistor is connected with the pull-up node;

alternatively, the first display precharge circuit includes: a ninth transistor and an eleventh transistor;

a control electrode of the ninth transistor is connected with the display signal input end, a first electrode of the ninth transistor is connected with a third power supply end, and a second electrode of the ninth transistor is connected with a first electrode of the eleventh transistor;

the control electrode of the eleventh transistor is connected with the display signal input end, the first electrode of the eleventh transistor is connected with the input enhancement node, and the second electrode of the eleventh transistor is connected with the first pull-up node.

In some embodiments, further comprising:

a first sense reset circuit connected to a sense reset signal input terminal, a second power supply terminal, and the first pull-up node, and configured to write a non-valid level signal provided by the second power supply terminal to the first pull-up node in response to control of a valid level signal provided by the sense reset signal input terminal;

a first display reset circuit connected with a display reset signal input end, a second power end and the first pull-up node and configured to respond to the control of an effective level signal provided by the sensing reset signal input end and write a non-effective level signal provided by the second power end into the first pull-up node;

a first pull-down control circuit connected to a second power supply terminal, a fifth power supply terminal, the first pull-up node, and a first pull-down node, configured to write a voltage to the first pull-down node that is opposite to a voltage at the first pull-up node;

a first pull-up noise reduction circuit connected to the second power supply terminal, the first pull-up node and the first pull-down node and configured to write a non-valid level signal provided by the second power supply terminal to the first pull-up node in response to control of the valid level signal at the first pull-down node;

A cascade output circuit connected to a first pull-up node, a first pull-down node, a second power supply terminal, a cascade clock signal input terminal, and a cascade signal output terminal, configured to write a signal provided by the cascade clock signal input terminal to the cascade signal output terminal in response to control of an active level signal at the first pull-up node, and to write a non-active level signal provided by the second power supply terminal to the cascade signal output terminal in response to control of an active level signal at the first pull-down node;

the first drive output circuit is further connected with the first pull-down node and a fourth power supply end, and is further configured to write a non-valid level signal provided by the fourth power supply end to the first drive signal output end in response to control of a valid level signal at the first pull-down node;

the second drive output circuit is further connected to the first pull-down node and a fourth power supply terminal, and is further configured to write a non-valid level signal provided by the fourth power supply terminal to the second drive signal output terminal in response to control of the valid level signal at the first pull-down node.

In some embodiments, further comprising: a first voltage control circuit;

the first voltage control circuit is connected with an effective level supply end, a first pull-up node and a first voltage control node, and is configured to respond to the control of an effective level signal at the first pull-up node and write the effective level signal provided by the effective level supply end into the first voltage control node;

the shift register unit further includes: at least one of the first anti-creeping circuit, the second anti-creeping circuit and the third anti-creeping circuit;

the first sensing reset circuit is connected with a second power supply end through the first anti-leakage circuit, the first sensing reset circuit and the first anti-leakage circuit are connected with a first anti-leakage node, the first anti-leakage node is connected with the first voltage control node, the first anti-leakage circuit is connected with a sensing reset signal input end, the first anti-leakage circuit is configured to enable a passage to be formed between the first anti-leakage node and the second power supply end in response to control of an effective level signal provided by the sensing reset signal input end, and enable a circuit to be broken between the first anti-leakage node and the second power supply end in response to control of an ineffective level signal provided by the sensing reset signal input end;

The first display reset circuit is connected with a second power supply end through the second anti-leakage circuit, the first display reset circuit and the second anti-leakage circuit are connected with a second anti-leakage node, the second anti-leakage node is connected with the first voltage control node, the second anti-leakage circuit is connected with a display reset signal input end, the second anti-leakage circuit is configured to enable a passage to be formed between the second anti-leakage node and the second power supply end in response to control of an effective level signal provided by the display reset signal input end, and enable a circuit to be broken between the second anti-leakage node and the second power supply end in response to control of an ineffective level signal provided by the display reset signal input end;

the first pull-up noise reduction circuit is connected with the second power end through the third anti-creeping circuit, the first pull-up noise reduction circuit is connected with the third anti-creeping circuit and is connected with a third anti-creeping node, the third anti-creeping node is connected with the first voltage control node, the third anti-creeping circuit is connected with the first pull-down node, and the third anti-creeping circuit is configured to respond to the control of an effective level signal at the first pull-down node to enable a passage to be formed between the third anti-creeping node and the second power end and respond to the control of a non-effective level signal at the first pull-down node to enable a circuit to be broken between the third anti-creeping node and the second power end.

In some embodiments, the active level supply terminal is the third power supply terminal;

alternatively, the auxiliary input circuit includes: a fourth transistor and a sixth transistor;

the control electrode of the fourth transistor is connected with the first power supply end, the first electrode of the fourth transistor is connected with the first power supply end, and the second electrode of the fourth transistor and the first electrode of the sixth transistor are connected with an effective level output node;

the control electrode of the sixth transistor is connected with the first power supply end, and the second electrode of the sixth transistor is connected with the input enhancement node;

the active level supply terminal is the active level output node.

In some embodiments, further comprising:

a second sensing precharge circuit coupled to the clock control signal input, the input boost node, and a second pull-up node, configured to write a voltage at the input boost node to the second pull-up node in response to control of an active level signal provided by the clock control signal input;

a second display precharge circuit connected to a display signal input terminal and a second pull-up node, configured to write an active level signal to the second pull-up node in response to control of the active level signal provided by the display signal input terminal;

A third driving output circuit connected to the second pull-up node, a third driving clock signal input terminal, and a third driving signal output terminal, and configured to write a signal provided by the third driving clock signal input terminal into the third driving signal output terminal in response to control of an active level signal at the second pull-up node;

and the fourth driving output circuit is connected with the second pull-up node, the fourth driving clock signal input end and the fourth driving signal output end and is configured to respond to the control of the effective level signal at the second pull-up node to write the signal provided by the fourth driving clock signal input end into the fourth driving signal output end.

In some embodiments, the second display precharge circuit includes: a thirty-ninth transistor;

a control electrode of the thirty-ninth transistor is connected with the display signal input end, a first electrode of the thirty-ninth transistor is connected with the third power supply end, and a second electrode of the thirty-ninth transistor is connected with the second pull-up node;

alternatively, the second display precharge circuit includes: a forty-first transistor;

the control electrode of the forty-first transistor is connected with the display signal input end, the first electrode of the forty-first transistor is connected with the input enhancement node, and the second electrode of the forty-first transistor is connected with the second pull-up node;

Alternatively, the second display precharge circuit includes: a thirty-ninth transistor and a forty-first transistor;

a control electrode of the thirty-ninth transistor is connected with the display signal input end, a first electrode of the thirty-ninth transistor is connected with the third power supply end, and a second electrode of the thirty-ninth transistor is connected with a first electrode of the forty-first transistor;

the control electrode of the forty-first transistor is connected with the display signal input end, the first electrode of the forty-first transistor is connected with the input enhancement node, and the second electrode of the forty-first transistor is connected with the second pull-up node.

In some embodiments, further comprising:

a second sense reset circuit connected to a sense reset signal input terminal, an inactive level supply terminal, and the second pull-up node, and configured to write an inactive level signal provided by the inactive level supply terminal to the second pull-up node in response to control of an active level signal provided by the sense reset signal input terminal;

a second display reset circuit connected to a display reset signal input terminal, an inactive level supply terminal, and the second pull-up node, and configured to write an inactive level signal provided by the inactive level supply terminal to the second pull-up node in response to control of an active level signal provided by the display reset signal input terminal;

A second pull-down control circuit connected to a second power supply terminal, a sixth power supply terminal, the second pull-up node, and a second pull-down node, configured to write a voltage to the second pull-down node that is opposite to a voltage at the second pull-up node;

a second pull-up noise reduction circuit connected to a non-active level supply terminal, the second pull-up node, and a second pull-down node, configured to write a non-active level signal provided by the non-active level supply terminal to the second pull-up node in response to control of an active level signal at the second pull-down node;

the third driving output circuit is further connected with the second pull-down node and a fourth power supply end, and is further configured to write a non-valid level signal provided by the fourth power supply end to the third driving signal output end in response to control of a valid level signal at the second pull-down node;

the fourth drive output circuit is further connected to the second pull-down node and a fourth power supply terminal, and is further configured to write a non-valid level signal provided by the fourth power supply terminal to the fourth drive signal output terminal in response to control of a valid level signal at the second pull-down node.

In some embodiments, the inactive level supply terminal is the second power supply terminal;

the shift register unit further includes: a second voltage control circuit;

the second voltage control circuit is connected with an effective level supply end, a first pull-up node and a second voltage control node, and is configured to respond to the control of an effective level signal at the second pull-up node and write the effective level signal provided by the effective level supply end into the second voltage control node;

the shift register unit further includes: at least one of the fourth anticreep circuit, the fifth anticreep circuit, and the sixth anticreep circuit;

the second sensing reset circuit is connected with a second power end through the fourth anti-leakage circuit, the second sensing reset circuit and the fourth anti-leakage circuit are connected with a fourth anti-leakage node, the fourth anti-leakage node is connected with the second voltage control node, the fourth anti-leakage circuit is connected with a sensing reset signal input end, the fourth anti-leakage circuit is configured to enable a passage to be formed between the fourth anti-leakage node and the second power end in response to control of an effective level signal provided by the sensing reset signal input end, and enable a circuit to be broken between the fourth anti-leakage node and the second power end in response to control of an ineffective level signal provided by the sensing reset signal input end;

The second display reset circuit is connected with a second power supply end through the fifth anti-leakage circuit, the second display reset circuit is connected with a fifth anti-leakage node which is connected with the second voltage control node, the fifth anti-leakage circuit is connected with a display reset signal input end, the fifth anti-leakage circuit is configured to enable a passage to be formed between the fifth anti-leakage node and the second power supply end in response to control of an effective level signal provided by the display reset signal input end, and enable a circuit to be broken between the fifth anti-leakage node and the second power supply end in response to control of an ineffective level signal provided by the display reset signal input end;

the second pull-up noise reduction circuit is connected with a second power end through the sixth anti-leakage circuit, the second pull-up noise reduction circuit is connected with the sixth anti-leakage circuit and is connected with a sixth anti-leakage node, the sixth anti-leakage node is connected with a second voltage control node, the sixth anti-leakage circuit is connected with a second pull-down node, and the sixth anti-leakage circuit is configured to respond to the control of an effective level signal at the second pull-down node to enable a passage to be formed between the sixth anti-leakage node and the second power end and respond to the control of a non-effective level signal at the second pull-down node to enable a circuit to be broken between the sixth anti-leakage node and the second power end.

In some embodiments, when the shift register unit includes a first voltage control circuit, the inactive level supply terminal is the first voltage control node.

In a second aspect, embodiments of the present disclosure further provide a gate driving circuit, including: a plurality of shift register units in cascade, the shift register units employing the shift register units provided in the first aspect.

In a third aspect, embodiments of the present disclosure further provide a display panel, including: the gate driving circuit as provided in the second aspect described above.

In a fourth aspect, an embodiment of the present disclosure further provides a display apparatus, including: the display panel as provided in the third aspect described above.

In a fifth aspect, an embodiment of the present disclosure further provides a gate driving method, based on the shift register unit provided in the first aspect, including:

the sensing control circuit responds to the control of the effective level signal provided by the random signal input end to write the signal provided by the sensing signal input end into the sensing control node;

the sensing precharge preparation circuit outputs a signal provided by the clock control signal input terminal to the input enhancement node in response to control of an effective level signal at the sensing control node, and the auxiliary input circuit outputs an effective level signal provided by the first power supply terminal to the input enhancement node;

The first sensing precharge circuit is used for responding to the control of the effective level signal provided by the clock control signal input end to write the voltage at the input enhancement node into the first pull-up node;

the first drive output circuit writes a signal provided by the first drive clock signal input to the first drive signal output in response to control of an active level signal at the first pull-up node.

Drawings

Fig. 1 is a schematic circuit diagram of a pixel circuit in an organic light emitting diode display panel;

FIG. 2 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 1;

fig. 3 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 4 is a schematic circuit diagram of another circuit structure of a shift register unit according to an embodiment of the disclosure;

FIG. 5 is a timing diagram illustrating operation of the shift register unit shown in FIG. 4;

fig. 6 is a schematic diagram of another circuit structure of a shift register unit according to an embodiment of the disclosure;

fig. 7 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

FIG. 8 is a timing diagram illustrating operation of the shift register unit shown in FIG. 7;

Fig. 9 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

FIG. 10 is a schematic diagram of another circuit structure of a shift register unit according to an embodiment of the disclosure;

FIG. 11 is a schematic diagram of another circuit structure of a shift register unit according to an embodiment of the disclosure;

FIG. 12 is a timing diagram illustrating operation of the shift register unit shown in FIG. 11;

fig. 13 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 14 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 15 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 16 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 17 is a schematic diagram of still another circuit structure of a shift register unit according to an embodiment of the disclosure;

fig. 18 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 19 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 20 is a schematic diagram of still another circuit structure of a shift register unit according to an embodiment of the disclosure;

Fig. 21 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 22 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 23 is a schematic circuit diagram of a gate driving circuit according to an embodiment of the disclosure;

FIG. 24 is a timing diagram illustrating operation of the gate driving circuit shown in FIG. 23;

fig. 25 is a method flowchart of a gate driving method according to an embodiment of the disclosure.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions of the present invention, a shift register unit, a gate driving circuit, a display panel and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not limited to physical or mechanical coupling, but may include electrical connection, whether direct or indirect.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the drain and source of each transistor may be coupled interchangeably, so that the drain and source of each transistor are virtually indistinguishable in the embodiments of the present disclosure. Here, only in order to distinguish between two electrodes of a transistor except a control electrode (i.e., a gate electrode), one of the electrodes is called a drain electrode and the other is called a source electrode. The thin film transistor adopted in the embodiment of the disclosure may be an N-type transistor or a P-type transistor. In the embodiment of the disclosure, when an N-type thin film transistor is used, the first pole may be a source electrode and the second pole may be a drain electrode. In the following embodiments, a thin film transistor is described as an example of an N-type transistor.

In the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on after being input to the control electrode of the transistor, and a "inactive level signal" refers to a signal that can control the transistor to be turned off after being input to the control electrode of the transistor. For an N-type transistor, the high level signal is an active level signal, and the low level signal is an inactive level signal; for a P-type transistor, the low level signal is an active level signal and the high level signal is an inactive level signal.

In the following description, a transistor will be described as an example of an N-type transistor, where an active level signal means a high level signal and an inactive level signal means a low level signal. It is conceivable that when a P-type transistor is employed, the timing variation of the control signal needs to be adjusted accordingly. Specific details are not set forth herein but are intended to be within the scope of the present disclosure.

Fig. 1 is a schematic circuit diagram of a pixel circuit in an oled display panel, and fig. 2 is a timing chart of operation of the pixel circuit shown in fig. 1, as shown in fig. 1 and 2, for an oled display panel with an external compensation function, a frame of image can be divided into two stages: a display driving stage and a sensing stage; in the display driving stage, each row of pixel units in the display panel completes display driving; in the sensing phase, a certain row of pixel units in the display panel completes current extraction (i.e. sensing).

Referring to fig. 1, the pixel circuit includes a display switching transistor QTFT (a control electrode connected to a first gate line G1), a driving transistor DTFT, a sensing switching transistor STFT (a control electrode connected to a second gate line G2), and a Cst. When external compensation is needed to be carried out on the pixel circuit, the pixel circuit at least comprises the following two stages in the working process: a pixel driving phase (including a data voltage writing process) and a pixel sensing phase (including a current reading process).

In the pixel driving stage, the Data voltage Vdata in the Data line Data needs to be written into the pixel unit; in the pixel sensing stage, a test voltage vsense needs to be written into the pixel unit through the Data line Data, and an electric signal at the drain of the driving transistor is read to the signal reading line sequence through the sensing switching transistor STFT. In the current reading process, an active level voltage needs to be written to the gate of the sensing switching transistor STFT through the corresponding second gate line G2. It should be noted that, the external compensation is performed on the pixel unit in the OLED display panel, and specific compensation processes and principles are not described herein.

For the second gate line G2 for controlling the sensing switching transistor STFT, a corresponding gate driving circuit is configured in a peripheral region of the display panel, the gate driving circuit includes a plurality of cascaded shift register units, wherein each shift register unit includes a sensing control circuit, a sensing precharge preparation circuit, and a first sensing precharge circuit therein, wherein the sensing control circuit, the sensing precharge preparation circuit, and the first sensing precharge circuit are used for implementing input of a sensing cascade signal (specifically, for writing an active level signal representing the sensing cascade to a first pull-up node). The higher the input capability of the sensing cascade signal of the shift register unit, the more stable the sensing cascade driving process of the gate driving circuit. Therefore, how to improve the input capability of the sensing cascade signal of the shift register unit is a technical problem that needs to be solved in the art.

In view of the foregoing technical problems, embodiments of the present disclosure provide corresponding solutions, and the following details of each embodiment will be described with reference to the accompanying drawings.

Fig. 3 is a schematic circuit diagram of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 3, the shift register unit includes a sensing control circuit 1, a sensing precharge preparation circuit 2, a first sensing precharge circuit 3, an auxiliary input circuit 4, and a first driving output circuit 5.

The sensing control circuit 1 is connected with the sensing signal INPUT end INPUT2, the random signal INPUT end OE and the sensing control node H, and the sensing control circuit 1 is configured to write the signal provided by the sensing signal INPUT end INPUT2 into the sensing control node H in response to the control of the effective level signal provided by the random signal INPUT end OE.

The sensing precharge preparation circuit 2 is connected to the sensing control node H, the clock control signal input terminal CLKA, and the input boost node M, and the sensing precharge preparation circuit 2 is configured to output a signal provided by the clock control signal input terminal CLKA in response to control of an active level signal at the sensing control node H. In some embodiments, the sense pre-charge preparation circuit 2 is specifically configured to write the signal provided by the clock control signal input CLKA to the input boost node M in response to control of the active level signal at the sense control node H and while the signal provided by the clock control signal input CLKA is in an active level state.

The first sensing precharge circuit 3 is connected to the clock control signal input terminal CLKA, the input boost node M and the first pull-up node PU1, and the first sensing precharge circuit 3 is configured to write a voltage at the input boost node M to the first pull-up node PU1 in response to control of an active level signal provided by the clock control signal input terminal CLKA.

The auxiliary input circuit 4 is connected to the first power supply terminal and the input boost node M, and the auxiliary input circuit 4 is configured to output an active level signal provided by the first power supply terminal. In some embodiments, the auxiliary input circuit 4 is specifically configured to write the active level signal provided by the first power supply terminal to the input enhancement node M when the first sensing precharge circuit 3 writes the voltage at the input enhancement node M to the first pull-up node PU1.

The first driving output circuit 5 is connected to the first pull-up node PU1, the first driving clock signal input terminal CLKE, and the first driving signal output terminal OUT2, and is configured to write a signal provided by the first driving clock signal input terminal CLKE to the first driving signal output terminal OUT2 in response to control of an active level signal at the first pull-up node PU1.

The shift register unit provided in the embodiment of the present disclosure is additionally provided with the auxiliary input circuit 4, when the first sensing precharge circuit writes the voltage at the input enhancing node M into the first pull-up node PU1, the auxiliary input circuit 4 also writes the effective level signal provided by the first power supply terminal into the input enhancing node M, and for the input enhancing node M, on the one hand, the sensing precharge preparation circuit 2 charges the input enhancing node M to write the effective level signal, and on the other hand, the auxiliary input circuit 4 charges the input enhancing node M to write the effective level signal, so that the voltage at the input enhancing node M is charged to the effective level state in a very short time, and correspondingly, the voltage at the first pull-up node PU1 is also charged to the effective level state in a very short time. That is, when the clock control signal input terminal CLKA provides the active level signal, the active level signal characterizing the sensing cascade can be instantly written into the first pull-up node PU1 through the input enhancing node M and the first sensing precharge circuit 3, so that the input capability of the sensing cascade signal of the shift register unit can be effectively improved.

Fig. 4 is a schematic diagram of another circuit structure of a shift register unit according to an embodiment of the disclosure, as shown in fig. 4, in some embodiments, the auxiliary input circuit 4 includes a fourth transistor M4; the control electrode of the fourth transistor M4 is connected to the first power supply terminal, the first electrode of the fourth transistor M4 is connected to the first power supply terminal, and the second electrode of the fourth transistor M4 is connected to the input enhancement node M.

In order to facilitate a clearer understanding of the technical solutions of the present disclosure by those skilled in the art, the technical solutions of the present disclosure will be described in detail below with reference to specific examples. The first power supply terminal provides an active level voltage VDD2, and the second power supply terminal provides an inactive level voltage VGL1.

In some embodiments, the shift register cell further comprises a first sense reset circuit 6; the first sense reset circuit 6 is connected to the sense reset signal input terminal T-RST, the second power supply terminal, and the first pull-up node PU1, and the first sense reset circuit 6 is configured to write the inactive level signal provided by the second power supply terminal to the first pull-up node PU1 in response to control of the active level signal provided by the sense reset signal input terminal T-RST.

In some embodiments, the sensing control circuit 1 includes a first transistor M1, the sensing precharge circuit includes a second transistor M2, the first sensing precharge circuit 3 includes a third transistor M3, the first driving output circuit 5 includes a fifth transistor M5, and the first sensing reset circuit 6 includes a seventh transistor M7.

The control electrode of the first transistor M1 is connected to the random signal INPUT end OE, the first electrode of the first transistor M1 is connected to the sensing signal INPUT end INPUT2, and the second electrode of the first transistor M1 is connected to the sensing control node H.

The control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the clock control signal input terminal CLKA, and the second electrode of the second transistor M2 is connected to the input boost node M.

The control electrode of the third transistor M3 is connected to the clock control signal input terminal CLKA, the first electrode of the third transistor M3 is connected to the input boost node M, and the second electrode of the third transistor M3 is connected to the first pull-up node PU 1.

The control electrode of the fifth transistor M5 is connected to the first pull-up node PU1, the first electrode of the fifth transistor M5 is connected to the first driving clock signal input terminal CLKE, and the second electrode of the fifth transistor M5 is connected to the first driving signal output terminal OUT 2.

The control electrode of the seventh transistor M7 is connected to the sensing reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the first pull-up node PU1, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal.

In some embodiments, a first capacitor C1 is configured at the sensing control node H that can stabilize the voltage at the sensing control node H. A second capacitor C2 capable of stabilizing the output of the first driving signal output terminal OUT2 is disposed at the first driving signal output terminal OUT 2.

FIG. 5 is a timing diagram of the operation of the shift register unit shown in FIG. 4. As shown in FIG. 5, in some embodiments, the shift register unit includes the following stages:

in the p1 stage, the sensing signal INPUT2 provides a high level signal, the random signal INPUT OE provides a high level signal, the clock control signal INPUT CLKA provides a low level signal, and the sensing reset signal INPUT T-RST provides a low level signal.

At this time, the first transistor M1 is turned on, the high level signal provided by the sensing signal INPUT terminal INPUT2 is written into the sensing control node H, and the voltage at the sensing control node H is in a high level state. Accordingly, the second transistor M2 is turned on, the low level signal provided by the clock signal input terminal CLKA is written to the input boost node M through the second transistor M2, and the voltage at the input boost node M is in a low level state, and at this time, the fourth transistor M4 is equivalent to a resistor.

Since the clock control signal input terminal CLKA provides a low level signal, the third transistor M3 is turned off; the sense reset signal input terminal T-RST provides a low level signal, so the seventh transistor M7 is turned off.

It should be noted that, the p1 stage is located in the display driving stage in one frame, and the voltage conditions applied by the first pull-up node PU1 and the first driving signal output terminal OUT2 in the display driving stage can be seen from the description in the following embodiments, and the present embodiment only describes the specific operation of the shift register unit in the sensing stage in detail.

In the p2 stage, the sensing signal INPUT2 provides a low level signal, the random signal INPUT OE provides a low level signal, the clock control signal INPUT CLKA provides a high level signal, and the sensing reset signal INPUT T-RST provides a low level signal.

Since the voltage at the sensing control node H maintains the high state in the previous stage, the second transistor M2 is kept on, the clock control signal input terminal CLKA provides a high level signal to be written into the input enhancement node M through the second transistor M2, and simultaneously the high level voltage VDD2 provided at the first power supply terminal is also written into the input enhancement node M through the fourth transistor M4, so that the voltage at the input node is enhanced to be charged to the high state instantaneously. Meanwhile, since the third transistor M3 is turned on by the high signal provided by the clock signal input terminal CLKA, the high signal at the enhanced input node is instantaneously written into the first pull-up node PU1. It can be seen that the shift register unit has a strong input capability for sensing the cascade signal.

Since the first pull-up node PU1 is in a high state, the fifth transistor M5 is turned on, the low level signal provided by the first driving clock signal input terminal CLKE is written to the first driving signal output terminal OUT2 through the fifth transistor M5, and the first driving signal output terminal OUT2 outputs the low level signal.

It should be noted that, there is a time interval between the p1 phase and the p2 phase, in order to ensure that the voltage at the sensing control node H remains stable in the time interval, the first capacitor C1 may be added at the sensing control node H.

In the p3 stage, the sensing signal INPUT2 provides a low level signal, the random signal INPUT OE provides a low level signal, the clock control signal INPUT CLKA provides a low level signal, and the sensing reset signal INPUT T-RST provides a low level signal.

Since the clock signal input terminal CLKA provides a low level signal, the third transistor M3 is turned off, and since the second transistor M2 is kept turned on, the low level signal provided by the clock signal input terminal CLKA is written into the input boost node M through the second transistor M2, and the input boost node M is in a low level state. At this time, the first pull-up node PU1 maintains the high state of the previous stage, and the fifth transistor M5 maintains on.

In this stage, the first driving clock signal input terminal CLKE provides a high level signal and then a low level signal, and the signal provided by the first driving clock signal input terminal CLKE is written to the first driving signal output terminal OUT2 through the fifth transistor M5, and the first driving signal output terminal OUT2 outputs a high level signal and then a low level signal. It should be noted that, in the process of switching the output low level signal to the output high level signal from the output low level signal of the first driving signal output terminal OUT2, the voltage at the first pull-up node PU1 is pulled up to a higher level under the bootstrap action of the second capacitor C2; in the process that the first driving signal output terminal OUT2 is switched from outputting the high level signal to outputting the low level signal, the voltage at the first pull-up node PU1 is pulled down to the initial high level state under the bootstrap action of the second capacitor C2.

In the p4 stage, the sensing signal INPUT2 provides a low level signal, the random signal INPUT OE provides a high level signal, the clock control signal INPUT CLKA provides a low level signal, and the sensing reset signal INPUT T-RST provides a high level signal.

Since the random signal INPUT end OE provides a high level signal, the first transistor M1 is turned on, the low level signal provided by the sensing signal INPUT end INPUT2 is written into the sensing control node H through the first transistor M1, the voltage at the sensing control node H is in a low level state, and the second transistor M2 is turned off. The input enhancement node M is in a floating state, and the high level voltage VDD2 provided by the first power terminal is written into the input enhancement node M through the fourth transistor M4, and the input enhancement node M maintains the high level state.

Meanwhile, since the sensing reset signal input terminal T-RST provides the high level signal, the seventh transistor M7 is turned on, the low level voltage VGL1 provided by the second power supply terminal is written into the first pull-up node PU1 through the seventh transistor M7, the first pull-up node PU1 is in the low level state, the fifth transistor M5 is turned off, and the first driving signal output terminal OUT2 maintains the low level state of the previous stage, i.e., maintains outputting the low level signal.

Based on the above, in the p2 stage of writing the high level signal representing the sensing cascade signal into the first pull-up node PU1, the auxiliary input circuit 4 writes the high level signal provided by the first power terminal into the input enhancement node M, and for the input enhancement node M, the sensing precharge preparation circuit 2 charges the input enhancement node M to write the high level signal, and the auxiliary input circuit 4 charges the input enhancement node M to write the high level signal, so that the voltage at the input enhancement node M is charged to the high level state in a very short time, and accordingly, the voltage at the first pull-up node PU1 is also charged to the high level state in a very short time. That is, when the clock control signal input terminal CLKA provides the high level signal, the high level signal characterizing the sensing cascade can be instantly written into the first pull-up node PU1 through the input enhancing node M and the first sensing precharge circuit 3, so that the input capability of the sensing cascade signal of the shift register unit can be improved.

Fig. 6 is a schematic circuit diagram of another circuit structure of a shift register unit according to an embodiment of the disclosure, as shown in fig. 6, in some embodiments, the auxiliary input circuit 4 includes not only the fourth transistor M4 in the previous embodiments, but also a sixth transistor M6, the sixth transistor M6 is located between the fourth transistor M4 and the input enhancement node M, and a second pole of the fourth transistor M4 is connected to the input enhancement node M through the sixth transistor M6; the control electrode of the sixth transistor M6 is connected to the first power supply terminal, the first electrode of the sixth transistor M6 is connected to the second electrode of the fourth transistor M4, and the second electrode of the sixth transistor M6 is connected to the input enhancement node M.

The operation sequence of the shift register unit shown in fig. 6 may be referred to as shown in fig. 5, and the detailed operation process is not repeated here. Compared with the case that the auxiliary input circuit 4 in fig. 4 only includes the fourth transistor M4, the auxiliary input circuit 4 in fig. 6 includes not only the fourth transistor M4 and the sixth transistor M6, which can effectively increase the load between the input enhancement node M and the first power terminal, and reduce the current between the input enhancement node M and the first power terminal, so as to prevent the circuit from being damaged due to the excessive current; specifically, when the sensing precharge preparation circuit 2 and the auxiliary input circuit 4 charge the input boost node M at the same time, the current flowing through the third transistor M3 may be large, and by reducing the current in the auxiliary input circuit 4, the current flowing through the third transistor M3 may be effectively reduced.

Fig. 7 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure, as shown in fig. 7, in some embodiments, the sensing and pre-charging preparation circuit 2 includes not only the second transistor M2 in the previous embodiments, but also an eighth transistor M8, where the eighth transistor M8 is located between the second transistor M2 and the input enhancement node M, and the second pole of the second transistor M2 is connected to the input enhancement node M through the eighth transistor M8; the control electrode of the eighth transistor M8 is connected to the clock signal input terminal CLKA, the first electrode of the eighth transistor M8 is connected to the second electrode of the second transistor M2, and the second electrode of the eighth transistor M8 is connected to the input boost node M.

Fig. 8 is a timing chart showing an operation of the shift register unit shown in fig. 7, and the shift register unit shown in fig. 7 includes p 1-p 4 phases similar to the operation of the shift register unit shown in fig. 4, except that the input boost node M is always in a high state in the shift register unit shown in fig. 7.

Specifically, in the p1 stage, the p3 stage and the p4 stage, the clock control signal input terminal CLKA provides a low level signal, so the third transistor M3 and the eighth transistor M8 are in an off state, and the input enhancement node M is in a floating state, and the high level voltage VDD2 provided by the first power supply terminal can be written into the input enhancement node M through the fourth transistor M4, and the input enhancement node M maintains a high level state. In the p2 stage, the clock signal input terminal CLKA provides a high level signal, the second transistor M2 and the eighth transistor M8 are in a conductive state, and at this time, the high level signal provided by the clock signal input terminal CLKA is written into the input boost node M through the second transistor M2 and the eighth transistor M8, and the input boost node M is in a high level state.

Compared with the previous embodiment, since the input enhancing node M is always in the high level state, the third transistor M3 is turned on at the instant of providing the high level signal at the clock signal input terminal CLKA, and the input enhancing node M in the high level state can immediately charge the first pull-up node PU1, so that the input speed of the sensing cascade signal of the shift register unit can be effectively improved.

Fig. 9 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure, as shown in fig. 9, in the embodiment shown in fig. 9, the auxiliary input circuit 4 includes a fourth transistor M4 and a sixth transistor M6, and the sensing precharge preparation circuit 2 includes a second transistor M2 and an eighth transistor M8. The shift register unit shown in fig. 9 combines the advantages of the shift register units provided in fig. 4, 6 and 7.

Fig. 10 is a schematic diagram of still another circuit structure of a shift register unit according to an embodiment of the present disclosure, as shown in fig. 10, in some embodiments, the shift register unit further includes a first display precharge circuit 7 and a second drive output circuit 9.

The first display precharge circuit 7 is connected to the display signal INPUT terminal INPUT1, the third power supply terminal, and the first pull-up node PU1, and the first display precharge circuit 7 is configured to write the inactive level signal provided by the third power supply terminal into the first pull-up node PU1 in response to the control of the active level signal provided by the display signal INPUT terminal INPUT 1.

The second driving output circuit 9 is connected to the first pull-up node PU1, the second driving clock signal input terminal CLKD, and the second driving signal output terminal OUT1, and the second driving output circuit 9 is configured to write a signal provided by the second driving clock signal input terminal CLKD to the second driving signal output terminal OUT1 in response to control of an active level signal at the first pull-up node PU1.

The shift register unit shown in fig. 10 has not only a sensing driving function, i.e., providing a driving signal to the second gate line G2 in fig. 1, but also a display driving function, i.e., providing a driving signal to the first gate line G1 in fig. 1. That is, the first gate line G1 and the second gate line G2 in the display panel can be driven by the same gate driving circuit, so that the number of gate driving circuits configured in the display panel can be effectively reduced, which is beneficial to the design of narrow frames of products.

In some embodiments, the shift register unit further includes a first display reset circuit 8, a first pull-down control circuit 11, a first pull-up noise reduction circuit 12, and a cascade output circuit 13.

The first display reset circuit 8 is connected to the display reset signal input terminal RST, the second power supply terminal, and the first pull-up node PU1, and the first display reset circuit 8 is configured to write the inactive level signal provided by the second power supply terminal into the first pull-up node PU1 in response to the control of the active level signal provided by the sensing reset signal input terminal T-RST.

The first pull-down control circuit 11 is connected to the second power supply terminal, the fifth power supply terminal, the first pull-up node PU1, and the first pull-down node PD1, and the first pull-down control circuit 11 is configured to write a voltage to the first pull-down node PD1 that is inverted from the voltage at the first pull-up node PU1.

The first pull-up noise reduction circuit 12 is connected to the second power supply terminal, the first pull-up node PU1 and the first pull-down node PD1, and the first pull-up noise reduction circuit 12 is configured to write the inactive level signal provided by the second power supply terminal to the first pull-up node PU1 in response to control of the active level signal at the first pull-down node PD 1.

The cascade output circuit 13 is connected to the first pull-up node PU1, the first pull-down node PD1, the second power supply terminal, the cascade clock signal input terminal CLKC, and the cascade signal output terminal CR, and the cascade output circuit 13 is configured to write a signal provided by the cascade clock signal input terminal CLKC to the cascade signal output terminal CR in response to control of an active level signal at the first pull-up node PU1, and to write an inactive level signal provided by the second power supply terminal to the cascade signal output terminal CR in response to control of an active level signal at the first pull-down node PD 1.

At this time, the first driving output circuit 5 is further connected to the first pull-down node PD1 and the fourth power supply terminal, and the first driving output circuit 5 is further configured to write the inactive level signal provided from the fourth power supply terminal to the first driving signal output terminal OUT2 in response to the control of the active level signal at the first pull-down node PD 1.

The second driving output circuit 9 is further connected to the first pull-down node PD1 and the fourth power supply terminal, and the second driving output circuit 9 is further configured to write the inactive level signal provided by the fourth power supply terminal to the second driving signal output terminal OUT1 in response to control of the active level signal at the first pull-down node PD 1.

Fig. 11 is a schematic circuit diagram of another embodiment of a shift register unit according to the present disclosure, where, as shown in fig. 11, the shift register unit shown in fig. 11 is an implementation alternative implementation of the shift register unit shown in fig. 10, and the sense control circuit 1, the sense pre-charge preparation circuit 2, the first sense pre-charge circuit 3, and the auxiliary input circuit 4 in the shift register unit shown in fig. 11 may be as shown in fig. 4, fig. 6, fig. 7, and fig. 9, and the sense control circuit 1, the sense pre-charge preparation circuit 2, the first sense pre-charge circuit 3, and the auxiliary input circuit 4 in the shift register unit shown in fig. 11 are as examples shown in fig. 9.

In some embodiments, the first display precharge circuit 7 includes a ninth transistor M9, the first display reset circuit 8 includes a tenth transistor M10, the first pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13, the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14, the first drive output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17, the second drive output circuit 9 includes a fifteenth transistor M15 and an eighteenth transistor M18, and the cascade output drop circuit includes a sixteenth transistor M16 and a nineteenth transistor M19.

The control electrode of the ninth transistor M9 is connected to the display signal INPUT terminal INPUT1, the first electrode of the ninth transistor M9 is connected to the third power supply terminal, and the second electrode of the ninth transistor M9 is connected to the first pull-up node PU 1.

The control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, the first electrode of the tenth transistor M10 is connected to the first pull-up node PU1, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal.

The control electrode of the twelfth transistor M12 is connected to the fifth power supply terminal, the first electrode of the twelfth transistor M12 is connected to the fifth power supply terminal, and the second electrode of the twelfth transistor M12 is connected to the first pull-down node PD 1.

The control electrode of the thirteenth transistor M13 is connected to the first pull-up node PU1, the first electrode of the thirteenth transistor M13 is connected to the first pull-down node PD1, and the second electrode of the thirteenth transistor M13 is connected to the second power supply terminal.

The control electrode of the fourteenth transistor M14 is connected to the first pull-down node PD1, the first electrode of the fourteenth transistor M14 is connected to the first pull-up node PU1, and the second electrode of the fourteenth transistor M14 is connected to the second power supply terminal.

A control electrode of the seventeenth transistor M17 is connected to the first pull-down node PD1, a first electrode of the seventeenth transistor M17 is connected to the first driving signal output terminal OUT2, and a second electrode of the seventeenth transistor M17 is connected to the fourth power supply terminal.

The control electrode of the fifteenth transistor M15 is connected to the first pull-up node PU1, the first electrode of the fifteenth transistor M15 is connected to the second driving clock signal input terminal CLKD, and the second electrode of the fifteenth transistor M15 is connected to the second driving signal output terminal OUT 1.

The gate of the eighteenth transistor M18 is connected to the first pull-down node PD1, the first gate of the eighteenth transistor M18 is connected to the second driving signal output terminal OUT1, and the second gate of the eighteenth transistor M18 is connected to the fourth power supply terminal.

The control electrode of the sixteenth transistor M16 is connected to the first pull-up node PU1, the first electrode of the sixteenth transistor M16 is connected to the cascade driving clock signal input terminal CLKC, and the second electrode of the sixteenth transistor M16 is connected to the cascade signal output terminal CR.

The control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD1, the first electrode of the nineteenth transistor M19 is connected to the cascade signal output terminal CR, and the second electrode of the nineteenth transistor M19 is connected to the fourth power supply terminal.

In some embodiments, the second capacitor C2 and the third capacitor C3 are respectively configured at the first driving signal output terminal OUT2 and the second driving signal output terminal OUT 1.

Fig. 12 is a timing chart of an operation of the shift register unit shown in fig. 11, wherein the first power terminal provides the high level voltage VDD2, the second power terminal provides the low level voltage VGL1, the third power terminal provides the high level voltage VDD1, the fourth power terminal provides the low level voltage VGL2, and the fifth power terminal provides the high level voltage VDDA. The operation of the shift register unit includes:

in the precharge phase T1, the display signal INPUT terminal INPUT1 provides a high level signal, the sensing signal INPUT terminal INPUT2 provides a low level signal, the random signal INPUT terminal OE provides a low level signal, the clock control signal INPUT terminal CLKA provides a low level signal, the display reset signal INPUT terminal RST provides a low level signal, and the sensing reset signal INPUT terminal T-RST provides a low level signal.

Since the display signal INPUT terminal INPUT1 provides a high level signal, the ninth transistor M9 is turned on, the high level voltage VDD1 provided by the third power supply terminal is written to the first pull-up node PU1 through the ninth transistor M9, the voltage at the first pull-up node PU1 is in a high level state, at this time, the thirteenth transistor M13, the fifth transistor M5, the fifteenth transistor M15 and the sixteenth transistor M16 are all turned on, the low level signal provided by the second power supply terminal is written to the first pull-down node PD1 through the thirteenth transistor M13, the low level signal provided by the first driving clock signal INPUT terminal CLKE is written to the first driving signal output terminal OUT2 through the fifth transistor M5, the low level signal provided by the second driving clock signal INPUT terminal CLKD is written to the second driving signal output terminal OUT1 through the fifteenth transistor M15, that is, the low level signal provided by the cascade clock signal INPUT terminal CLKC is written to the cascade signal output terminal CR through the sixteenth transistor M16, that is, the first driving signal output terminal OUT2, the second driving signal output terminal OUT1 and the cascade signal output terminal OUT1 are all low level signals.

In the display output stage T2, the display signal INPUT terminal INPUT1 provides a low level signal, the sensing signal INPUT terminal INPUT2 provides a high level signal, the random signal INPUT terminal OE provides a high level signal, the clock control signal INPUT terminal CLKA provides a low level signal, the display reset signal INPUT terminal RST provides a low level signal, and the sensing reset signal INPUT terminal T-RST provides a low level signal.

Since the random signal INPUT end OE provides a high level signal, the first transistor M1 is turned on, the high level signal provided by the sensing signal INPUT end INPUT2 is written into the sensing control node H, and the voltage at the sensing control node H is in a high level state. Accordingly, the second transistor M2 is turned on, and the low level signal provided from the clock control signal input terminal CLKA is written to the first pole of the eighth transistor M8 through the second transistor M2.

Since the clock control signal input terminal CLKA provides a low level signal, the third transistor M3 and the eighth transistor M8 are turned off, the input enhancement node M is in a floating state, the high level signal provided by the first power supply terminal is written into the input enhancement node M through the fourth transistor M4 and the sixth transistor M6, and the input enhancement node M is in a high level state.

Since the first pull-up node PU1 is in the high state, the thirteenth transistor M13, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all maintained on, the first driving clock signal input terminal CLKE continues to write signals to the first driving signal output terminal OUT2, the second driving clock signal input terminal CLKD continues to write signals to the second driving signal output terminal OUT1, and the cascade clock signal input terminal CLKC continues to write signals to the cascade signal output terminal CR. In this process, the first driving clock signal input terminal CLKE, the second driving clock signal input terminal CLKD and the cascade signal input terminal CLKC each input a high level signal and then a low level signal, so the first driving signal output terminal OUT2, the second driving signal output terminal OUT1 and the cascade signal output terminal CR output a high level signal and then a low level signal. It should be noted that, in the process of switching the first driving signal output terminal OUT2 and the second driving signal output terminal OUT1 from outputting the low level signal to outputting the high level signal, under the bootstrap action of the second capacitor C2 and the third capacitor C3, the voltage at the first pull-up node PU1 is pulled up to a higher level; in the process of switching the first driving signal output terminal OUT2 and the second driving signal output terminal OUT1 from outputting the high level signal to outputting the low level signal, under the bootstrap action of the second capacitor C2, the voltage at the first pull-up node PU1 is pulled down to the initial high level state.

In the display reset phase T3, the display signal INPUT terminal INPUT1 provides a low level signal, the sensing signal INPUT terminal INPUT2 provides a low level signal, the random signal INPUT terminal OE provides a low level signal, the clock control signal INPUT terminal CLKA provides a low level signal, the display reset signal INPUT terminal RST provides a high level signal, and the sensing reset signal INPUT terminal T-RST provides a low level signal.

Since the display reset signal input terminal RST provides a high level signal, the tenth transistor M10 is turned on, and at this time, the low level signal provided by the second power supply terminal is written into the first pull-up node PU1 through the tenth transistor M10, and the voltage at the first pull-up node PU1 is in a low level state; at the same time, the thirteenth transistor M13 is turned off, the high level signal provided by the fifth power terminal is written to the first pull-down node PD1 through the twelfth transistor M12, the first pull-down node PD1 is in the high level state, and the fourteenth transistor M14, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all turned on.

When the fourteenth transistor M14 is turned on, the low level signal provided by the second power supply terminal is written into the first pull-up node PU1 through the fourteenth transistor M14 to reduce noise of the first pull-up node PU 1. When the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all turned on, the low-level signal provided from the second power supply terminal is written to the first driving signal output terminal OUT2 and the second driving signal output terminal OUT1 through the seventeenth transistor M17 and the eighteenth transistor M18, respectively, and the low-level signal provided from the fourth power supply terminal is written to the cascade signal output terminal CR through the nineteenth transistor M19, that is, the first driving signal output terminal OUT2, the second driving signal output terminal OUT1, and the cascade signal output terminal CR each output the low-level signal.

In the sensing precharge phase T4, the display signal INPUT terminal INPUT1 provides a low level signal, the sensing signal INPUT terminal INPUT2 provides a low level signal, the random signal INPUT terminal OE provides a low level signal, the clock control signal INPUT terminal CLKA provides a high level signal, the display reset signal INPUT terminal RST provides a low level signal, and the sensing reset signal INPUT terminal T-RST provides a low level signal.

Since the voltage at the sensing control node H maintains the high state of the previous stage, the second transistor M2 is maintained on, and the clock control signal input CLKA provides a high signal to be written into the input boost node M through the second transistor M2 and the eighth transistor M8. In the previous stage, since the third transistor M3 and the eighth transistor M8 are both in the off state, the high level voltage VDD2 provided by the first power terminal is written to the input boost node M through the fourth transistor M4 and the sixth transistor M6, so the input boost node M is always maintained in the high level state in the previous stage. After the clock control signal input terminal CLKA inputs the high level signal, the third transistor M3 and the eighth transistor M8 are turned on, the high level signal at the input boost node M can be quickly written to the first pull-up node PU1 through the third transistor M3. Therefore, the shift register unit provided by the disclosure has a strong input capability of sensing cascade signals.

Since the first pull-up node PU1 is in a high level state, the thirteenth transistor M13, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all turned on, the low level signal provided from the second power supply terminal is written to the first pull-down node PD1 through the thirteenth transistor M13, the low level signal provided from the first driving clock signal input terminal CLKE is written to the first driving signal output terminal OUT2 through the fifth transistor M5, the low level signal provided from the second driving clock signal input terminal CLKD is written to the second driving signal output terminal OUT1 through the fifteenth transistor M15, and the low level signal provided from the cascade clock signal input terminal CLKC is written to the cascade signal output terminal CR through the sixteenth transistor M16, that is, the first driving signal output terminal OUT2, the second driving signal output terminal OUT1, and the cascade signal output terminal CR all output the low level signal.

In the sense output stage T5, the display signal INPUT terminal INPUT1 provides a low level signal, the sense signal INPUT terminal INPUT2 provides a low level signal, the random signal INPUT terminal OE provides a low level signal, the clock control signal INPUT terminal CLKA provides a low level signal, the display reset signal INPUT terminal RST provides a low level signal, and the sense reset signal INPUT terminal T-RST provides a low level signal.

Since the clock control signal input terminal CLKA provides a low level signal, both the third transistor M3 and the eighth transistor M8 are turned off. At this time, the first pull-up node PU1 maintains the high state of the previous stage, and the thirteenth transistor M13, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 all maintain on. In this process, the second driving clock signal input terminal CLKD and the cascade driving clock signal input terminal both provide a low level signal, so the second driving signal output terminal OUT1 and the cascade signal output terminal CR both output a low level signal. Meanwhile, the first driving clock signal input terminal CLKE inputs a high level signal and then inputs a low level signal, so the first driving signal output terminal OUT2 outputs a high level signal and then outputs a low level signal. Under the bootstrap action of the second capacitor C2, the voltage at the first pull-up node PU1 is pulled up and then pulled down.

In the sense reset phase T6, the display signal INPUT terminal INPUT1 provides a low level signal, the sense signal INPUT terminal INPUT2 provides a low level signal, the random signal INPUT terminal OE provides a high level signal, the clock control signal INPUT terminal CLKA provides a low level signal, the display reset signal INPUT terminal RST provides a low level signal, and the sense reset signal INPUT terminal T-RST provides a high level signal.

Since the random signal INPUT terminal OE provides a high level signal, the first transistor M1 is turned on, and at this time, the low level signal provided by the sensing signal INPUT terminal INPUT2 is written to the sensing control node H through the first transistor M1, and the voltage at the sensing control node H is in a low level state.

Since the sensing reset signal input terminal T-RST provides a high level signal, the seventh transistor M7 is turned on, and at this time, the low level signal provided by the second power terminal is written into the first pull-up node PU1 through the seventh transistor M7, and the voltage at the first pull-up node PU1 is in a low level state; at the same time, the thirteenth transistor M13 is turned off, the high level signal provided by the fifth power terminal is written to the first pull-down node PD1 through the twelfth transistor M12, the first pull-down node PD1 is in the high level state, and the fourteenth transistor M14, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all turned on.

In the embodiment of the present disclosure, the cascade clock signal input terminal CLKC and the second driving clock signal input terminal CLKD may input the same clock signal, so they may be the same clock signal input terminal.

Fig. 13 is a schematic diagram of still another circuit structure of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 13, unlike in the previous embodiment, the first display precharge circuit 7 in the embodiment shown in fig. 13 includes: a ninth transistor M9 and an eleventh transistor M11; a control electrode of the ninth transistor M9 is connected to the display signal INPUT terminal INPUT1, a first electrode of the ninth transistor M9 is connected to the third power supply terminal, and a second electrode of the ninth transistor M9 is connected to the first electrode of the eleventh transistor M11; the control electrode of the eleventh transistor M11 is connected to the display signal INPUT terminal INPUT1, the first electrode of the eleventh transistor M11 is connected to the INPUT boost node M, and the second electrode of the eleventh transistor M11 is connected to the first pull-up node PU 1.

In the embodiment of the disclosure, the second pole of the ninth transistor M9 and the first pole of the eleventh transistor M11 are both connected to the input enhancement node M, so that in the process of writing the active level signal representing the display cascade into the first pull-up node PU1 by the first display precharge circuit 7, the auxiliary input circuit 4 also charges the input enhancement node M, which can effectively improve the input capability of the display cascade signal of the shift register unit. Specifically, when the display signal INPUT terminal INPUT1 provides a high level signal, the ninth transistor M9 and the eleventh transistor M11 are turned on, and the high level signal provided at the third power terminal may be written to the first pull-up node PU1 through the ninth transistor M9 and the eleventh transistor M11, and at the same time, the high level signal provided at the first power terminal may be written to the first pull-up node PU1 through the fourth transistor M4, the sixth transistor M6 and the eleventh transistor M11, so that the voltage at the first pull-up node PU1 may be rapidly charged to a high level state. Therefore, the technical scheme of the present disclosure can effectively improve the input capability of the display cascade of the shift register unit.

Fig. 14 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure, and as shown in fig. 14, unlike the previous embodiment, the shift register unit according to the embodiment of the present disclosure further includes: a first voltage control circuit 14; the first voltage control circuit 14 is connected to the active level supply terminal, the first pull-up node PU1, and the first voltage control node OFF1, and the first voltage control circuit 14 is configured to write the active level signal provided by the active level supply terminal into the first voltage control node OFF1 in response to control of the active level signal at the first pull-up node PU 1.

The shift register unit further includes at least one of a first leakage preventing circuit 15, a second leakage preventing circuit 16, and a third leakage preventing circuit 17.

The first sensing reset circuit 6 is connected to the second power supply terminal through a first anti-leakage circuit 15, the first sensing reset circuit 6 is connected to the first anti-leakage circuit 15 by a first anti-leakage node Q1, the first anti-leakage node Q1 is connected to a first voltage control node OFF1, the first anti-leakage circuit 15 is connected to a sensing reset signal input terminal T-RST, the first anti-leakage circuit 15 is configured to form a path between the first anti-leakage node Q1 and the second power supply terminal in response to control of an active level signal provided by the sensing reset signal input terminal T-RST, and to break a circuit between the first anti-leakage node Q1 and the second power supply terminal in response to control of an inactive level signal provided by the sensing reset signal input terminal T-RST.

Alternatively, in the same gate driving circuit, the sense reset signal input terminals T-RST configured by the shift registers located at different stages are connected to the same sense reset signal input line TRST'. For details, see the description below.

The first display reset circuit 8 is connected to the second power supply terminal through the first anti-leakage circuit 16, the first display reset circuit 8 is connected to the first anti-leakage circuit 16 at the second anti-leakage node Q2, the second anti-leakage node Q2 is connected to the first voltage control node OFF1, the first anti-leakage circuit 16 is connected to the display reset signal input terminal RST, the first anti-leakage circuit 16 is configured to enable a path to be formed between the second anti-leakage node Q2 and the second power supply terminal in response to control of an active level signal provided by the display reset signal input terminal RST, and enable a circuit to be broken between the second anti-leakage node Q2 and the second power supply terminal in response to control of an inactive level signal provided by the display reset signal input terminal RST.

Optionally, in the same gate driving circuit, the display reset signal input end RST configured by any one stage of shift register unit except the last two stages of shift registers is connected with the cascade signal output end of the last two stages of shift registers. For details, see the description below.

The first pull-up noise reduction circuit 12 is connected to the second power supply terminal through a third anti-leakage circuit 17, the first pull-up noise reduction circuit 12 is connected to a third anti-leakage node Q3 through the third anti-leakage circuit 17, the third anti-leakage node Q3 is connected to the first voltage control node OFF1, the third anti-leakage circuit 17 is connected to the first pull-down node PD1, the third anti-leakage circuit 17 is configured to enable a path to be formed between the third anti-leakage node Q3 and the second power supply terminal in response to control of an active level signal at the first pull-down node PD1, and enable a circuit to be broken between the third anti-leakage node Q3 and the second power supply terminal in response to control of an inactive level signal at the first pull-down node PD 1.

Referring to fig. 14, in some embodiments, the active level supply terminal is a third power terminal. As an example, the third power supply terminal supplies the high level voltage VDD1.

In some embodiments, the first voltage control circuit 14 includes a twentieth transistor M20, a control electrode of the twentieth transistor M20 is connected to the first pull-up node PU1, a first electrode of the twentieth transistor M20 is connected to the active level supply terminal, and a second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF 1.

In some embodiments, the first anti-leakage circuit 15 includes a twenty-first transistor M21, the control electrode of the twenty-first transistor M21 is connected to the sensing reset signal input terminal T-RST, the first electrode of the twenty-first transistor M21 is connected to the sensing reset circuit and the first voltage control node OFF1, and the second electrode of the second transistor M22 is connected to the second power supply terminal.

In some embodiments, the first anti-leakage circuit 16 includes a twenty-second transistor M22, the control electrode of the twenty-second transistor M22 is connected to the display reset signal input terminal RST, the first electrode of the twenty-second transistor M22 is connected to the display reset circuit and the first voltage control node OFF1, and the second electrode of the twenty-second transistor M22 is connected to the second power supply terminal.

In some embodiments, the third anti-leakage circuit 17 includes: the control electrode of the twenty-third transistor M23 is connected to the first pull-down node PD1, the first electrode of the twenty-third transistor M23 is connected to the first pull-down control circuit and the first voltage control node OFF1, and the second electrode of the twenty-third transistor M23 is connected to the second power supply terminal.

In fig. 14, a case where the shift register unit includes the first leakage preventing circuit 15, the first leakage preventing circuit 16, and the third leakage preventing circuit 17 is exemplified. In practical applications, at least one of the first anti-leakage circuit 15, the first anti-leakage circuit 16, and the third anti-leakage circuit 17 may be set according to practical needs.

Fig. 15 is a schematic circuit diagram of another shift register unit according to an embodiment of the disclosure, as shown in fig. 15, in some embodiments, when the auxiliary input circuit 4 includes a fourth transistor M4 and a sixth transistor M6, a control electrode of the fourth transistor M4 is connected to the first power supply terminal, a first electrode of the fourth transistor M4 is connected to the first power supply terminal, and a second electrode of the fourth transistor M4 and a first electrode of the sixth transistor M6 are connected to the active level output node; a control electrode of the sixth transistor M6 is connected with the first power supply end, and a second electrode of the sixth transistor M6 is connected with the input enhancement node M; the active level supply terminal is an active level output node.

Unlike the technical means that the first pole of the twentieth transistor M20 is directly connected to the third power supply terminal in the previous embodiment, in the embodiment of the present disclosure, the first pole of the twentieth transistor M20 is connected to the first power supply terminal through the fourth transistor M4 of the circuit of the auxiliary input circuit 4, and due to the presence of the fourth transistor M4 (which can be regarded as a load), the current flowing through the twentieth transistor M20 can be reduced, which is beneficial to increase the usage of the twentieth transistor M20.

Referring again to fig. 14 and 15, in some embodiments, the shift register cell further includes a first pull-down noise reduction circuit 18 and/or a second pull-down noise reduction circuit 19.

The first pull-down noise reduction circuit 18 is connected to the first pull-down node PD1, the second power supply terminal, the sensing control node H, and the clock control signal input terminal CLKA, and the first pull-down noise reduction circuit 18 is configured to write the inactive level signal provided by the second power supply terminal into the first pull-down node PD1 in response to control of the active level signal at the sensing control node H and the active level signal provided by the clock control signal input terminal CLKA, so as to perform noise reduction on the output voltage of the first pull-down node PD 1.

The second pull-down noise reduction circuit 19 is connected to the first pull-down node PD1, the second power supply terminal, and the sensing signal INPUT terminal INPUT2, and the second pull-down noise reduction circuit 19 is configured to write the inactive level signal provided by the second power supply terminal to the first pull-down node PD1 in response to the control of the active level signal provided by the sensing signal INPUT terminal INPUT2, so as to perform noise reduction on the output voltage of the first pull-down node PD 1.

In some embodiments, the first pull-down noise reduction circuit 18 includes a twenty-ninth transistor M29 and a thirty-first transistor M30, and the second pull-down noise reduction circuit 19 includes a thirty-first transistor M31.

The control electrode of the twenty-ninth transistor M29 is connected to the clock signal input terminal CLKA, the first electrode of the twenty-ninth transistor M29 is connected to the first pull-down node PD1, and the second electrode of the twenty-ninth transistor M29 is connected to the first electrode of the thirty-second transistor M30.

The control electrode of the thirty-second transistor M30 is connected to the sensing control node H, and the second electrode of the thirty-second transistor M30 is connected to the second power supply terminal.

The control electrode of the thirty-first transistor M31 is connected to the sensing signal INPUT terminal INPUT2, the first electrode of the thirty-first transistor M31 is connected to the first pull-down node PD1, and the second electrode of the thirty-first transistor M31 is connected to the second power supply terminal.

Fig. 16 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure, where, as shown in fig. 16, the shift register unit shown in fig. 16 includes not only the first driving output circuit 5 and the second driving output circuit 9 in the previous embodiment, but also: a second sensing precharge circuit, a second display precharge circuit 27, a third drive output circuit 25, and a fourth drive output circuit 29.

The second sensing precharge circuit is connected with the clock control signal input end CLKA, the input enhancement node M and the second pull-up node PU2, and is configured to write the voltage at the input enhancement node M into the second pull-up node PU2 in response to the control of the active level signal provided by the clock control signal input end CLKA;

the second display precharge circuit 27 is connected to the display signal INPUT terminal INPUT1 and the second pull-up node PU2, and the second display precharge circuit 27 is configured to write an active level signal to the second pull-up node PU2 in response to control of the active level signal provided by the display signal INPUT terminal INPUT 1;

the third driving output circuit 25 is connected to the second pull-up node PU2, the third driving clock signal input terminal CLKE ', and the third driving signal output terminal, and the third driving output circuit 25 is configured to write the signal provided by the third driving clock signal input terminal CLKE' into the third driving signal output terminal in response to the control of the active level signal at the second pull-up node PU2;

the fourth driving output circuit 29 is connected to the second pull-up node PU2, the fourth driving clock signal input CLKD ', and the fourth driving signal output, and the fourth driving output circuit 29 is configured to write a signal provided by the fourth driving clock signal input CLKD' to the fourth driving signal output in response to control of the active level signal at the second pull-up node PU 2.

In the embodiment of the disclosure, the first driving output circuit 5 and the second driving output circuit 9 may be used to provide corresponding driving signals to two gate lines G2 and G1 configured by a pixel unit in a certain row in the display panel, and at the same time, the third driving output circuit 25 and the fourth driving output circuit 29 may be used to provide corresponding driving signals to two gate lines G2 and G1 configured by a pixel unit in another row in the display panel. That is, the shift register unit provided in the present embodiment can be used to drive four gate lines configured by two rows of pixel units (e.g., two adjacent rows of pixel units). Through the design, the number of stages of the shift register unit in the gate driving circuit can be effectively reduced, the occupied size of the gate driving circuit is reduced, and the narrow frame design of a product is facilitated.

In some embodiments, the shift register unit further includes: a second sense reset circuit 26, a second display reset circuit 28, a second pull-down control circuit 31, and a second pull-up noise reduction circuit 32.

The second sense reset circuit 26 is connected to the sense reset signal input terminal T-RST, the inactive level supply terminal, and the second pull-up node PU2, and the second sense reset circuit 26 is configured to write the inactive level signal provided by the inactive level supply terminal to the second pull-up node PU2 in response to control of the active level signal provided by the sense reset signal input terminal T-RST.

The second display reset circuit 28 is connected to the display reset signal input terminal RST, the inactive level supply terminal, and the second pull-up node PU2, and the second display reset circuit 28 is configured to write the inactive level signal provided from the inactive level supply terminal to the second pull-up node PU2 in response to control of the active level signal provided from the display reset signal input terminal RST.

The second pull-down control circuit 31 is connected to the second power supply terminal, the sixth power supply terminal, the second pull-up node PU2, and the second pull-down node PD2, and the second pull-down control circuit 31 is configured to write a voltage to the second pull-down node PD2 that is opposite to the voltage at the second pull-up node PU2. The sixth power terminal provides a sixth operating voltage VDDB.

The second pull-up noise reduction circuit 32 is connected to the inactive level supply terminal, the second pull-up node PU2, and the second pull-down node PD2, and the second pull-up noise reduction circuit 32 is configured to write the inactive level signal provided by the inactive level supply terminal to the second pull-up node PU2 in response to control of the active level signal at the second pull-down node PD 2.

At this time, the third driving output circuit 25 is further connected to the second pull-down node PD2 and the fourth power supply terminal, and the third driving output circuit 25 is further configured to write the inactive level signal provided from the fourth power supply terminal to the third driving signal output terminal in response to the control of the active level signal at the second pull-down node PD 2.

The fourth driving output circuit 29 is further connected to the second pull-down node PD2 and the fourth power supply terminal, and the fourth driving output circuit 29 is further configured to write the inactive level signal provided by the fourth power supply terminal to the fourth driving signal output terminal in response to control of the active level signal at the second pull-down node PD 2.

Fig. 17 is a schematic circuit diagram of another circuit structure of the shift register unit according to the embodiment of the present disclosure, as shown in fig. 17, for the specific circuit structures of the sensing control circuit 1, the sensing precharge preparation circuit 2, the first sensing precharge circuit 3, the first display precharge circuit 7, the auxiliary input circuit 4, the sensing reset circuit, the display reset circuit, the first driving output circuit 5, the second driving output circuit 9, the cascade output circuit 13, the first pull-down control circuit 11, and the first pull-up noise reduction circuit 12 in the embodiment, the details of which are described in the previous embodiments will be omitted here.

In some embodiments, the second display precharge circuit 27 includes a thirty-ninth transistor M39, a control electrode of the thirty-ninth transistor M39 is connected to the display signal INPUT terminal INPUT1, a first electrode of the thirty-ninth transistor M39 is connected to the third power supply terminal, and a second electrode of the thirty-ninth transistor M39 is connected to the second pull-up node PU 2.

In some embodiments, the second sensing precharge circuit includes a thirteenth transistor M33, a control electrode of the thirteenth transistor M33 is connected to the clock signal input terminal CLKA, a first electrode of the thirty-third transistor M33 is connected to the input boost node M, and a second electrode of the thirty-third transistor M33 is connected to the second pull-up node PU 2.

The third driving output circuit 25 includes a thirty-fifth transistor M35 and a forty-seventh transistor M47, and the fourth driving output circuit 29 includes a forty-fifth transistor M45 and a forty-eighth transistor M48.

The control electrode of the thirty-fifth transistor M35 is connected to the second pull-up node PU2, the first electrode of the thirty-fifth transistor M35 is connected to the third driving clock signal input terminal CLKE', and the second electrode of the thirty-fifth transistor M35 is connected to the third driving signal output terminal.

The control electrode of the forty-seventh transistor M47 is connected to the second pull-down node PD2, the first electrode of the forty-seventh transistor M47 is connected to the third driving signal output terminal, and the second electrode of the forty-seventh transistor M47 is connected to the fourth power supply terminal.

The control electrode of the forty-fifth transistor M45 is connected to the second pull-up node PU2, the first electrode of the forty-fifth transistor M45 is connected to the fourth driving clock signal input CLKD', and the second electrode of the forty-fifth transistor M45 is connected to the fourth driving signal output.

The control electrode of the forty-eight transistor M48 is connected to the second pull-down node PD2, the first electrode of the forty-eight transistor M48 is connected to the fourth driving signal output terminal, and the second electrode of the forty-eight transistor M48 is connected to the fourth power supply terminal.

In some embodiments, a fourth capacitor C4 and a fifth capacitor C5 are configured for the third and fourth drive signal outputs, respectively.

In some embodiments, the second sense reset circuit 26 includes a thirty-seventh transistor M37, the second display reset circuit 28 includes a forty-fourth transistor M40, the second pull-down control circuit 31 includes a forty-second transistor M42 and a forty-third transistor M43, and the second pull-up noise reduction circuit 32 includes a forty-fourth transistor M44.

The control electrode of the thirty-seventh transistor M37 is connected to the sense reset signal input terminal T-RST, the first electrode of the thirty-seventh transistor M37 is connected to the second pull-up node PU2, and the second electrode of the thirty-seventh transistor M37 is connected to the inactive level supply terminal.

The control electrode of the forty transistor M40 is connected to the display reset signal input terminal RST, the first electrode of the forty transistor M40 is connected to the second pull-up node PU2, and the second electrode of the forty transistor M40 is connected to the inactive level supply terminal.

The control electrode of the forty-second transistor M42 is connected to the sixth power supply terminal, the first electrode of the forty-second transistor M42 is connected to the sixth power supply terminal, and the second electrode of the forty-second transistor M42 is connected to the second pull-down node PD 2.

The control electrode of the forty-third transistor M43 is connected to the second pull-up node PU2, the first electrode of the forty-third transistor M43 is connected to the second pull-down node PD2, and the second electrode of the forty-third transistor M43 is connected to the inactive level supply terminal.

The control electrode of the forty-fourth transistor M44 is connected to the second pull-down node PD2, the first electrode of the forty-fourth transistor M44 is connected to the second pull-up node PU2, and the second electrode of the forty-fourth transistor M44 is connected to the inactive level supply terminal.

Fig. 18 is a schematic circuit diagram of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 18, unlike the case where the second display precharge circuit 27 shown in fig. 17 includes the thirty-ninth transistor M39, the second display precharge circuit 27 in the shift register unit shown in fig. 18 includes a forty-first transistor M41, a control electrode of the forty-first transistor M41 is connected to the display signal INPUT terminal INPUT1, a first electrode of the forty-first transistor M41 is connected to the INPUT enhancement node M, and a second electrode of the forty-first transistor M40 is connected to the second pull-up node PU 2.

Fig. 19 is a schematic diagram of still another circuit structure of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 19, unlike the case where the second display precharge circuit 27 shown in fig. 17 and 18 includes the thirty-ninth transistor M39 or the forty-first transistor M41, the second display precharge circuit 27 in the shift register unit shown in fig. 19 includes the thirty-ninth transistor M39 and the forty-first transistor M41.

The control electrode of the thirty-ninth transistor M39 is connected to the display signal INPUT terminal INPUT1, the first electrode of the thirty-ninth transistor M39 is connected to the third power supply terminal, and the second electrode of the thirty-ninth transistor M39 is connected to the first electrode of the forty-first transistor M41; the control electrode of the forty-first transistor M41 is connected to the display signal INPUT terminal INPUT1, the first electrode of the forty-first transistor M41 is connected to the INPUT enhancement node M, and the second electrode of the forty-first transistor M41 is connected to the second pull-up node PU 2.

Referring to fig. 17-19, in some embodiments, the inactive level supply terminal is a second power terminal.

Fig. 20 is a schematic diagram of still another circuit structure of a shift register unit according to an embodiment of the disclosure, as shown in fig. 20, in some embodiments, the shift register unit further includes: a second voltage control circuit; the second voltage control circuit 34 is connected to the active level supply terminal, the first pull-up node PU1, and the second voltage control node OFF2, and the second voltage control circuit 34 is configured to write the active level signal provided by the active level supply terminal into the second voltage control node OFF2 in response to control of the active level signal at the second pull-up node PU 2.

The shift register unit further includes: at least one of the fourth leakage preventing circuit 35, the fifth leakage preventing circuit 36, and the sixth leakage preventing circuit 37.

The second sensing reset circuit 26 is connected to the second power supply terminal through a fourth anti-leakage circuit 35, the second sensing reset circuit 26 is connected to a fourth anti-leakage node Q4 through the fourth anti-leakage circuit 35, the fourth anti-leakage node Q4 is connected to the second voltage control node OFF2, the fourth anti-leakage circuit 35 is connected to the sensing reset signal input terminal T-RST, the fourth anti-leakage circuit 35 is configured to form a path between the fourth anti-leakage node Q4 and the second power supply terminal in response to control of an active level signal provided by the sensing reset signal input terminal T-RST, and to open a circuit between the fourth anti-leakage node Q4 and the second power supply terminal in response to control of an inactive level signal provided by the cascade reset signal input terminal.

The second display reset circuit 28 is connected to the second power supply terminal through a fifth anti-leakage circuit 36, the second display reset circuit 28 is connected to a fifth anti-leakage node Q5 with the fifth anti-leakage circuit 36, the fifth anti-leakage node Q5 is connected to the second voltage control node OFF2, the fifth anti-leakage circuit 36 is connected to the display reset signal input terminal RST, the fifth anti-leakage circuit 36 is configured to enable a path to be formed between the fifth anti-leakage node Q5 and the second power supply terminal in response to control of an active level signal provided by the display reset signal input terminal RST, and enable a circuit to be broken between the fifth anti-leakage node Q5 and the second power supply terminal in response to control of an inactive level signal provided by the cascade reset signal input terminal.

The second pull-up noise reduction circuit 32 is connected to the second power supply terminal through a sixth anti-leakage circuit 37, the second pull-up noise reduction circuit 32 is connected to a sixth anti-leakage node Q6 with the sixth anti-leakage circuit 37, the sixth anti-leakage node Q6 is connected to the second voltage control node OFF2, the sixth anti-leakage circuit 37 is connected to the second pull-down node PD2, the sixth anti-leakage circuit 37 is configured to form a path between the sixth anti-leakage node Q6 and the second power supply terminal in response to control of an active level signal at the second pull-down node PD2, and to open a circuit between the sixth anti-leakage node Q6 and the second power supply terminal in response to control of an inactive level signal at the second pull-down node PD 2.

A case where the shift register unit includes the fourth anticreep circuit 35, the fifth anticreep circuit 36, and the sixth anticreep circuit 37 at the same time is exemplarily shown in fig. 20. In practical applications, at least one of the fourth anti-leakage circuit 35, the fifth anti-leakage circuit 36, and the sixth anti-leakage circuit 37 may be set according to practical needs.

In some embodiments, the second voltage control circuit 34 includes a fifty-th transistor M50, the control electrode of the fifty-th transistor M50 is connected to the first pull-up node PU1, the first electrode of the fifty-th transistor M50 is connected to the active level supply terminal, and the second electrode of the fifty-th transistor M50 is connected to the second voltage control node OFF 2.

In some embodiments, the fourth anti-leakage circuit 35 includes a fifty-first transistor M51, the control electrode of the fifty-first transistor M51 is connected to the sense reset signal input terminal T-RST, the first electrode of the fifty-first transistor M51 is connected to the sense reset circuit and the second voltage control node OFF2, and the second electrode of the fifty-transistor M52 is connected to the second power supply terminal.

In some embodiments, the fifth anti-leakage circuit 36 includes a fifth twelve transistor M52, the control electrode of the fifth twelve transistor M52 is connected to the display reset signal input RST, the first electrode of the fifty transistor M52 is connected to the display reset circuit and the second voltage control node OFF2, and the second electrode of the fifty transistor M52 is connected to the second power supply terminal.

In some embodiments, the sixth anti-leakage circuit 37 includes: the control electrode of the fifty-third transistor M53 is connected to the second pull-down node PD2, the first electrode of the fifty-third transistor M53 is connected to the second pull-down control circuit and the second voltage control node OFF2, and the second electrode of the fifty-third transistor M53 is connected to the second power supply terminal.

Fig. 21 is a schematic diagram of still another circuit structure of a shift register unit according to an embodiment of the disclosure, as shown in fig. 21, in some embodiments, when the shift register unit includes the first voltage control circuit 14, the inactive level supply terminal is the first voltage control node OFF1.

At this time, the second sensing reset circuit 26, the second display reset circuit 28, and the second pull-up noise reduction circuit 32 in the shift register unit can realize the anti-leakage by using the first anti-leakage circuit 15, the first anti-leakage circuit 16, and/or the third anti-leakage circuit 17, so that the fourth anti-leakage circuit 35, the fifth anti-leakage circuit 36, and the sixth anti-leakage circuit 37 are not required to be configured in the shift register unit, which is beneficial to simplifying the circuit structure.

Referring again to fig. 20 and 21, in some embodiments, the shift register cell further includes a third pull-down noise reduction circuit 38 and/or a fourth pull-down noise reduction circuit 39.

The third pull-down noise reduction circuit 38 is connected to the second pull-down node PD2, the second power supply terminal, the sensing control node H, and the clock control signal input terminal CLKA, and the first pull-down noise reduction circuit 18 is configured to write the inactive level signal provided by the second power supply terminal into the first pull-down node PD1 in response to control of the active level signal at the sensing control node H and the active level signal provided by the clock control signal input terminal CLKA, so as to perform noise reduction processing on the output voltage of the first pull-down node PD 1.

The fourth pull-down noise reduction circuit 39 is connected to the second pull-down node PD2, the second power supply terminal, and the sensing signal INPUT terminal INPUT2, and the second pull-down noise reduction circuit 19 is configured to write the inactive level signal provided by the second power supply terminal to the first pull-down node PD1 in response to the control of the active level signal provided by the sensing signal INPUT terminal INPUT2, so as to perform noise reduction on the output voltage of the first pull-down node PD 1.

In some embodiments, the third pull-down noise reduction circuit 38 includes a fifty-ninth transistor M59 and a sixty-first transistor M60, and the fourth pull-down noise reduction circuit 39 includes a sixty-first transistor M61.

The control electrode of the fifty-ninth transistor M59 is connected to the clock signal input terminal CLKA, the first electrode of the fifty-ninth transistor M59 is connected to the second pull-down node PD2, and the second electrode of the fifty-ninth transistor M59 is connected to the first electrode of the sixtieth transistor M60.

The control electrode of the sixty transistor M60 is connected to the sensing control node H, and the second electrode of the sixty transistor M60 is connected to the second power supply terminal.

The control electrode of the sixty-first transistor M61 is connected to the sensing signal INPUT terminal INPUT2, the first electrode of the sixty-first transistor M61 is connected to the second pull-down node PD2, and the second electrode of the sixty-first transistor M61 is connected to the second power supply terminal.

Fig. 22 is a schematic circuit diagram of another circuit structure of the shift register unit according to the embodiment of the disclosure, and as shown in fig. 22, when the first pull-down node PD1 and the second pull-down node PD2 are simultaneously configured in the shift register unit, in some embodiments, the third anti-leakage circuit 17, the first pull-up noise reduction circuit 12, the cascade output circuit 13, the first driving output circuit 5, and the second driving output circuit 9 are further connected to the second pull-down node PD 2.

The third leakage prevention circuit 17 is further configured to write a non-active level signal to the third leakage prevention node in response to control of the active level signal at the second pull-down node PD 2. Optionally, the third leakage preventing circuit 17 includes a twenty third transistor M23 and a twenty eighth transistor M28, wherein a control electrode of the twenty third transistor M23 is connected to the first pull-down node PD1, and a control electrode of the twenty eighth transistor M28 is connected to the second pull-down node PD 2.

The first pull-up noise reduction circuit 12 is further configured to write an inactive level signal to the first pull-up node PU1 in response to control of the active level signal at the second pull-down node PD 2. Alternatively, the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14 and a twenty-seventh transistor M27, wherein a control electrode of the fourteenth transistor M14 is connected to the first pull-down node PD1, and a control electrode of the twenty-seventh transistor M27 is connected to the second pull-down node PD 2.

The cascade output circuit 13 is further configured to write a non-active level signal to the cascade signal output terminal CR in response to control of the active level signal at the second pull-down node PD 2. Optionally, the cascade output circuit 13 includes a nineteenth transistor M19 and a twenty-fourth transistor M24, wherein a control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD1 and a control electrode of the twenty-fourth transistor M24 is connected to the second pull-down node PD 2.

The first driving output circuit 5 is further configured to write an inactive level signal to the first driving signal output terminal OUT2 in response to control of the active level signal at the second pull-down node PD 2. Alternatively, the first driving output circuit 5 includes a seventeenth transistor M17 and a twenty-sixth transistor M26, wherein a control electrode of the seventeenth transistor M17 is connected to the first pull-down node PD1, and a control electrode of the twenty-sixth transistor M26 is connected to the second pull-down node PD 2.

The second drive output circuit 9 is further configured to write a non-active level signal to the second drive signal output terminal OUT1 in response to control of the active level signal at the second pull-down node PD 2. Alternatively, the second driving output circuit 9 includes an eighteenth transistor M18 and a twenty-fifth transistor M25, wherein a control electrode of the eighteenth transistor M18 is connected to the first pull-down node PD1, and a control electrode of the twenty-fifth transistor M25 is connected to the second pull-down node PD 2.

In some embodiments, the sixth anti-leakage circuit 37, the second pull-up noise reduction circuit 32, the third drive output circuit 25, and the fourth drive output circuit 29 are connected to the first pull-down node PD 1.

The sixth leakage prevention circuit 37 is further configured to write a non-active level signal to the sixth leakage prevention node in response to control of the active level signal at the first pull-down node PD 1. Optionally, the sixth leakage prevention circuit 37 includes a thirteenth transistor M53 and a fifty-eighth transistor M58, wherein a control electrode of the fifty-third transistor M53 is connected to the second pull-down node PD2, and a control electrode of the fifty-eighth transistor M58 is connected to the first pull-down node PD 1.

The second pull-up noise reduction circuit 32 is further configured to write an inactive level signal to the second pull-up node PU2 in response to control of the active level signal at the first pull-down node PD 1. Optionally, the second pull-up noise reduction circuit 32 includes a forty-fourth transistor M44 and a fifty-seventh transistor M57, wherein a control electrode of the forty-fourth transistor M44 is connected to the second pull-down node PD2 and a control electrode of the fifty-seventh transistor M57 is connected to the first pull-down node PD 1.

The third drive output circuit 25 is further configured to write a non-active level signal to the third drive signal output terminal in response to control of the active level signal at the first pull-down node PD 1. Optionally, the third driving output circuit 25 includes a forty-seventh transistor M47 and a fifty-sixth transistor M56, wherein a control electrode of the forty-seventh transistor M47 is connected to the second pull-down node PD2 and a control electrode of the fifty-sixth transistor M56 is connected to the first pull-down node PD 1.

The fourth drive output circuit 29 is further configured to write a non-active level signal to the fourth drive signal output in response to control of the active level signal at the first pull-down node PD 1. Optionally, the fourth driving output circuit 29 includes a forty-eighth transistor M48 and a fifty-fifth transistor M55, wherein a gate electrode of the forty-eighth transistor M48 is connected to the second pull-down node PD2 and a gate electrode of the fifty-fifth transistor M55 is connected to the first pull-down node PD 1.

The specific operation sequence of the shift register unit shown in fig. 17 to 22 can be referred to as that shown in fig. 12 in the previous embodiment, and the specific process is not repeated here.

Based on the same inventive concept, the embodiments of the present disclosure also provide a gate driving circuit. Fig. 23 is a schematic circuit diagram of a gate driving circuit according to an embodiment of the present disclosure, fig. 24 is a timing chart of operation of the gate driving circuit shown in fig. 23, and as shown in fig. 23 and 24, the gate driving circuit includes a plurality of shift register units SRU1 to SRU3 cascaded, wherein the shift register units SRU1 to SRU3 may be the shift register units provided in any of the previous embodiments, and for a specific description of the shift register units, reference may be made to the content in the previous embodiments.

In some embodiments, when each of the shift register units SRU1 to SRU3 is used for driving the gate lines corresponding to two rows of pixel units, that is, the shift register unit includes the first driving output circuit 5, the second driving output circuit 9, the third driving output circuit 25, the fourth driving output circuit 29 and the cascade output circuit 13, each of the shift register units SRU1 to SRU3 can be regarded as two shift register circuits, for example, the shift register unit SRU1 includes the shift register circuits SR1 and SR2, the shift register unit SRU2 includes the shift register circuits SR3 and SR4, and the shift register unit SRU3 includes the shift register circuits SR5 and SR6.

As an example, if 2N rows of pixel units are disposed in the display panel, N shift register units may be disposed in the gate driving circuit, and the N shift register unit cascades may be regarded as 2N shift register circuit cascades, where the shift register circuit SR2N-1 located in the odd number of bits is configured with the sensing signal INPUT terminal INPUT2, the random signal INPUT terminal OE, and the cascade signal output terminal CR, and the shift register circuit SR2N located in the even number of bits is not configured with the sensing signal INPUT terminal INPUT2, the random signal INPUT terminal OE, and the cascade signal output terminal CR, where 1N is less than or equal to N and N is an integer.

Fig. 23 shows only an example of the case of 3 stages of shift register units SRU1 to SRU3 (6 stages of shift register circuits SR1 to SR 6), which serves only an example purpose.

In some embodiments, the sensing signal INPUT terminal INPUT2 of each stage of shift register units SRU1 to SRU3 is connected to the cascade signal output terminal CR configured by itself; the clock control signal input ends CLKA of the shift register units SRU1 to SRU3 are connected to the clock control signal line CKA, the sense reset signal input ends T-RST of the shift register units SRU1 to SRU3 are connected to the sense reset signal input line TRST ', and the random signal input ends OE of the shift register units are connected to the random signal input line OE'.

The display signal INPUT end INPUT1 of the first polar shift register unit SRU1 is connected with the frame start signal INPUT end STV, any other shift register unit except the first shift register unit SRU1 is connected with the cascade signal output end CR of the shift register unit of the previous stage; the sensing reset signal input ends T-RST of the shifting register units of each stage are connected with a sensing reset signal line; the display reset signal input end RST of the shift register unit positioned at the N-th stage and the display reset signal input end RST of the shift register unit positioned at the N-1 th stage are connected with the frame end reset signal line, and the display reset signal input ends RST of any one shift register unit except the shift register units positioned at the N-th stage and the N-1 th stage are connected with the cascade signal output ends CR of the two stages of shift registers.

Of course, in practical application, the specific cascade mode can be adjusted according to actual needs.

In some embodiments, 6 first driving clock signal lines CKE1 to CKE6 and 6 second driving clock signal lines CKD1 to CKD6 are configured for the gate driving circuit;

The first driving clock signal input terminal CLKE located at the 3i+1-th stage shift register unit sru3i+1 is connected to the first driving clock signal line CKE1, the second driving clock signal input terminal CLKD located at the 3i+1-th stage shift register unit sru3i+1 is connected to the second driving clock signal line CKD1, the third driving clock signal input terminal CLKE 'located at the 3i+1-th stage shift register unit sru3i+1 is connected to the second driving clock signal line CKE2, the fourth driving clock signal input terminal CLKD' located at the 3i+1-th stage shift register unit sru3i+1 is connected to the second driving clock signal line CKD2, and the cascade clock signal input terminal (not shown in fig. 23) located at the 3i+1-th stage shift register unit sru3i+1 is connected to the second driving clock signal line CKD 2.

The first driving clock signal input terminal CLKE located at the 3i+2-th stage shift register unit sru3i+2 is connected to the first driving clock signal line CKE3, the second driving clock signal input terminal CLKD located at the 3i+2-th stage shift register unit sru3i+2 is connected to the second driving clock signal line CKD3, the third driving clock signal input terminal CLKE 'located at the 3i+2-th stage shift register unit sru3i+2 is connected to the second driving clock signal line CKE4, the fourth driving clock signal input terminal CLKD' located at the 3i+2-th stage shift register unit sru3i+2 is connected to the second driving clock signal line CKD4, and the cascade clock signal input terminal (not shown in fig. 23) located at the 3i+2-th stage shift register unit sru3i+2 is connected to the second driving clock signal line CKD 4.

The first driving clock signal input terminal CLKE located at the 3i+3 stage shift register unit sru3i+3 is connected to the first driving clock signal line CKE5, the second driving clock signal input terminal CLKD located at the 3i+3 stage shift register unit sru3i+3 is connected to the second driving clock signal line CKD5, the third driving clock signal input terminal CLKE 'located at the 3i+3 stage shift register unit sru3i+3 is connected to the second driving clock signal line CKE6, the fourth driving clock signal input terminal CLKD' located at the 3i+3 stage shift register unit sru3i+3 is connected to the second driving clock signal line CKD6, and the cascade clock signal input terminal (not shown in fig. 23) located at the 3i+3 stage shift register unit sru3i+3 is connected to the second driving clock signal line CKD 6. Wherein i is a positive integer and 3i+3.ltoreq.N.

Based on the same inventive concept, the embodiments of the present disclosure further provide a display panel, where the display panel includes the gate driving circuit provided in the previous embodiments, and for a specific description of the gate driving circuit, reference may be made to the content in the previous embodiments, which is not repeated herein.

In some embodiments, the gate driving circuit is prepared on the array substrate of the display panel by using a GOA method.

Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, where the display device includes the display panel provided in the previous embodiments, and for a specific description of the display panel, reference may be made to the content in the previous embodiments, which is not repeated herein.

The display device provided by the embodiment of the disclosure may be: any product or component with display function such as a liquid crystal display, a wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the present disclosure.

Based on the same inventive concept, the embodiments of the present disclosure further provide a gate driving method, which is based on the shift register unit provided in the previous embodiments, and the specific description of the shift register unit may refer to the content in the previous embodiments, which is not repeated herein. Fig. 25 is a method flowchart of a gate driving method according to an embodiment of the disclosure, as shown in fig. 25, where the gate driving method includes:

In step S101, the sensing control circuit responds to the control of the active level signal provided by the random signal input terminal to write the signal provided by the sensing signal input terminal into the sensing control node.

In step S102, the sensing pre-charge preparing circuit outputs the signal provided by the clock control signal input terminal to the input enhancing node in response to the control of the effective level signal at the sensing control node, and the auxiliary input circuit outputs the effective level signal provided by the first power supply terminal to the input enhancing node.

In step S103, the first sensing precharge circuit writes the voltage at the input enhancement node to the first pull-up node in response to the control of the active level signal provided by the clock control signal input terminal.

In step S104, the first driving output circuit writes the signal provided by the first driving clock signal input terminal into the first driving signal output terminal in response to the control of the active level signal at the first pull-up node.

For the specific description of the above steps S101 to S104, reference may be made to the content in the previous embodiments, and the description is omitted here.

In the embodiment of the disclosure, when the first sensing precharge circuit writes the voltage at the input enhancement node to the first pull-up node, the auxiliary input circuit also writes the active level signal provided by the first power supply terminal to the input enhancement node, and at this time, for the input enhancement node, the sensing precharge preparation circuit charges the input enhancement node to write the active level signal, and the auxiliary input circuit charges the input enhancement node to write the active level signal, so that the voltage at the input enhancement node is charged to the active level state in a very short time, and correspondingly, the voltage at the first pull-up node is also charged to the active level state in a very short time. That is, when the clock control signal input end provides the effective level signal, the effective level signal of the sensing cascade can be represented to be written into the first pull-up node through the input enhancing node and the first sensing pre-charging circuit instantly, so that the input capability of the sensing cascade signal of the shift register unit can be effectively improved.

It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims

1. A shift register unit, comprising:

2. The shift register unit according to claim 1, wherein the auxiliary input circuit comprises: a fourth transistor;

3. The shift register unit of claim 2, wherein the auxiliary input circuit further comprises: a sixth transistor located between the fourth transistor and the input enhancement node, a second diode of the fourth transistor being connected to the input enhancement node through the sixth transistor;

4. The shift register cell of claim 1, wherein the sense pre-charge preparation circuit comprises: a second transistor;

5. The shift register cell of claim 4, wherein the sense pre-charge preparation circuit further comprises: an eighth transistor located between the second transistor and the input enhancement node, a second pole of the second transistor being connected to the input enhancement node through the eighth transistor;

6. The shift register unit of claim 1, further comprising:

7. The shift register cell of claim 6, wherein the first display precharge circuit comprises: a ninth transistor;

the control electrode of the ninth transistor is connected with the display signal input end, the first electrode of the ninth transistor is connected with the third power supply end, and the second electrode of the ninth transistor is connected with the pull-up node.

8. The shift register cell of claim 6, wherein the first display precharge circuit comprises: a ninth transistor and an eleventh transistor;

9. The shift register unit of claim 6, further comprising:

10. The shift register unit of claim 9, further comprising: a first voltage control circuit;

11. The shift register cell of claim 10, wherein the active level supply terminal is the third power supply terminal;

the active level supply terminal is the active level output node.

12. The shift register unit according to any one of claims 6 to 11, further comprising:

13. The shift register cell of claim 12, wherein the second display precharge circuit comprises: a thirty-ninth transistor;

14. The shift register unit of claim 12, further comprising:

15. The shift register cell of claim 14, wherein the inactive level supply terminal is the second power supply terminal;

the shift register unit further includes: a second voltage control circuit;

16. A shift register unit as claimed in claim 14, characterized in that the shift register unit is the shift register unit of claim 10, and the inactive level supply terminal is the first voltage control node.

17. A gate driving circuit, comprising: a plurality of shift register units in cascade, said shift register units employing any of the shift register units of the preceding claims 1 to 16.

18. A display panel, comprising: a gate drive circuit as claimed in claim 17.

19. A display device, comprising: a display panel as claimed in claim 18.

20. A gate driving method, characterized in that based on the shift register unit according to any one of claims 1 to 16, the gate driving method comprises: