CN114580340B - Chip power decoupling simulation optimization method and device - Google Patents
Chip power decoupling simulation optimization method and device Download PDFInfo
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Abstract
The application relates to a chip power decoupling simulation optimization method and device. The application can ensure that the chip power supply meets the quality standard, can meet the preset resource range while improving the chip system design success rate, saves the resource consumption cost, reduces the trial-and-error cost and improves the chip design efficiency. The method comprises the following steps: acquiring an initial printed circuit board design diagram of a chip to be designed, and acquiring initial circuit parameters based on the initial printed circuit board design diagram; inputting initial circuit parameters and capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters of the power supply integrity simulation model meet preset requirement standards; calculating a resource consumption component based on the adjusted capacitor device parameters, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range; and outputting the adjusted resource consumption component.
Description
Technical Field
The application relates to the technical field of semiconductor chips, in particular to a chip power decoupling simulation optimization method and device.
Background
The processor chip is widely applied to various scenes such as computers, mobile phones, deep learning, scientific computing and the like, in the design process of hardware circuits such as a CPU (central processing unit, a central processing unit), a GPU (graphics processing unit, a graphic processor) and the like, PI (Power integrity) is very important, power integrity refers to the quality of a Power supply, in the practical application process, a Power supply module in the chip cannot achieve the effect of an ideal Power supply due to the influence of wiring or load requirements of a PCB (printed circuit board, a printed circuit board), and the voltage or current waveform provided by the practical Power supply cannot be stabilized and flattened like the ideal Power supply, but has more fluctuation and noise, so that the performance of the whole chip is influenced, such as a screen display problem caused by unstable work of a display card hardware circuit.
In order to ensure the integrity of the power supply, a power supply decoupling method is mostly adopted in the current chip design, and the power supply decoupling refers to designing a proper capacitor for a power supply pin so as to filter power supply noise and ensure that the power supply can meet the performance requirement of a system. The existing power decoupling method is mostly a stacking group or an experience group, wherein the stacking group refers to adding the types and the quantity of the capacitors at each pin of the power chip, and the more the better. Experience refers to designing a power decoupling circuit with experience accumulated in the past by engineers.
However, as the current chip circuits develop toward the large-scale integrated circuits, the density of the single boards is higher and higher, the requirement on the power integrity is higher and higher, and the stacking group is easy to increase a stack of unnecessary capacitors, occupy valuable PCB space, and each experience group needs to actually measure the processor chip, so that at least one to two plate making iteration cycles are needed, and the trial-and-error cost is increased. Therefore, the existing power decoupling method consumes more resource cost, which is not beneficial to improving the chip design efficiency.
Disclosure of Invention
Based on the above, it is necessary to provide a method and a device for optimizing the decoupling simulation of the chip power supply.
In a first aspect, the application provides a chip power decoupling simulation optimization method. The method comprises the following steps:
acquiring an initial printed circuit board design diagram of a chip to be designed, and acquiring initial circuit parameters based on the initial printed circuit board design diagram;
inputting the initial circuit parameters and the capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters output by the power supply integrity simulation model meet preset requirement standards;
Calculating a resource consumption component based on the adjusted capacitor device parameter, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and outputting the adjusted resource consumption component.
In one embodiment, the inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total amount of resource consumption output by the preset resource optimization model meets a preset resource range includes:
inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption;
and adjusting each resource consumption component until the total resource consumption meets the preset range.
In one embodiment, the resource consumption component includes a capacitance quantity and a capacitance average resource consumption quantity; the step of inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption, wherein the method comprises the following steps:
Inputting the capacitance quantity and the capacitance average resource consumption into the preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
In one embodiment, the resource consumption component further comprises a capacitance species; the step of inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption, wherein the method comprises the following steps:
inputting the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a second product of the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the second product as the total resource consumption.
In one embodiment, the method further comprises:
calculating the occupied area of the total capacitance based on the capacitance quantity and the capacitance type;
and inputting the occupied area of the total capacitor, the capacitor quantity, the average capacitor resource consumption and the capacitor type into the preset resource optimization model, calculating a third product of the occupied area of the total capacitor, the capacitor quantity, the average capacitor resource consumption and the capacitor type through the preset resource optimization model, and taking the third product as the total resource consumption.
In one embodiment, the resource consumption component further comprises a time resource; the step of inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption, wherein the method comprises the following steps:
and inputting the time resource, the total capacitance occupied area, the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a fourth product of the time resource, the total capacitance occupied area, the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the fourth product as the total resource consumption.
In one embodiment, the resource consumption component includes a capacitance number, a capacitance type; the method further comprises the steps of:
and inputting the capacitance quantity and the capacitance type into the preset resource optimization model, calculating the occupied area of the total capacitance through the preset resource optimization model, and taking the occupied area of the total capacitance as the total resource consumption.
In one embodiment, the method further comprises:
inputting the adjusted resource consumption component into the power supply integrity simulation model, and outputting a secondary simulation performance parameter;
and if the secondary simulation performance parameter meets the requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result.
In one embodiment, the method further comprises:
if the secondary simulation performance parameter does not meet the requirement standard, continuing to adjust the capacitor device parameter until the capacitor device parameter after final adjustment can enable the capacitor simulation performance parameter to meet the requirement standard, and enabling the total resource consumption to meet the preset resource range by the corresponding resource consumption component;
and taking the resource consumption component corresponding to the final adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
In a second aspect, the application further provides a chip power decoupling simulation optimizing device. The device comprises:
the circuit board design diagram acquisition module is used for acquiring an initial printed circuit board design diagram of a chip to be designed and acquiring initial circuit parameters based on the initial printed circuit board design diagram;
The power supply integrity simulation module is used for inputting the initial circuit parameters and the capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters output by the power supply integrity simulation model meet preset requirement standards;
the resource consumption component adjusting module is used for calculating a resource consumption component based on the adjusted capacitor device parameters, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and the resource consumption component output module is used for outputting the adjusted resource consumption component.
According to the chip power decoupling simulation optimization method and device, the initial printed circuit board design diagram of the chip to be designed is obtained, and initial circuit parameters are collected based on the initial printed circuit board design diagram; inputting initial circuit parameters and capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters of the power supply integrity simulation model meet preset requirement standards; calculating a resource consumption component based on the adjusted capacitor device parameters, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range; and outputting the adjusted resource consumption component. According to the decoupling capacitor device parameter optimization method, the decoupling capacitor device parameters meeting the quality standard are designed through the power supply integrity simulation model, and then the resource optimization model adjusts and optimizes the decoupling capacitor device parameters, so that the quantity and the type of the optimized decoupling capacitors can meet the preset resource range.
Drawings
FIG. 1 is a flow diagram of a method for optimizing the decoupling simulation of a chip power supply in one embodiment;
FIG. 2 is a graph of the operating characteristics of a single capacitor in one embodiment;
FIG. 3 is a graph showing the operating characteristics of a plurality of capacitors in one embodiment;
FIG. 4 is a flow chart of a method for optimizing the decoupling simulation of the chip power supply according to another embodiment;
FIG. 5 is a block diagram of a chip power decoupling simulation optimizing apparatus in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The chip power decoupling simulation optimization method provided by the embodiment of the application can be applied to terminal equipment or a server. The terminal device may be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, internet of things devices and portable wearable devices, and the internet of things devices may be smart speakers, smart televisions, smart air conditioners, smart vehicle devices and the like. The portable wearable device may be a smart watch, smart bracelet, headset, or the like. The server may be implemented as a stand-alone server or as a server cluster composed of a plurality of servers.
In one embodiment, as shown in fig. 1, a method for optimizing the decoupling simulation of a chip power supply is provided, and the method is applied to the terminal for illustration, and includes the following steps:
step S101, an initial printed circuit board design diagram of a chip to be designed is obtained, and initial circuit parameters are collected based on the initial printed circuit board design diagram;
the chip is a generic term of semiconductor element products, and may be, for example, a CPU (central processing unit ), a GPU (graphics processing unit, graphics processor) or a microchip (microchip) of an automatic control system in a computer device, generally, the chip is composed of an integrated circuit and an O-S-D device (optoelectronics, sensor, discrete device) (i.e., an Optoelectronic device, a Sensor, and a Discrete device), where the integrated circuit occupies about 80% and the integrated circuit is mainly composed of transistors. The chip type is not limited herein. The chip to be designed refers to a target chip to be designed, and the target chip can be of different types according to different practical application scenes, such as a chip in a vehicle-mounted system or a central processor in computer equipment. In the chip design process, the design of an initial PCB (printed circuit board ) is finished according to the system principle, and the initial PCB is the initial printed circuit board design diagram. The initial circuit parameters refer to the working voltage, current, load size, load frequency, impedance generated by wiring in the initial PCB design diagram, parasitic inductance, and the like of the chip to be designed.
Specifically, after the chip is initially designed to form a system schematic diagram and an initial PCB design diagram, the computer device may count circuit components used by the chip based on the initial PCB design diagram and form a Bill of materials (BOM), and extract initial circuit parameters affecting a power layer (a power supply part may be referred to as a power supply layer or a power supply module because the PCB is designed layer by layer) in the chip to be designed according to the system schematic diagram, the initial PCB design diagram and the Bill of materials (BOM), where the power supply module may be more than one and may be individually analyzed for each power supply module, and this is described only by a decoupling simulation optimization process of one power supply module, and the like.
Step S102, inputting the initial circuit parameters and the capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters output by the power supply integrity simulation model meet the preset requirement standard.
The Power Integrity (PI) simulation is to design a proper power decoupling circuit by simulating and analyzing various parameters of a chip in a circuit design stage, so that a power distribution system can provide stable and reliable electric energy, and the system performance is ensured. The power integrity simulation model may be a software model that is set up in advance. The capacitive device parameters include the self-resonant frequency and impedance of the capacitor, etc. The capacitor device parameters refer to the capacitance value, packaging properties, etc. of the capacitor.
The principle of power decoupling will be described. As is well known, a power module (or power distribution module) is a circuit that delivers power from a power source terminal to a load, and current flows from the power source terminal to the load terminal through the power distribution module, and then flows back to the power source terminal through the power distribution module. In an ideal model, wires in the circuit are all impedance-free, parasitic inductance-free and parasitic capacitance-free, an ideal power supply can stably maintain required voltage, and can provide instant response current when load demand current suddenly increases, but in practical application, the effect that the power supply cannot achieve the ideal power supply is caused because the wires are also provided with impedance and load demand fluctuates at any time, and power supply output waveforms have more noise. In order to keep the power supply stable, it is found that the power supply pin is connected with enough capacitor to perform filtering function and filter redundant noise, so that the power supply tends to be perfect, that is, the influence of wires or loads on the power supply is removed (also called decoupling function), the capacitor is called decoupling capacitor, and the basic requirement of decoupling of the power supply module is that the impedance of the equivalent power supply is small enough.
For a single capacitor, the operating characteristic curve is shown in fig. 2, the horizontal axis represents the operating frequency f, the vertical axis represents the impedance z of the capacitor, and each capacitor has a self-resonance point (also called resonance point), at which the impedance of the capacitor is minimum, so that the capacitor can be added in the power module to reduce the impedance, and realize the decoupling (filtering) effect.
However, since there is only one self-resonance point of a single capacitor, which is an inherent property of the capacitor, the self-resonance point cannot be changed at will, which is determined by the capacitance value, the material and the packaging type of the capacitor, and the power module cannot be adapted to a wide range of operating frequencies by using the single capacitor, so that a plurality of capacitors are required to be used in combination. The current common practice is to use a plurality of capacitors with different capacitance values to form a low-impedance frequency band, as shown in fig. 3, so that the power supply can work in a wider low-impedance frequency band range, and the stable operation of the system is ensured.
Specifically, in step S102, initial circuit parameters such as load size, load frequency, and the like, and capacitor device parameters such as capacitance, and the like, are input into a power integrity simulation model to obtain power simulation performance parameters such as impedance, parasitic inductance, and the like, and the final power simulation performance parameters are obtained by multiple simulations of adjusting the initial circuit parameters to the capacitor device parameters such as adding capacitor types, adding capacitor numbers, and the like, and the final power simulation performance parameters meet preset requirement standards, which are not unique and can be flexibly set according to the chip application scenario and the actual requirements of users. At this time, the power integrity simulation is completed, and the chip power module can stably work under the function of the adjusted capacitor device parameters.
Step S103, calculating a resource consumption component based on the adjusted capacitor device parameters, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets the preset resource range.
The resource consumption component refers to resources consumed in the power decoupling process, such as the number of capacitors, the type of capacitors, the time spent, the PCB area, and other cost factors. The total resource consumption is the total resource consumption result consumed in the whole chip power supply optimization process under the comprehensive influence of the resource consumption components, and practice shows that the total result is not a simple superposition of the components. The resource optimization model refers to an optimization method that enables the above-described overall result of resource consumption to be reduced. The resource optimization model may be the total product of the individual resource consumption components.
Specifically, the resource consumption components are calculated according to the adjusted capacitor device parameters, for example, the total number of capacitors, the types of capacitors, the total area of the used capacitors, the time consumption and other resource consumption components are calculated in the optimization process, the components are input into the preset resource optimization model, the size of each component is continuously adjusted until the total product (namely the total resource consumption) of the final components meets the preset resource range, and the preset resource range refers to the preset total cost of input resources in advance and can be flexibly set according to actual requirements.
Furthermore, the adjustment of the resource consumption component is not an arbitrary adjustment, and it is also necessary to take into account that the adjusted component can enable the power integrity to meet the preset requirement standard, and the adjustment can take time, use the capacitor to occupy the total area of the PCB board, and the like.
Step S104, outputting the adjusted resource consumption component.
Specifically, the adjusted resource consumption components are output, and the next processing is performed according to the capacitance types and the capacitance amounts corresponding to the components, for example, purchase and board production is started.
According to the embodiment, the decoupling capacitor device parameters meeting the quality standard are designed through the power supply integrity simulation model, and then the decoupling capacitor device parameters are adjusted and optimized through the resource optimization model, so that the quantity and the type of the optimized decoupling capacitors can meet the preset resource range.
In an embodiment, the step S103 includes: inputting the resource consumption components into a preset resource optimization model, calculating the total product of each resource consumption component through the preset resource optimization model, and taking the product as the total resource consumption; and adjusting each resource consumption component until the total resource consumption meets a preset range.
We have found through calculation that the total amount of resource consumption is directly related to the total product of the individual resource consumption components, so that the total product of the individual resource consumption components can be taken as the total amount of resource consumption.
Specifically, the resource consumption components such as the total number of used capacitances and the type of used capacitances are input into the above-described resource optimization model, and the size of the model input components is adjusted until the total product of the resource consumption components satisfies a preset resource range such as a [10, 25] interval range.
According to the embodiment, the relation between the total consumption of the resources and each component is obtained through empirical analysis, so that the resource optimization model is constructed to realize automatic optimization of the resource investment, and the efficiency of resource optimization is improved.
In one embodiment, the resource consumption component includes a capacitance amount and a capacitance average resource consumption amount, and the step S103 includes: and inputting the capacitance quantity and the capacitance average resource consumption into a preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
Specifically, the calculation manner of the total amount of resource consumption can be set as shown in the following formula (1):
Decoupling Cap Total Cost＝Quantity×Mean Vlue (1)
Wherein, quality represents the capacitance Quantity; mean Vlue represents the average consumed resource (e.g., may be average unit price or average manufacturing time, etc.) for using capacitance; decoupling Cap Total Cost the total amount of resource consumption, i.e. the first product of the number of capacitances and the average amount of capacitance resource consumption.
According to the embodiment, the correlation between the total consumption of the resources and the capacitance quantity and the average consumption of the capacitance is obtained through empirical analysis, so that the construction of a proper resource optimization model is facilitated, the automatic optimization of the resource investment is realized, and the efficiency of resource optimization is improved.
In one embodiment, the resource consumption component further includes a capacitance type, and the step S103 includes: the capacitance quantity, the capacitance average resource consumption and the capacitance type are input into a preset resource optimization model, a second product of the capacitance quantity, the capacitance average resource consumption and the capacitance type is calculated through the preset resource optimization model, and the second product is used as the total resource consumption.
Specifically, the calculation manner of the total amount of resource consumption can be set as shown in the following formula (2):
Decoupling Cap Total Cost＝Quantity×Mean Vlue×Kinds (2)
wherein, quality represents the capacitance Quantity; mean Vlue represents the average consumed resource (e.g., may be average unit price or average manufacturing time, etc.) for using capacitance; kinds represents the capacitance type; decoupling Cap Total Cost the total amount of resource consumption, i.e. the second product of the number of capacitances, the average amount of resource consumption of the capacitance and the kind of capacitance.
According to the embodiment, the correlation between the total consumption of the resources and the quantity, the type and the average consumption of the capacitors is obtained through empirical analysis, so that the construction of a proper resource optimization model is facilitated, the automatic optimization of the resource investment is realized, and the efficiency of resource optimization is improved.
In an embodiment, the step S103 includes: calculating the occupied area of the total capacitance based on the number of the capacitances and the types of the capacitances; the occupied area of the total capacitor, the number of the capacitors, the average capacitance resource consumption and the capacitance type are input into a preset resource optimization model, a third product of the occupied area of the total capacitor, the number of the capacitors, the average capacitance consumption and the capacitance type is calculated through the preset resource optimization model, and the third product is used as the total resource consumption.
Specifically, since the capacitors have different bottom areas according to different types, the bottom Area of each capacitor can be queried based on the types of the capacitors, and the total capacitance occupied Area PCB Area is calculated according to the number of the capacitors and the types of the capacitors; on the basis of the above formula (2), the calculation manner of the total amount of resource consumption may be set as shown in the following formula (3):
Decoupling Cap Total Cost＝Quantity×Mean Vlue×Kinds×PCB Area (3)
wherein, quality represents the capacitance Quantity; mean Vlue represents the average consumed resource (e.g., may be average unit price or average manufacturing time, etc.) for using capacitance; kinds represents the capacitance type; PCB Area represents the total capacitance occupied; decoupling Cap Total Cost the total amount of resource consumption, i.e. the third product of the number of capacitances, the average amount of resource consumption of the capacitances, the type of capacitance, the total capacitance occupied.
According to the embodiment, the correlation between the total consumption of the resources and the capacitance quantity, the average consumption of the resources of the capacitors, the types of the capacitors and the occupied area of the total capacitors is obtained through empirical analysis, so that the construction of a proper resource optimization model is facilitated, the automatic optimization of the resource investment is realized, and the efficiency of resource optimization is improved.
In one embodiment, the resource consumption component further includes a time resource, and the step S103 includes: the time resource, the occupied area of the total capacitor, the number of capacitors, the average capacitance resource consumption and the type of capacitors are input into a preset resource optimization model, a fourth product of the time resource, the occupied area of the total capacitor, the number of capacitors, the average capacitance consumption and the type of capacitors is calculated through the preset resource optimization model, and the fourth product is used as the total resource consumption.
Specifically, we sum up the total amount of resource consumption calculated as shown in the following equation (4):
Decoupling Cap Total Cost＝Quantity×Kinds×Mean Vlue×PCB Area×Time (4)
where quality represents the total number of capacitors used; kit: the type of the capacitor used is shown; mean Vlue represents the average consumed resource (e.g., average unit price) using capacitance; PCB Area represents the total Area of the PCB using capacitance; time represents Time spent; decoupling Cap Total Cost the total amount of resource consumption, i.e. the fourth product of the individual components.
According to the embodiment, the correlation between the total consumption of the resources and the quantity of the capacitors, the average consumption of the resources of the capacitors, the types of the capacitors, the occupied area of the total capacitors and the time spent is obtained through empirical analysis, so that the construction of a proper resource optimization model is facilitated, the automatic optimization of the input of the resources is realized, and the efficiency of resource optimization is improved.
In one embodiment, the resource consumption component includes a capacitance number and a capacitance type; the method further comprises the steps of: the method comprises the steps of inputting the quantity and the type of the capacitors into a preset resource optimization model, calculating the occupied area of the total capacitors through the preset resource optimization model, and taking the occupied area of the total capacitors as the total consumption of resources.
Specifically, the resource optimization model can obtain a bottom Area corresponding to the type according to the input capacitance type query, calculate a total capacitance occupied Area PCB Area according to the number of each capacitance, and take the total capacitance occupied Area PCB Area as the total resource consumption.
According to the embodiment, the correlation of the occupied area of the total capacitor is calculated, so that the type and the number of the capacitors can be adjusted later, the occupied area of the total capacitor is introduced, and precious PCB area resources are saved.
In an embodiment, the method further includes: inputting the adjusted resource consumption component into a power supply integrity simulation model, and outputting a secondary simulation performance parameter; and if the secondary simulation performance parameter meets the requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result.
Specifically, as shown in fig. 4, fig. 4 shows a further flow diagram of a chip power decoupling simulation optimization method, including:
first, the system is designed preliminarily. The design of a system schematic diagram and a PCB is mainly completed, and a material table (BOM) is listed for calculation of subsequent steps;
second, power integrity simulation (PI). The designed PCB carries out power integrity simulation, and decoupling is carried out through redundant capacitors, so that good simulation performance is ensured.
And thirdly, substituting any one of the formulas (1) - (4) to calculate and optimizing. And if the total resource consumption is within the preset resource range, carrying out the next step of PCB board throwing and piece loading production.
Further, if the total resource consumption is too high, after parameters such as the number of capacitors, the capacitance value of the capacitors and the like are required to be modified, performing secondary PI simulation, and taking the adjusted resource consumption component as an optimal decoupling capacitor combination result if the secondary simulation performance parameter of the simulation output meets the preset requirement standard.
And fourthly, throwing/producing the PCB.
And fifthly, mass production of the PCB.
According to the embodiment, the optimized capacitor device parameters are subjected to secondary PI simulation, so that the optimized device parameters can meet the power supply integrity requirement and save the resource investment.
In one embodiment, as shown in fig. 4, the method further includes: if the secondary simulation performance parameter does not meet the requirement standard, continuing to adjust the capacitor device parameter until the capacitor device parameter after final adjustment can enable the capacitor simulation performance parameter to meet the preset requirement standard, and enabling the total resource consumption to meet the preset resource range by the corresponding resource consumption component; and taking the resource consumption component corresponding to the finally adjusted capacitor device parameter as the optimal decoupling capacitor combination result.
According to the embodiment, PI simulation is repeatedly carried out on the optimized capacitor device parameters, so that the optimized device parameters can be further ensured to meet the power supply integrity requirement, and the resource investment can be further ensured.
The technical effects brought by the method are clarified by a specific application, and the method is applied to the power integrity optimization process of the vehicle-mounted chip:
firstly, comparing an optimized scheme and an original scheme of a CORE power supply VDD_CORE of a CPU, and accounting BOM (bill of materials) cost and total cost by using a formula (4). Then, the optimized scheme and the original scheme of the memory cell vdd_mem are compared, and the BOM cost and the total cost are calculated by using the formula (4).
The optimized scheme and the original scheme of the CORE power supply VDD_CORE of the CPU are compared with the following table 1
TABLE 1 VDD_CORE optimization scheme vs. original scheme BOM
It can be seen from table 1 that, although the number of capacitors used in the scheme is the same before and after optimization, the same decoupling filtering effect can be achieved by changing materials due to different unit prices of different capacitors, and meanwhile, the types are reduced, so that the BOM cost is reduced, and the piece feeding cost is also reduced indirectly.
Table 2 below lists the relative BOM costs and the relative total costs before and after VDD_CORE optimization.
TABLE 2 cost comparison of VDD_CORE optimization scheme to original scheme
*1, annotating: the relative BOM cost is obtained by making the purchase price of all the capacitor costs uniform with the price of Murata GRM 100nF capacitor as 1. In the calculation of this scheme, the relative BOM cost of 100nF is 1.0, 330nF is 4.6,4.7 μF is 5.2, and 10 μF is 6.1.
*2, annotating: the relative total cost refers to the fact that the total relative BOM cost is added by considering the formula (4) and simultaneously considering the factors of the quantity of the capacitors, the single cost, the type, the occupied area, the time and 5.
As can be seen from table 2, the optimized scheme, only one term vdd_core, can compress the corresponding cost to-9.7%.
The optimization scheme and the original scheme of the power supply vdd_mem for the memory are compared with the following table 3:
| scheme for the production of a semiconductor device | 100nF capacitor | 4.7 mu F capacitor | 10 mu F capacitor |
| Original scheme | 23 | 5 | 0 |
| Optimization scheme | 11(-12) | 0(-5) | 4(+4) |
Table 3 vdd_mem optimization scheme vs. original scheme
It can be seen from the table that the number of capacitors used by the scheme is reduced by 13 before and after the vdd_mem is optimized, the types are reduced from 3 types to 2 types, the optimized scheme achieves better effects through simulation and actual measurement, and meanwhile, the optimization brings about obvious improvement to the preparation, purchase and design of a PCB. The BOM cost is reduced.
Table 4 below lists the relative BOM costs and the relative total costs before and after VDD_CORE optimization.
| Scheme for the production of a semiconductor device | Relative BOM cost *1 | Relative total cost *2 |
| Original scheme | 49.0 | 49.0 |
| Optimization scheme | 35.4(-27.8％) | 29.1(-40.6％) |
Table 4 vdd mem optimization scheme vs. original scheme
*1, annotating: the relative BOM cost is obtained by making the purchase price of all the capacitor costs uniform with the price of Murata GRM 100nF capacitor as 1. In the calculation of this scheme, the relative BOM cost of 100nF is 1.0, 330nF is 4.6,4.7 μF is 5.2, and 10 μF is 6.1.
*2, annotating: the relative total cost refers to the fact that the total relative BOM cost is added by considering the formula (4) and simultaneously considering the factors of the quantity of the capacitors, the single cost, the type, the occupied area, the time and 5.
As can be seen from table 4, the optimized scheme, only one term vdd_mem, can compress the corresponding total cost to-40.6%.
Therefore, the capacitance optimization scheme of the CPU core power supply and the memory power supply is integrated, and the compression of the total cost after optimization can reach more than 25%. Experiments show that the scheme can achieve good effects, not only can compress development cost, but also can improve system development flow, quicken development progress and ensure overall stability.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a chip power decoupling simulation optimizing device for realizing the above-mentioned chip power decoupling simulation optimizing method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the device for optimizing the decoupling simulation of the chip power supply provided below may be referred to the limitation of the method for optimizing the decoupling simulation of the chip power supply in the above description, which is not repeated here.
In one embodiment, as shown in fig. 5, a chip power decoupling simulation optimizing apparatus 500 is provided, including: a circuit board design diagram obtaining module 501, a power integrity simulation module 502, a resource consumption component adjusting module 503 and a resource consumption component outputting module 504, wherein:
the circuit board design diagram acquisition module is used for acquiring an initial printed circuit board design diagram of a chip to be designed and acquiring initial circuit parameters based on the initial printed circuit board design diagram;
the power supply integrity simulation module is used for inputting the initial circuit parameters and the capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters output by the power supply integrity simulation model meet preset requirement standards;
The resource consumption component adjusting module is used for calculating a resource consumption component based on the adjusted capacitor device parameters, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and the resource consumption component output module is used for outputting the adjusted resource consumption component.
In an embodiment, the resource consumption component adjustment module 503 is further configured to:
inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption; and adjusting each resource consumption component until the total resource consumption meets the preset range.
In an embodiment, the resource consumption component includes a capacitance quantity and a capacitance average resource consumption quantity; the resource consumption component adjustment module 503 is further configured to:
inputting the capacitance quantity and the capacitance average resource consumption into the preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
In an embodiment, the resource consumption component further includes a capacitance type, and the resource consumption component adjustment module 503 is further configured to:
inputting the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a second product of the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the second product as the total resource consumption.
In an embodiment, the resource consumption component adjustment module 503 is further configured to:
calculating the occupied area of the total capacitance based on the capacitance quantity and the capacitance type; and inputting the occupied area of the total capacitor, the capacitor quantity, the average capacitor resource consumption and the capacitor type into the preset resource optimization model, calculating a third product of the occupied area of the total capacitor, the capacitor quantity, the average capacitor resource consumption and the capacitor type through the preset resource optimization model, and taking the third product as the total resource consumption.
In an embodiment, the resource consumption component further comprises a time resource; the resource consumption component adjustment module 503 is further configured to:
And inputting the time resource, the total capacitance occupied area, the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a fourth product of the time resource, the total capacitance occupied area, the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the fourth product as the total resource consumption.
In an embodiment, the resource consumption component includes a capacitance number, a capacitance type; the resource consumption component adjustment module 503 is further configured to:
and inputting the capacitance quantity and the capacitance type into the preset resource optimization model, calculating the occupied area of the total capacitance through the preset resource optimization model, and taking the occupied area of the total capacitance as the total resource consumption.
In one embodiment, the power integrity simulation module 502 is further configured to:
inputting the adjusted resource consumption component into the power supply integrity simulation model, and outputting a secondary simulation performance parameter; and if the secondary simulation performance parameter meets the preset requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result.
In an embodiment, the resource consumption component adjustment module 503 is further configured to:
if the secondary simulation performance parameter does not meet the preset requirement standard, continuing to adjust the capacitor device parameter until the capacitor device parameter after final adjustment can enable the capacitor simulation performance parameter to meet the preset requirement standard, and enabling the total resource consumption to meet the preset resource range by the corresponding resource consumption component; and taking the resource consumption component corresponding to the final adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
The modules in the chip power decoupling simulation optimizing device can be realized in whole or in part by software, hardware and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
The user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (8)
1. A method for optimizing the decoupling simulation of a chip power supply, the method comprising:
acquiring an initial printed circuit board design diagram of a chip to be designed, and acquiring initial circuit parameters based on the initial printed circuit board design diagram;
inputting the initial circuit parameters and the capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters output by the power supply integrity simulation model meet preset requirement standards;
Calculating a resource consumption component based on the adjusted capacitor device parameter, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
outputting the adjusted resource consumption component; inputting the adjusted resource consumption component into the power supply integrity simulation model, and outputting a secondary simulation performance parameter; if the secondary simulation performance parameter meets the preset requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result; if the secondary simulation performance parameter does not meet the preset requirement standard, continuing to adjust the capacitor device parameter until the capacitor device parameter after final adjustment can enable the capacitor simulation performance parameter to meet the preset requirement standard, and enabling the total resource consumption to meet the preset resource range by the corresponding resource consumption component; and taking the resource consumption component corresponding to the final adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
2. The method according to claim 1, wherein said inputting the resource consumption component into a preset resource optimization model, adjusting the resource consumption component until a total amount of resource consumption output by the preset resource optimization model meets a preset resource range, comprises:
Inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption;
and adjusting each resource consumption component until the total resource consumption meets the preset resource range.
3. The method of claim 2, wherein the resource consumption component comprises a capacitance quantity and a capacitance average resource consumption; the step of inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption, wherein the method comprises the following steps:
inputting the capacitance quantity and the capacitance average resource consumption into the preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
4. A method according to claim 3, wherein the resource consumption component further comprises a capacitance class; the step of inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption, wherein the method comprises the following steps:
Inputting the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a second product of the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the second product as the total resource consumption.
5. The method according to claim 4, wherein the method further comprises:
calculating the occupied area of the total capacitance based on the capacitance quantity and the capacitance type;
and inputting the occupied area of the total capacitor, the capacitor quantity, the average capacitor resource consumption and the capacitor type into the preset resource optimization model, calculating a third product of the occupied area of the total capacitor, the capacitor quantity, the average capacitor resource consumption and the capacitor type through the preset resource optimization model, and taking the third product as the total resource consumption.
6. The method of claim 5, wherein the resource consumption component further comprises a time resource; the step of inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption, wherein the method comprises the following steps:
And inputting the time resource, the total capacitance occupied area, the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a fourth product of the time resource, the total capacitance occupied area, the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the fourth product as the total resource consumption.
7. The method of claim 2, wherein the resource consumption component comprises a capacitance quantity, a capacitance type; the method further comprises the steps of:
and inputting the capacitance quantity and the capacitance type into the preset resource optimization model, calculating the occupied area of the total capacitance through the preset resource optimization model, and taking the occupied area of the total capacitance as the total resource consumption.
8. A chip power decoupling simulation optimizing device, the device comprising:
the circuit board design diagram acquisition module is used for acquiring an initial printed circuit board design diagram of a chip to be designed and acquiring initial circuit parameters based on the initial printed circuit board design diagram;
The power supply integrity simulation module is used for inputting the initial circuit parameters and the capacitor device parameters into a power supply integrity simulation model, and adjusting the capacitor device parameters until the power supply simulation performance parameters output by the power supply integrity simulation model meet preset requirement standards;
the resource consumption component adjusting module is used for calculating a resource consumption component based on the adjusted capacitor device parameters, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
the resource consumption component output module is used for outputting the adjusted resource consumption component; inputting the adjusted resource consumption component into the power supply integrity simulation model, and outputting a secondary simulation performance parameter; if the secondary simulation performance parameter meets the preset requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result; if the secondary simulation performance parameter does not meet the preset requirement standard, continuing to adjust the capacitor device parameter until the capacitor device parameter after final adjustment can enable the capacitor simulation performance parameter to meet the preset requirement standard, and enabling the total resource consumption to meet the preset resource range by the corresponding resource consumption component; and taking the resource consumption component corresponding to the final adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
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