CN109508505A - A kind of emulation mode of printed circuit board power completeness - Google Patents
A kind of emulation mode of printed circuit board power completeness Download PDFInfo
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- CN109508505A CN109508505A CN201811438102.6A CN201811438102A CN109508505A CN 109508505 A CN109508505 A CN 109508505A CN 201811438102 A CN201811438102 A CN 201811438102A CN 109508505 A CN109508505 A CN 109508505A
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- 238000004088 simulation Methods 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000001514 detection method Methods 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 7
- 235000013599 spices Nutrition 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011889 copper foil Substances 0.000 claims description 3
- 238000005868 electrolysis reaction Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 9
- 238000012795 verification Methods 0.000 abstract description 4
- 238000012360 testing method Methods 0.000 description 5
- 238000005457 optimization Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000005094 computer simulation Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Structure Of Printed Boards (AREA)
Abstract
This application discloses a kind of emulation mode of printed circuit board power completeness, this method specifically includes that selection simulation model；In selected simulation model, the project of power completeness simulation analysis is determined；According to the project that power completeness simulation is analyzed, simulation model is established；The frequency range of printed circuit board is determined in simulation model；Detect power-supply system impedance；According to frequency range and power-supply system impedance, according to the target that power completeness simulation is analyzed, power completeness simulation analysis is carried out to printed circuit board.By the method in the application, design cycle of printed circuit board can be effectively shortened, improve the Power Integrity verification efficiency to printed circuit board.
Description
Technical field
This application involves power supply simulation technical fields, more particularly to a kind of emulation side of printed circuit board power completeness
Method.
Background technique
With the development of high-speed digital circuit plate technique, signal is getting faster along pace of change.Quick signal edge becomes
Change will lead to circuit signal generate ring, reflection, crosstalk, many problems of Signal Integrity such as bullet.For printed circuit board
For power supply, less than 1 nanosecond signal along variation, can make PCB (Printed Circuit Board, printed circuit board, also known as
Printed wiring board) voltage of on board supply layer and ground interlayer is all not quite similar everywhere in circuit board, to influence IC chip
Power supply, and then lead to the logic error of chip.Therefore, the Power Integrity for studying printed circuit board is very important asks
Topic.
Currently, the method generallyd use is to be designed to print according to user demand for the Power Integrity of verifying printed circuit board
The power supply of printed circuit board carries out repetition test to its integrality, the power supply of pcb board is then further corrected according to test result,
Power Integrity is verified again after amendment, it is final to obtain the printed circuit board for meeting Power Integrity requirement.
However, at present in the method for verifying printed circuit board power completeness, due to needing the pcb board electricity to actual design
Source carries out repetition test and amendment, too low to the Power Integrity verification efficiency of printed circuit board, leads to setting for printed circuit board
The meter period is too long, is unfavorable for the quick exploitation of new product.
Summary of the invention
This application provides a kind of emulation modes of printed circuit board power completeness, to solve in the prior art to printing
The problem that the verification efficiency of board power integrality is too low, the PCB design period is too long.
In order to solve the above-mentioned technical problem, the embodiment of the present application discloses following technical solution:
A kind of emulation mode of printed circuit board power completeness, the emulation mode include:
Choose simulation model；
In selected simulation model, the project of power completeness simulation analysis is determined；
According to the project that power completeness simulation is analyzed, simulation model is established；
The frequency range of printed circuit board is determined in simulation model；
Detect power-supply system impedance；
According to the frequency range and power-supply system impedance, according to the target that power completeness simulation is analyzed, to printing electricity
Road plate carries out power completeness simulation analysis.
Optionally, the selection simulation model, specifically:
Select Extraction Mode simulation model.
Optionally, the project of the power completeness simulation analysis includes: plate level power supply channel impedance simulation analysis, plate grade
Direct current pressure drop simulation analysis and plate grade harmonic analysis.
Optionally, the project analyzed according to power completeness simulation, establishes simulation model, comprising:
Determine power supply and GND network to be emulated；
It is generated using PEEC (Partial Element Equivalent Circuit, unit equivalent circuit) technology
RLGC (resistance/inductance/conductance/capacitor) equivalent；
Lumped parameter model is established to the cavity that via hole is formed between bus plane and bottom；
Decoupling capacitance is modeled using series connection RLC model.
Optionally, before detecting power-supply system impedance, the method also includes:
Judge whether the frequency range is satisfaction: frequency range≤1kHz；
If frequency range≤the 1kHz, directly detection power-supply system impedance；
If the frequency range > 1kHz, power-supply system impedance is detected after decoupling capacitance is placed in simulation model.
Optionally, the frequency range > 1kHz, places decoupling capacitance in simulation model, comprising:
It is that electrolysis is placed in the signal area 1kHz < frequency≤1MHz in frequency range as the frequency range > 1MHz
Capacitor；
High frequency ceramic disc capacitor is placed in the signal area that frequency range is frequency > 1MHz.
Optionally, the detection power-supply system impedance, comprising:
First port is set at any one IC chip of printed circuit board；
Utilize the power-supply system impedance of the first port computing board；
Second port is added in power input, and third port and the 4th port are set at other two IC chip；
Broad frequency sweep is carried out to printed circuit board, obtains S parameter (Scattering parameter, scattering parameter)
Collision matrix, the S parameter include: the equivalent Spice model of the resonance of circuit board, impedance, selected network and circuit；
The circuit file compatible with Spice is generated using Full-Wave Spice tool.
Optionally, the specification of the collision matrix is 4*4.
Optionally, the printed circuit board includes: bus plane, substrate and stratum, and bus plane and stratum are 1.4mil
Thick copper foil.
The technical solution that embodiments herein provides can include the following benefits:
The application provides a kind of emulation mode of printed circuit board power completeness, and this method chooses simulation model first,
Then the project of power completeness simulation analysis is determined in selected simulation model, secondly according to the project of simulation analysis,
Simulation model is established, the frequency range of printed circuit board is then determined in simulation model, detects power-supply system impedance, last root
According to frequency range and system impedance, according to the target that power completeness simulation is analyzed, Power Integrity is carried out to printed circuit board
Simulation analysis.The present embodiment by establishing Virtual prototype of the simulation model as printed circuit board, by Virtual prototype into
The method of row emulation, substitutes the design method of repetition test, can effectively shorten design cycle of printed circuit board；According to void
The design of the simulation result optimization printed circuit board of quasi- prototype, can greatly improve the Power Integrity verifying to printed circuit board
Efficiency.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The application can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the application
Example, and together with specification it is used to explain the principle of the application.
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of process signal of the emulation mode of printed circuit board power completeness provided by the embodiment of the present application
Figure.
Specific embodiment
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with the application reality
The attached drawing in example is applied, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described implementation
Example is merely a part but not all of the embodiments of the present application.Based on the embodiment in the application, this field is common
The application protection all should belong in technical staff's every other embodiment obtained without making creative work
Range.
The application in order to better understand explains in detail presently filed embodiment with reference to the accompanying drawing.
Referring to Fig. 1, Fig. 1 is a kind of emulation mode of printed circuit board power completeness provided by the embodiment of the present application
Flow diagram.As shown in Figure 1, the emulation mode in the present embodiment, mainly comprises the following processes:
S1: simulation model is chosen.
The present embodiment carries out power completeness simulation using Cadence Power SI software, in Cadence Power SI
Extraction Mode simulation model is selected in software, can easily be taken out using Extraction Mode simulation model
It is rounded the S parameter of a power-supply system, further according to S parameter computer sim- ulation impedance, to improve the accuracy and simulation efficiency of emulation.
Printed circuit board includes: bus plane, substrate and stratum in the present embodiment, and bus plane and stratum are 1.4mil thickness
Copper foil.
If Cadence Power SI software is not currently in Extraction Mode simulation model, need to cut first
Extraction Mode simulation model is shifted to, then executes subsequent simulation process.
S2: in selected simulation model, the project of power completeness simulation analysis is determined.
In the present embodiment power completeness simulation analyze project, specifically include that plate level power supply channel impedance simulation analysis,
Plate grade direct current pressure drop simulation analysis and plate grade harmonic analysis.
By plate level power supply channel impedance simulation analysis, emulation can be passed through on the basis of making full use of plane capacitance
The parameters such as the quantity, type and position for analyzing to determine shunt capacitance, then judge plate level power supply channel according to these parameters
Whether impedance meets the job requirement of device stability, is conducive to subsequent according to the parameter adjustment printing electricity for influencing device stability
The design of road plate.
By plate grade direct current pressure drop simulation analysis, it can judge whether plate level power supply channel meets the pressure drop limitation of device and want
It asks, according to simulation analysis as a result, being adjusted to the parameter for influencing plate level power supply channel pressure drop.
By plate grade harmonic analysis, harmonic analysis is got as a result, it is possible to avoid plate electrode resonance to power quality and EMI
It influences.
S3: the project analyzed according to power completeness simulation establishes simulation model.
Specifically, step S3 is comprised the following processes again:
S31: power supply and GND network to be emulated are determined.
After determining power supply to be emulated, the GND of artificial mains is waited for by Cadence Power SI software automatic identification
Network.When Cadence Power SI software can not automatic identification or automatic identification fail when, it is possible to specify to artificial mains
GND network, the electric power network that Cadence Power SI software is inputted according to user determine the GND network to artificial mains.
S32: RLGC equivalent is generated using PEEC technology.
Since printed circuit board is in planar structure, for plane, RLGC equivalent is generated using PEEC technology, it can be effective
Improve the accuracy of simulation efficiency and emulation.
S33: lumped parameter model is established to the cavity that via hole is formed between bus plane and bottom.
S34: decoupling capacitance is modeled using series connection RLC model.
When to decoupling capacitance modeling, need to comprehensively consider the dead resistance and capacitor of capacitor, and be fanned out to cabling and mistake
The dead resistance and inductance in hole.
With continued reference to Fig. 1 it is found that establishing simulation model after, execute step S4: in simulation model determine printed circuit board
Frequency range.
S7: detection power-supply system impedance.
Specifically, step S7 is comprised the following processes again:
S71: first port is set at any one IC chip of printed circuit board.
S72: the power-supply system impedance of first port computing board is utilized.
S73: second port is added in power input, and third port and the 4th end are set at other two IC chip
Mouthful.
S74: broad frequency sweep is carried out to printed circuit board, obtains the collision matrix of S parameter.
Wherein the specification of collision matrix is 4*4.
S75: the circuit file compatible with Spice is generated using Full-Wave Spice tool.
Further, further include step S5 before step S7: judge in printed circuit board information frequency range whether be
Meet: frequency range≤1kHz.
If frequency range≤1kHz, directly execution step S7: detection power-supply system impedance.
If frequency range > 1kHz, executes step S6: placing decoupling capacitance in simulation model, then execute step
S7: detection power-supply system impedance.
Specifically, step S6 includes: again
S61: being that electrolysis is placed in the signal area 1kHz < frequency≤1MHz in frequency range as frequency range > 1MHz
Capacitor.
S62: high frequency ceramic disc capacitor is placed in the signal area that frequency range is frequency > 1MHz.
By above step S5 and S6 it is found that frequency for≤1kHz, since low resistance and low is presented in bus plane and stratum
The structure on inductance characteristic, bus plane and stratum will not usually destroy impedance operator, and power supply meets the requirement of impedance operator.Work as frequency
When higher than 1kHz, the mutual inductance that electric current is through-flow, which reaches, is enough to make voltage to be more than that limit value needs to use for higher frequency range
Decoupling capacitance is connected as the Low ESR between bus plane and stratum.The present embodiment by frequency range be 1kHz < frequency≤
The biggish electrolytic capacitor of volume is placed in the signal area of 1MHz, places high frequency in the signal area that frequency range is frequency > 1MHz
Ceramic disc capacitor realizes power completeness simulation so as to reach the bandwidth of requirement.
S8: according to frequency range and power-supply system impedance, according to the target that power completeness simulation is analyzed, to printed circuit
Plate carries out power completeness simulation analysis.
The present embodiment can be used component and automatically generate port (that is: port), can also exist by hand when being emulated
Characteristic location adds port, after setting port, power-supply system impedance detection is realized by defining port, in certain frequency model
The impedance for enclosing interior power system will meet the requirement of target impedance, according to the frequency range of software emulation, to complete plate grade electricity
Source channels impedance simulation analysis, plate grade direct current pressure drop simulation analysis and plate grade harmonic analysis.
In conclusion the present embodiment is by establishing Virtual prototype of the simulation model as printed circuit board, by void
Quasi- prototype is emulated, and the design method of repetition test is substituted, by designing a printed circuit board power completeness simulation method,
It can effectively shorten design cycle of printed circuit board；According to setting for the simulation result optimization printed circuit board to Virtual prototype
Meter, can greatly improve the Power Integrity verification efficiency to printed circuit board.
The above is only the specific embodiment of the application, is made skilled artisans appreciate that or realizing this Shen
Please.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (9)
1. a kind of emulation mode of printed circuit board power completeness, which is characterized in that the emulation mode includes:
Choose simulation model；
In selected simulation model, the project of power completeness simulation analysis is determined；
According to the project that power completeness simulation is analyzed, simulation model is established；
The frequency range of printed circuit board is determined in simulation model；
Detect power-supply system impedance；
According to the frequency range and power-supply system impedance, according to the target that power completeness simulation is analyzed, to printed circuit board
Carry out power completeness simulation analysis.
2. a kind of emulation mode of printed circuit board power completeness according to claim 1, which is characterized in that the choosing
Simulation model is taken, specifically:
Select Extraction Mode simulation model.
3. a kind of emulation mode of printed circuit board power completeness according to claim 1, which is characterized in that the electricity
Source completeness simulation analysis project include: plate level power supply channel impedance simulation analysis, plate grade direct current pressure drop simulation analysis and
Plate grade harmonic analysis.
4. a kind of emulation mode of printed circuit board power completeness according to claim 1, which is characterized in that described
According to the project that power completeness simulation is analyzed, simulation model is established, comprising:
Determine power supply and GND network to be emulated；
RLGC equivalent is generated using PEEC technology；
Lumped parameter model is established to the cavity that via hole is formed between bus plane and bottom；
Decoupling capacitance is modeled using series connection RLC model.
5. a kind of emulation mode of printed circuit board power completeness according to claim 1, which is characterized in that detection electricity
Before the system impedance of source, the method also includes:
Judge whether the frequency range is satisfaction: frequency range≤1kHz；
If frequency range≤the 1kHz, directly detection power-supply system impedance；
If the frequency range > 1kHz, power-supply system impedance is detected after decoupling capacitance is placed in simulation model.
6. a kind of emulation mode of printed circuit board power completeness according to claim 5, which is characterized in that the frequency
Rate range > 1kHz, places decoupling capacitance in simulation model, comprising:
It is that electrolysis electricity is placed in the signal area 1kHz < frequency≤1MHz in frequency range as the frequency range > 1MHz
Hold；
High frequency ceramic disc capacitor is placed in the signal area that frequency range is frequency > 1MHz.
7. a kind of emulation mode of printed circuit board power completeness according to claim 1, which is characterized in that the inspection
Survey power-supply system impedance, comprising:
First port is set at any one IC chip of printed circuit board；
Utilize the power-supply system impedance of the first port computing board；
Second port is added in power input, and third port and the 4th port are set at other two IC chip；
Broad frequency sweep is carried out to printed circuit board, obtains the collision matrix of S parameter；
The circuit file compatible with Spice is generated using Full-Wave Spice tool.
8. a kind of emulation mode of printed circuit board power completeness according to claim 7, which is characterized in that described to dissipate
The specification for penetrating matrix is 4*4.
9. according to claim 1 in -8 a kind of any printed circuit board power completeness emulation mode, feature exists
In the printed circuit board includes: bus plane, substrate and stratum, and bus plane and stratum are the copper foil of 1.4mil thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811438102.6A CN109508505A (en) | 2018-11-28 | 2018-11-28 | A kind of emulation mode of printed circuit board power completeness |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811438102.6A CN109508505A (en) | 2018-11-28 | 2018-11-28 | A kind of emulation mode of printed circuit board power completeness |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110705202A (en) * | 2019-11-21 | 2020-01-17 | 无锡江南计算技术研究所 | System-level power integrity design method for packaging and printed board |
| CN112241617A (en) * | 2020-10-22 | 2021-01-19 | 浪潮商用机器有限公司 | PCB power integrity simulation method and related device |
| CN113806997A (en) * | 2020-06-15 | 2021-12-17 | 英业达科技有限公司 | Method for producing printed circuit board assembly scheme |
| CN114580340A (en) * | 2022-03-01 | 2022-06-03 | 格兰菲智能科技有限公司 | Chip power supply decoupling simulation optimization method and device |
| CN115087193A (en) * | 2022-06-30 | 2022-09-20 | 苏州浪潮智能科技有限公司 | Printed circuit board, power supply system of printed circuit board, simulation method and device |
| CN116702693A (en) * | 2023-06-12 | 2023-09-05 | 上海韬润半导体有限公司 | SMA connector model signal integrity simulation method and device |
-
2018
- 2018-11-28 CN CN201811438102.6A patent/CN109508505A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110705202A (en) * | 2019-11-21 | 2020-01-17 | 无锡江南计算技术研究所 | System-level power integrity design method for packaging and printed board |
| CN110705202B (en) * | 2019-11-21 | 2022-11-15 | 无锡江南计算技术研究所 | System-level power integrity design method for packaging and printed board |
| CN113806997A (en) * | 2020-06-15 | 2021-12-17 | 英业达科技有限公司 | Method for producing printed circuit board assembly scheme |
| CN113806997B (en) * | 2020-06-15 | 2023-11-24 | 英业达科技有限公司 | Method for producing printed circuit board assembly scheme |
| CN112241617A (en) * | 2020-10-22 | 2021-01-19 | 浪潮商用机器有限公司 | PCB power integrity simulation method and related device |
| CN114580340A (en) * | 2022-03-01 | 2022-06-03 | 格兰菲智能科技有限公司 | Chip power supply decoupling simulation optimization method and device |
| CN114580340B (en) * | 2022-03-01 | 2023-11-28 | 格兰菲智能科技有限公司 | Chip power decoupling simulation optimization method and device |
| CN115087193A (en) * | 2022-06-30 | 2022-09-20 | 苏州浪潮智能科技有限公司 | Printed circuit board, power supply system of printed circuit board, simulation method and device |
| CN116702693A (en) * | 2023-06-12 | 2023-09-05 | 上海韬润半导体有限公司 | SMA connector model signal integrity simulation method and device |
| CN116702693B (en) * | 2023-06-12 | 2024-02-09 | 上海韬润半导体有限公司 | SMA connector model signal integrity simulation method and device |
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