CN114546866A

CN114546866A - JTAG read instruction delay processing method

Info

Publication number: CN114546866A
Application number: CN202210177944.0A
Authority: CN
Inventors: 潘菲; 李泉泉; 韩琼磊; 胡孔阳; 章钰; 刘先博
Original assignee: Anhui Core Century Technology Co ltd
Current assignee: Anhui Core Century Technology Co ltd
Priority date: 2022-02-24
Filing date: 2022-02-24
Publication date: 2022-05-27

Abstract

The invention discloses a JTAG read instruction delay processing method, wherein if valid read data still does not return when a valid read instruction issued by an upper computer arrives in a new scan chain capturing state, the upper computer issues an invalid instruction until the upper computer receives the valid read data to return. The upper computer issues an invalid instruction to drive the TAP state machine to normally operate, but effective read-write operation is not generated (the chip receives the instruction and discards the instruction directly), and the significance is to realize polling of read data. And the JTAG module receives an invalid instruction sent by the upper computer, the TAP state can normally operate, each round of capturing state can detect whether valid data is returned, and the upper computer continues to send the valid instruction to avoid the problem that the read data is covered only after the valid read data is detected to be returned.

Description

JTAG read instruction delay processing method

Technical Field

The invention relates to the technical field of JTAG debugging, in particular to a JTAG read instruction delay processing method.

Background

With the rapid development of computer technology, communication technology and microelectronic technology, JTAG (joint test action Group) is widely used as an international standard test protocol (IEEE1149.1 compliant) for testing the inside of a chip. Currently, the JTAG interface is mainly used for chip electrical characteristic testing (boundary scan) and chip internal debugging (online programming).

JTAG has a state machine internal to it, called the TAP controller. And the state machine of the TAP controller changes the state through the TCK and the TMS to realize the input of data and instructions. The TAP state machine has 16 states, as shown in fig. 1, each ellipse in fig. 1 represents a state, and is labeled with a state name and an identification code, and an arrow represents all possible conversion flows of each state; the transition before the state is driven by TCK and controlled by TMS. There are four operations in the JTAG scan chain, namely suspend, Capture (Capture), Shift (Shift), and Update (Update). A read instruction of the upper computer is issued when the scan chain is in an update state, and then return data corresponding to the read instruction can be updated to the scan chain when the scan chain is in a capture state, referring to fig. 2. The network delays for reading different memory data are not completely the same, the delay time is difficult to predict in advance, in order to ensure that the read data are not covered, the existing solution reduces the TCK according to the longest delay time, and in practical application, the TCK is reduced to one thousandth or even one ten thousandth of the core clock of a chip, thereby greatly reducing the working efficiency.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a JTAG read instruction delay processing method, which can greatly improve the working efficiency.

A JTAG read instruction time delay processing method, if the valid read instruction that the upper computer issues still does not return the valid read data when the new scan chain catches the state to come, the upper computer issues the invalid instruction, until the upper computer receives the valid read data to return; an invalid instruction is an instruction with a most significant bit of 0.

Further, the JTAG module comprises a TAP state machine, an instruction register, a bypass register and a debugging scan chain,

the TAP state machine module is compatible with a standard IEEE1149.1 protocol, and completes issuing of a debugging instruction and uploading of return data according to writing and reading of a state conversion control instruction register and a debugging scan chain;

the instruction register is used for controlling the selection of the link, is written into the instruction register through the TAP state machine, and is selectively accessed into the bypass register chain or the debugging scan chain according to the register value of the instruction register;

the bypass register is used for bypassing the JTAG debugging circuit of the appointed chip and activating the JTAG debugging circuit of the chip to be debugged under the condition that a plurality of chip JTAG interfaces are connected in series;

the debugging scan chain is used for completing receiving operation of an instruction issued by the simulator and uploading operation of an instruction return value in the previous round under the condition that the debugging mode is activated.

Furthermore, the debugging scan chain is connected with 1 instruction cache unit and 1 data cache unit; the cache unit is a synchronization fifo with a depth of 32 and a width of 65.

The invention has the beneficial effects that: 1. the upper computer issues an invalid instruction to drive the TAP state machine to normally operate, but effective read-write operation is not generated (the chip receives the instruction and discards the instruction directly), and the significance is to realize polling of read data. The JTAG module receives an invalid instruction sent by the upper computer, the TAP state can normally operate, each round of capturing state can detect whether valid data is returned, and the upper computer continues to send the valid instruction to avoid the problem that the read data is covered only after the valid read data is detected to be returned; 2. the debugging scan chain is connected with 1 instruction cache unit and 1 data cache unit, and due to the existence of the cache units, the upper computer can continuously issue a batch of effective read instructions, and then always issue invalid instructions until the read data corresponding to the 16 read instructions are all returned, and then start the issuing of the next batch of effective instructions, so that the average waiting time of the returned data is further shortened, the working frequency of the online simulator is improved, and the overall working efficiency is further improved.

Drawings

FIG. 1 is a state transition diagram of a TAP state machine;

FIG. 2 is a state diagram of a conventional debug scan chain debug operation timing sequence;

FIG. 3 is a state diagram of a debugging operation timing sequence of the conventional debugging scan chain after an invalid instruction is issued by an upper computer;

FIG. 4 is a schematic diagram of the internal structure of the JTAG module;

FIG. 5 is a schematic diagram of a debug scan chain structure with cache;

FIG. 6 is a state diagram of debug scan chain debug operation timing with cache.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Example 1

As can be seen from fig. 2, the read instruction of the upper computer is issued when the scan chain is in the update state, if the return data corresponding to the read instruction is read before the next scan chain jumps to the capture state, the read instruction can be successfully updated to the scan chain, otherwise, the return data corresponding to the read instruction can be updated to the scan chain only when the next scan chain jumps to the capture state. If the upper computer issues a read instruction again before the return data corresponding to the read instruction is updated to the scan chain, and the return data corresponding to the read instruction is read out in time, the return data of the previous read instruction is covered, so that the return data of the previous read instruction is lost. At present, the solution to this technical problem is to reduce TCK according to the longest delay time, and in practical applications, TCK is reduced to one thousandth or even one ten thousandth of the clock of the chip core, thereby greatly reducing the working efficiency.

Therefore, this embodiment provides a JTAG read instruction delay processing method, where if a valid read instruction issued by an upper computer still does not return valid read data when a new scan chain capture state arrives, the upper computer issues an invalid instruction until the upper computer receives a valid read data return.

The upper computer issues an invalid instruction to drive the TAP state machine to normally operate, but effective read-write operation is not generated (the chip receives the instruction and discards the instruction directly), and the significance is to realize polling of read data. The JTAG module receives an invalid instruction issued by the upper computer, as shown in fig. 3, the TAP state may operate normally, each capture state may detect whether valid data is returned, and only after detecting that valid read data is returned, the upper computer continues to issue a valid instruction to avoid the problem that read data is covered.

The JTAG read instruction delay processing method provided by this embodiment has the following advantages: and the upper computer sends an invalid instruction, and effective read-write operation is not generated on the premise of ensuring the normal operation of the TAP state machine. The upper computer issues the invalid instruction to play a role in monitoring whether the read data is returned or not, so that the problem of read data coverage is solved by reducing the TCK, the TCK can be increased to half of the core clock of the highest chip, the effective delay of the debugging instruction is close to the network delay of the internal instruction of the chip by inserting the invalid instruction, and the working efficiency is greatly improved.

The JTAG module comprises a TAP state machine, an instruction register, a bypass register and a debugging scan chain, and the internal connection relation is shown in figure 4.

the instruction register is used for controlling the selection of the link, is written into the instruction register through the TAP state machine, and is selectively accessed into the bypass register chain or the debugging scan chain according to the register value of the instruction register.

And the bypass register is used for bypassing the JTAG debugging circuit of the appointed chip and activating the JTAG debugging circuit of the chip to be debugged under the condition that a plurality of chip JTAG interfaces are connected in series.

Example 2

When the upper computer needs to continuously issue a batch of read instructions, the scan chain needs to wait for capture states with different numbers of return data of each read instruction, and in order to further shorten the average waiting time of the return data under this condition, the debug scan chain in this embodiment is connected with 1 instruction cache unit and 1 data cache unit, where the cache units may be synchronous fifos with a depth of 32 and a width of 65, as shown in fig. 5.

Due to the existence of the cache unit, the upper computer can continuously issue a batch (for example, 16 valid read instructions, which do not exceed the fifo depth), refer to fig. 6, and then issue an invalid instruction until all read data corresponding to the 16 read instructions return, and then start the issue of the next batch of valid instructions.

It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by one of ordinary skill in the art and related arts based on the embodiments of the present invention without any creative effort, shall fall within the protection scope of the present invention.

Claims

1. A JTAG read instruction delay processing method is characterized in that if valid read data is not returned when a valid read instruction issued by an upper computer arrives in a new scan chain capturing state, the upper computer issues an invalid instruction until the upper computer receives the valid read data and returns.

2. The JTAG read instruction latency processing method of claim 1, wherein the invalid instruction is an instruction having a most significant bit of 0.

3. The JTAG read instruction latency processing method of claim 2, wherein the JTAG module includes a TAP state machine, an instruction register, a bypass register, a debug scan chain,

4. The JTAG read instruction latency processing method of claim 3, wherein 1 instruction cache unit and 1 data cache unit are connected to the debug scan chain.

5. The JTAG read instruction latency processing method of claim 4, wherein the cache unit is a sync fifo having a depth of 32 and a width of 65.