CN105550119A - Simulation device based on JTAG protocol - Google Patents
Simulation device based on JTAG protocol Download PDFInfo
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- CN105550119A CN105550119A CN201610063492.8A CN201610063492A CN105550119A CN 105550119 A CN105550119 A CN 105550119A CN 201610063492 A CN201610063492 A CN 201610063492A CN 105550119 A CN105550119 A CN 105550119A
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
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- G06F11/3656—Software debugging using additional hardware using a specific debug interface
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Abstract
The invention discloses a simulation device based on a JTAG protocol. The device comprises a parallel bus interface, a JTAG interface, a JTAG simulation processing IP core and an interface conversion unit. One end of the JTAG simulation processing IP core is connected with a debugging host through the parallel bus interface and the interface conversion unit, and the other end of the JTAG simulation processing IP core is connected with a target chip through the JTAG interface. The JTAG simulation processing IP core receives debugging data of the debugging host through the parallel bus interface and the interface conversion unit, converts the data into JTAG data and outputs the JTAG data to the target chip through the JTAG interface. The JTAG simulation processing IP core receives the JTAG data of the target chip through the JTAG interface, converts the JTAG data into data conforming to the parallel bus protocol, and outputs the data to the debugging host through the parallel bus interface and a communication interface conversion unit. The simulation device has the advantages that the structure is simple, the JTAG simulation function can be achieved on the basis of the IP core, the simulation speed is high, and universality and expansibility are high.
Description
Technical field
The present invention relates to JTAG simulation technical field, particularly relate to a kind of simulator based on JTAG agreement.
Background technology
Chip all likely has problems in design, manufacture and encapsulation process, the mistake brought thus not only can affect the performance of whole chip or cause the inefficacy of chip, also can affect development efficiency and the application quality of chip, thus in order to ensure the correctness of chip functions, must also need to debug chip, it is most important that the correctness of debugging and Usefulness Pair produce high-quality chip.The debud mode of current main flow adopts sheet sand covered, namely extra control module is embedded in processor inside, enter special state when meeting certain trigger condition, under this special state, application program is out of service, and main frame is then by the various resources of emulator access chip inside.
The emulator of current employing mainly contains 2 kinds: one is in-circuit emulator (InCircuitEmulator, ICE), this in-circuit emulator is as special commissioning device, need configure dedicated in the joint of certain chip, to make both can be used for monitoring the activity of chip pin and the external environment condition of chip, again can the operation of emulation chip, but all need a kind of ICE corresponding with it during often kind of CPU emulation, and thus cost of development is very high; Another is JTAG emulator (JTAGEmulator), also be a kind of emulator that application is maximum at present, JTAG is a kind of international standard test protocol (IEEE-1149.1 standard), namely JTAG emulator adopts jtag interface, the jtag interface simultaneously provided by chip is debugged, and therefore can save the expense of hardware.When JTAG emulator performs emulation, debug host and objective chip is connected by JTAG emulator, debugging interface logic is provided by objective chip, this logic adopts two-stage pattern, be respectively operational mode and debugging mode, wherein in the operating mode, debug features does not control the operation of chip, and chip system normally works; Under debugging mode, chip stops normal work, then accepts the order that debugging interface sends, and now emulator can read and write the operation etc. of the internal memory of objective chip and register, control program.
When wanting by JTAG control objectives chip, then must be realized by connection emulator, but also there is following problem when applying in JTAG emulator: JTAG emulator is in the processing mode of data stream at present, a kind of mode directly converts the parallel port data of main frame to JTAG data by FPGA or CPLD, then by controlling to realize in host side software programming, this mode speed is slow, and needs main frame support and jaws equipment; A kind of mode is also had to be the emulator communicated by USB serial ports or network interface, although this mode speed is fast, but normally adopt in type application-specific entity circuit board, namely the form of surface-mounted integrated circuit is adopted, and the method mounting an emulator outward again in debug host during owing to emulating at present, usually can only be adopted to communicate, and the interface protocol of different emulators and debug host is also not quite similar, thus use is upper and not convenient, universal performance is poor, and user is difficult to other devices of Integration of Extended and function again.
Summary of the invention
The technical problem to be solved in the present invention is just: the technical matters existed for prior art, the invention provides a kind of structure simple, the fast and versatility of JTAG copying, simulation velocity and the strong simulator based on JTAG agreement of Scalable Performance can be realized based on IP kernel.
For solving the problems of the technologies described above, the technical scheme that the present invention proposes is:
A kind of simulator based on JTAG agreement, comprise parallel bus interface, jtag interface, JTAG process IP kernel and the interface conversion unit for interface logic conversion, one end of described JTAG process IP kernel is by described parallel bus interface, interface conversion unit connects debug host, the other end is by described jtag interface linking objective chip, described JTAG process IP kernel receives the tune-up data of debug host by described parallel bus interface, objective chip is exported to by described jtag interface after being converted to JTAG control data, and described JTAG process IP kernel is by the JTAG data of described jtag interface receiving target chip, be converted to after the data meeting parallel bus protocol by described parallel bus interface, interface conversion unit exports debug host to.
As a further improvement on the present invention: described JTAG process IP kernel comprises for accessing parallel debugging data, exports the data interface module of parallel artificial data, for perform JTAG protocol conversion JTAG modular converter, for performing the data conversion module of data serioparallel exchange and the storage buffer module for carrying out buffer memory to data, described data interface module is connected with described data conversion module by described JTAG modular converter, and described storage buffer module is connected with described data interface module, data conversion module respectively.
As a further improvement on the present invention: described JTAG modular converter comprises interconnective processing unit and status unit, described processing unit is according to described tune-up data configuration JTAG protocol signal, and described status unit produces corresponding JTAG protocol signal as JTAG control data according to the configuration of described processing unit.
As a further improvement on the present invention: described processing unit comprising the control register of the state for configuring JTAG protocol signal, starting the command register of data transmission for configuring the shift count register of serial data shift count in JTAG agreement, the link attribute being used to specify serial data and control, and read, write the read-write buffer register of data for buffer memory, by configuring above-mentioned each register configuration JTAG protocol signal.
As a further improvement on the present invention: during described processing unit configuration, by configuration control register or command register to be configured to JTAG protocol signal Static output state, or according to read-write operation type by configuration control register, shift count register, command register and read-write buffer register respectively to be configured to JTAG protocol signal dynamic data state.
As a further improvement on the present invention: described status unit comprises TMS state machine, described TMS state machine produces JTAG protocol signal according to the sequential of TAP controller state machine in JTAG agreement.
As a further improvement on the present invention: when a startup data manipulation, described status unit receives startup command and starts inner TMS state machine, described TMS state machine carries out State Transferring according to the configuration of described processing unit according to JTAG agreement, and when state is in displaced condition, the status signal producing data shifts sends to data conversion module.
As a further improvement on the present invention: described data conversion module comprises read-write shift register, counter and for controlling the transmission control unit that data are transmitted between described storage buffer module, described read-write shift register performs by described counter controls the serial-shift read and write data and transmits.
As a further improvement on the present invention: during the shift signal that described read-write shift register accepting state control module sends, sampling input data are carried out shifting function and are exported enabling signal to described counter; The enabling signal that described counter receives read-write shift register starts counting, has counted rear output count completion signal to described transmission controlling functions unit; After described transmission controlling functions unit receives count completion signal, control data reading in read-write shift register or write to store buffer module, and control startup is shifted, until shift signal is invalid next time.
As a further improvement on the present invention: described storage buffer module comprises single port RAM body and memory controller.
Compared with prior art, the invention has the advantages that:
1) the present invention is based on the simulator of JTAG agreement, the function of JTAG emulator is realized with the form of IP kernel, with by JTAG emulator IPization, thus use this IP kernel just can complete the function of emulator, realize the replacement to JTAG emulator, make JTAG emulator no longer be confined to the form of circuit board, but can be integrated on SOC as IP kernel or user FPGA in, effectively improve the integrated level of emulator; Additionally provide general parallel interface and jtag interface, the IP kernel thus based on the present embodiment simulator can carry out various application extension easily, substantially increases versatility and the convenience of simulator simultaneously;
2) the present invention is based on the simulator of JTAG agreement, in conjunction with the enough data data meeting parallel bus protocol being converted to standard compliant JTAG agreement of JTAG process IP nuclear energy, export the JTAG control data of control objectives chip; Simultaneously, JTAG process IP kernel is exported by bus after can also converting the JTAG data that objective chip exports to parallel data, realize the exchange of order and data between debug host and objective chip, complete the function of JTAG emulator, and transmission structure is simple, effectively can improve the transfer rate of JTAG serial data;
3) the present invention is based on the simulator of JTAG agreement, JTAG process IP kernel realizes especially by a set of DLC (digital logic circuit), the whole logic of IP kernel uses hardware description language to realize, emulator function is realized without the need to relying on entity circuit board, can be integrated in the design of the chips such as FPGA, ASIC easily, easy to use and configuration;
4) the present invention is based on the simulator of JTAG agreement, on the basis of parallel bus protocol, only need to add any communication interface (as traditional parallel port, USB interface and Ethernet interface etc.) that one end meets parallel bus protocol, the other end meets host communication protocol, just can expand to the communication of interface mode arbitrarily between support and debug host;
5) the present invention is based on the simulator of JTAG agreement, processing unit arranges multiple register further, different JTAG protocol signal can be configured flexibly by the configuration of multiple register and carry out control objectives chip, add dirigibility and the controllability of artificial debugging, the setting of register simultaneously also meets the use habit of embedded system, is thus convenient to realize integrated and expansion.
Accompanying drawing explanation
Fig. 1 is the principle schematic of the present embodiment based on the simulator execution emulation of JTAG agreement.
Fig. 2 is the structural representation of the present embodiment based on the simulator of JTAG agreement.
The realization flow schematic diagram of processing unit configuration register when Fig. 3 is the present embodiment read-write operation.
Fig. 4 is the principle schematic that the present embodiment data conversion module and state control.
Marginal data: 1, JTAG process IP kernel; 11, data interface module; 12, JTAG modular converter; 121, processing unit; 122, status unit; 13, data conversion module; 14, buffer module is stored.
Embodiment
Below in conjunction with Figure of description and concrete preferred embodiment, the invention will be further described, but protection domain not thereby limiting the invention.
As Fig. 1, shown in 2, the present embodiment comprises parallel bus interface based on the simulator of JTAG agreement, jtag interface, JTAG process IP kernel 1 and the interface conversion unit for interface logic conversion, parallel bus interface is passed through in one end of JTAG process IP kernel 1, interface conversion unit connects debug host, the other end is by jtag interface linking objective chip, JTAG process IP kernel 1 receives the tune-up data of debug host by parallel bus interface, objective chip is exported to by described jtag interface after being converted to JTAG control data, and JTAG process IP kernel 1 is by the JTAG data of jtag interface receiving target chip, be converted to after the data meeting parallel bus protocol by described parallel bus interface, interface conversion unit exports debug host to.
IP kernel (intellectualpropertycore, intellectual property core) is form is logical block, and reusable integrated circuit (IC) design module can carry out the logical design of special IC or FPGA based on IP kernel, thus reduces the design cycle.As shown in Figure 1, the present embodiment simulator realizes the function of JTAG emulator between debug host and objective chip with the form of IP kernel, with by JTAG emulator IPization, thus use this IP kernel just can complete the function of emulator, realize the replacement to JTAG emulator, JTAG emulator is made no longer to be confined to the form of circuit board, but can be integrated on SOC or FPGA as IP kernel, effectively improve the integrated level of emulator, the present embodiment simulator provides general parallel interface and jtag interface simultaneously, thus the IP kernel based on the present embodiment simulator can carry out various application extension easily, substantially increase versatility and the convenience of simulator.
The present embodiment parallel bus interface is the interface based on parallel bus protocol, the data meeting parallel bus protocol can be converted to the data of the JTAG agreement meeting IEEE1149.1 standard in conjunction with JTAG process IP kernel 1, export the JTAG control data of control objectives chip, objective chip can be the chip of all kinds of support JTAG agreement; Simultaneously, JTAG process IP kernel 1 is exported by bus after can also converting the JTAG data that objective chip exports to parallel data, realize the exchange of order and data between debug host and objective chip, complete the function of JTAG emulator, and transmission structure is simple, effectively can improve the transfer rate of JTAG serial data, transfer rate specifically can carry out arranging and adjusting according to demand.
The present embodiment interface conversion unit is the interface conversion logic based on parallel bus protocol, can be realized the communication connection of user-defined any communication interface by translation interface logic.The present embodiment JTAG process IP kernel 1 is connected to interface conversion unit by parallel bus interface, interface conversion unit is connected to debug host by user-defined any communication interface again, thus JTAG process IP kernel 1 can be supported, and one end meets any communication interface of parallel bus protocol.Therefore the present embodiment is on the basis of parallel bus protocol, only need to add any communication interface (as traditional parallel port, USB interface and Ethernet interface etc.) that one end meets parallel bus protocol, the other end meets host communication protocol, just can expand to the communication of interface mode arbitrarily between support and debug host.
During emulation testing, the tune-up data of debug host exports JTAG process IP kernel 1 to by parallel bus interface after the interface conversion logic of interface conversion unit, the data that JTAG process IP kernel 1 exports are sent to interface conversion unit by parallel bus interface, and interface conversion unit is supplied to debug host after carrying out interface conversion logic.
As shown in Figure 2, in the present embodiment, JTAG process IP kernel 1 comprises for accessing parallel debugging data, export the data interface module 11(Interface module of parallel artificial data), for performing the JTAG modular converter 12 of JTAG protocol conversion, for performing the data conversion module 13(Trans module of data serioparallel exchange), and for carrying out the storage buffer module 14(FIFO module of buffer memory to data), data interface module 11 is connected with data conversion module 13 by JTAG modular converter 12, store buffer module 14 respectively with data interface module 11, data conversion module 13 connects.By above-mentioned each module composition JTAG process IP kernel 1, the function of JTAG emulator can be realized, when using as IP kernel, workable and can flexible configuration simultaneously.
In the present embodiment, data interface module 11 specifically processes the access of parallel bus, and the parallel data that sample bus imports into, returns parallel data by bus simultaneously.For improving the dirigibility that IP kernel uses, the present embodiment data interface module 11 comprises 2 clocks, and one is user clock, and another is jtag test clock (TCK), wherein user clock is supplied to user interface use, and tck clock is then the work clock of whole IP kernel inside.Asynchronous docking process has also been carried out between above-mentioned 2 clock zone signals in the present embodiment data interface module 11.
As shown in Figure 2, when data interface module 11 processes the access of parallel bus, under CLK clock zone, according to writing data enable signal WE and address signal Addr(the present embodiment width gets 4bit), data-signal Data(the present embodiment width of catching write gets 16bit); Or according to read data enable signal RE and address signal Addr, data-signal Data is exported; Busy signal (Busy) represents that data interface module 11 is in other modules in asynchronous docking operation or IP kernel and is in duty time effective, and therefore read-write operation sends when Busy invalidating signal.
In the present embodiment, JTAG modular converter 12 specifically comprises interconnective processing unit 121(Processor unit) and status unit 122(StateCtrl unit), processing unit 121 is according to tune-up data configuration JTAG protocol signal, and status unit 122 produces corresponding JTAG protocol signal as JTAG control data according to the configuration of processing unit 121.Processing unit 121 specifically process synchronous from data interface module 11 after address date, configure JTAG protocol signal after carrying out address decoding.
In the present embodiment, processing unit 121 comprising the control register of the state for configuring JTAG protocol signal, starting the command register of data transmission for configuring the shift count register of serial data shift count in JTAG agreement, the link attribute being used to specify serial data and control, and read, write the read-write buffer register of data for buffer memory, by configuring above-mentioned each register configuration JTAG protocol signal.The present embodiment processing unit 121 specifically arranges control register (Control register), shift count register (Count register), read buffer register (ReadBuffer register), Write post register (WriteBuffer register) and command register (Command register) totally 5 registers, the width of each register is 16bit, according to each register of address decoding data configuration of data interface module 11, by configuring the difference of above-mentioned 5 registers, can control to produce different JTAG signals.Each register is specially:
Control register (Control register): by configure this register can the unlatching of clock (TCK) in control JTAG agreement, the low level of closedown or stable output or high level; The opening and closing of state of a control signal (TMS); Control the unlatching of serial data output signal (TDO), closedown, the low level of stable output or high level, output valid data;
Shift count register (Count register): the number of times that serial data displacement in JTAG agreement can be specified by configuring this register, wherein the present embodiment is set to maximum support 65536 displacements;
Read buffer register (ReadBuffer register): this register is used for the 16bit data that buffer memory once reads, and is read-only register; According to the difference of address configuration, the source of read data can be the value of other registers in processing unit 121, also can be to store the data in buffer module 14;
Write post register (WriteBuffer register): this register is used for the 16bit data of buffer memory write-once, and is read-only register; According to the difference of address configuration, the target writing data can be other registers in processing unit 121, also can be to store buffer module 14;
Command register (Command register): can the warm reset of all modules in control JTAG process IP kernel 1 by configuring this register, and when controlling to reset, the JTAG reset signal (TRST) of output also can be in reset effective status; Can also control to select data (DR) link or instruction (IR) link in JTAG agreement, the transmission of a startup JTAG serial data can be controlled and the frequency of tck clock can be configured by configuring this register.
Different JTAG protocol signal can be configured flexibly by the configuration of above-mentioned multiple register and carry out control objectives chip, add dirigibility and the controllability of artificial debugging, the simultaneously setting of register also meets the use habit of embedded system, is thus convenient to realize integrated.
When the present embodiment processing unit 121 configures, by configuration control register or command register to be configured to JTAG protocol signal Static output state, or according to read-write operation type by configuration control register, shift count register, command register and read-write buffer register respectively to be configured to JTAG protocol signal dynamic data state.During configuration signal Static output, by configuration Control register or Command register, TMS, TDO and TRST signal of JTAG is exported and keeps stable dead level or maintain high-impedance state, this configuration is applied to particular demands pattern; During configuration dynamic data, make jtag interface correctly effectively can export, input data by configuring above-mentioned each register, this configuration is applied to normal mode of operation.
The present embodiment configuration dynamic data as shown in Figure 3, configures Control register first according to demand, specifies the data output source of JTAG to be data from write or steady state value; Then configure Count register, specify the number of serial date transfer or output; Restart Command register, specify the link attribute of serial data, and start a data manipulation, specifically comprise:
When using read operation, first configuring a startup data manipulation, making JTAG process IP kernel 1 enter data transmission state, and the data of transmission can keep in storage buffer module 14; When after Busy invalidating signal, data are read, when multiple data are read, then need repeatedly to configure ReadBuffer register by configuration ReadBuffer register from storage buffer module 14;
When using write operation, first configure WriteBuffer register data to be write, the data of write can be kept in and be stored in buffer module 14; Then after configuring a startup data manipulation, make JTAG process IP kernel 1 enter data transmission state, the data stored in buffer module 14 are exported; When after Busy invalidating signal, restart write operation next time, during multiple data write, then need repeatedly to configure WriteBuffer register.
In the present embodiment, status unit 122 comprises TMS state machine, TMS state machine produces JTAG protocol signal according to the sequential of TAP controller state machine in JTAG agreement, namely TMS state machine is with reference to the TAP(TestAccessPort in JTAG agreement, test access port) controller state machine sequential perform, thus can configure according to the difference of Control register and Count register in processing unit 121, produce various different TMS, TRST and TDO signal (JTAG protocol signal), and export with the form meeting IEEE1149.1 standard agreement under tck clock territory.
In the present embodiment, when after a startup data manipulation, status unit 122 receives startup command, start inner TMS state machine, TMS state machine can according to the configuration in Command register, select to complete the conversion of whole state by IR command link or DR data link according to JTAG agreement, namely State Transferring meets the requirement of JTAG standard agreement; When state is in displacement (Shift-State) state, the status signal (Data_Shift) of data shifts can be produced and send to data conversion module 13, notifying that it starts data shifts.
What the concrete data cache interface module 11 of the present embodiment storage buffer module 14 exported writes data, process to be transferred to data conversion module 13, and the data that data cached modular converter 13 exports, process to be transferred to data interface module 11, thus can data cache interface module 11 send write data, and be transferred to data conversion module 13 and process, also can the data sent of data cached modular converter 13 be transferred to data interface module 11 and process.Store buffer module 14 when data write full after, then send signal notice follow-up data and suspend and write.The present embodiment, based on parallel bus, thus can carry out by Busy signal the state that perception stores buffer module 14.
In the present embodiment, store buffer module 14 and specifically comprise a single port RAM body and memory controller, wherein the data width of RAM body specifically gets 16bit, the degree of depth gets 2K, and arranges the storage of maximum support 32Kb data.
In the present embodiment, the transmission control unit that data conversion module 13 comprises read-write shift register, counter and transmits for data between control with storage buffer module (14), read-write shift register performs by counter controls the serial-shift read and write data and transmits to complete data serioparallel exchange.As shown in Figure 4, the present embodiment specifically comprises 2 shift registers (ShiftReg), the counter (Counter16) of 1 16 and 2 transmission controlling functions unit (TransferFunction), the serial-shift be responsible for process read data respectively by 2 shift registers and write data transmits, counter for control to read and write data serioparallel exchange, transmission controlling functions unit controls shift register and the data interaction that stores between buffer module 14.
In the present embodiment, the shift signal that read-write shift register accepting state control module 122 sends, sampling input data TDI carries out shifting function and exports enabling signal to counter; The enabling signal that counter receives read-write shift register starts counting, has counted rear output count completion signal to transmission controlling functions unit; Transmit controlling functions unit count pick up settling signal, control to write data reading or write in shift register and store buffer module 14, and control startup is shifted, until shift signal is invalid next time.
The serial-shift transmission that data conversion module 13 performs reading and writing data is specially:
When data are read, receive that processing unit 121 sends read useful signal after, according to the Data_Shift shift signal that status unit 122 is sent, read shift unit ReadShiftReg and start working, sampled data TDI also carries out shifting function; Start counter Counter16 simultaneously and start counting, count after completing for 16 times, send count completion signal.After transmission controlling functions unit TransferFunction receives count completion signal, the data write in shift register is stored in buffer module 14, and controls again to start displacement; After said process is continued until Data_Shift invalidating signal, counter stops counting, and displacement stops thereupon;
When writing data, receive that processing unit 121 sends write useful signal after, according to the Data_Shift shift signal that status unit 122 is sent, write shift unit WriteShiftReg and start working, carry out shifting function and data TDO is exported; Start counter Counter16 simultaneously and start counting, count after completing for 16 times, send count completion signal; After transmission controlling functions unit TransferFunction receives count completion signal, from storage buffer module 14, read next parallel data put into shift register, and control again to start displacement; Said process is continued until Data_Shift invalidating signal, and counter stops counting, and displacement stops thereupon.
In the present embodiment data conversion module 13, whole shifting process controls by Data_Shift shift signal, and data TDI and the TMS be therefore shifted works in coordination, and thus meets JTAG agreement.
The present embodiment JTAG process IP kernel 1 realizes especially by a set of DLC (digital logic circuit), the above-mentioned whole logic of IP kernel uses hardware description language to realize, emulator function is realized without the need to relying on entity circuit board, can be integrated in the design of the chips such as FPGA, ASIC easily, easy to use and configuration.
Above-mentioned just preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Therefore, every content not departing from technical solution of the present invention, according to the technology of the present invention essence to any simple modification made for any of the above embodiments, equivalent variations and modification, all should drop in the scope of technical solution of the present invention protection.
Claims (10)
1. the simulator based on JTAG agreement, it is characterized in that: comprise parallel bus interface, jtag interface, JTAG process IP kernel (1) and the interface conversion unit for interface logic conversion, one end of described JTAG process IP kernel (1) is by described parallel bus interface, interface conversion unit connects debug host, the other end is by described jtag interface linking objective chip, described JTAG process IP kernel (1) is by described parallel bus interface, interface conversion unit receives the tune-up data of debug host, objective chip is exported to by described jtag interface after being converted to JTAG control data, and described JTAG process IP kernel (1) is by the JTAG data of described jtag interface receiving target chip, be converted to after the data meeting parallel bus protocol by described parallel bus interface, interface conversion unit exports debug host to.
2. the simulator based on JTAG agreement according to claim 1, it is characterized in that: described JTAG process IP kernel (1) comprises for receiving parallel debugging data, export the data interface module (11) of parallel artificial data, for performing the JTAG modular converter (12) of JTAG protocol conversion, for performing the data conversion module (13) of data serioparallel exchange, and for carrying out the storage buffer module (14) of buffer memory to data, described data interface module (11) is connected with described data conversion module (13) by described JTAG modular converter (12), described storage buffer module (14) respectively with described data interface module (11), data conversion module (13) connects.
3. the simulator based on JTAG agreement according to claim 2, it is characterized in that: described JTAG modular converter (12) comprises interconnective processing unit (121) and status unit (122), described processing unit (121) is according to described tune-up data configuration JTAG protocol signal, and described status unit (122) produces corresponding JTAG protocol signal as JTAG control data according to the configuration of described processing unit (121).
4. the simulator based on JTAG agreement according to claim 3, it is characterized in that: described processing unit (121) comprising the control register of the state for configuring JTAG protocol signal, starting the command register of data transmission for configuring the shift count register of serial data shift count in JTAG agreement, the link attribute being used to specify serial data and control, and read, write the read-write buffer register of data for buffer memory, by configuring above-mentioned each register configuration JTAG protocol signal.
5. the simulator based on JTAG agreement according to claim 4, it is characterized in that: during described processing unit (121) configuration, by configuration control register or command register to be configured to JTAG protocol signal Static output state, or according to read-write operation type by configuration control register, shift count register, command register and read-write buffer register respectively to be configured to JTAG protocol signal dynamic data state.
6. the simulator based on JTAG agreement according to claim 3 or 4 or 5, it is characterized in that, described status unit (122) comprises TMS state machine, and described TMS state machine produces JTAG protocol signal according to the sequential of TAP controller state machine in JTAG agreement.
7. the simulator based on JTAG agreement according to claim 6, it is characterized in that: when a startup data manipulation, described status unit (122) receives startup command and starts inner TMS state machine, described TMS state machine carries out State Transferring according to the configuration of described processing unit (121) according to JTAG agreement, and when state is in displaced condition, the status signal producing data shifts sends to data conversion module (13).
8. according to the simulator based on JTAG agreement in claim 2 ~ 5 described in any one, it is characterized in that: the transmission control unit that described data conversion module (13) comprises read-write shift register, counter and transmits for data between control with described storage buffer module (14), described read-write shift register performs by described counter controls the serial-shift read and write data and transmits.
9. the simulator based on JTAG agreement according to claim 8, it is characterized in that: during the shift signal that described read-write shift register accepting state control module (122) sends, sampling input data are carried out shifting function and are exported enabling signal to described counter; The enabling signal that described counter receives read-write shift register starts counting, has counted rear output count completion signal to described transmission controlling functions unit; After described transmission controlling functions unit receives count completion signal, control data reading in read-write shift register or write to store buffer module (14), and control startup is shifted, until shift signal is invalid next time.
10. according to the simulator based on JTAG agreement in claim 2 ~ 5 described in any one, it is characterized in that: described storage buffer module (14) comprises single port RAM body and memory controller.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106527402A (en) * | 2016-12-02 | 2017-03-22 | 深圳市紫光同创电子有限公司 | FPGA debugging conversion equipment, system and method |
| CN107122304A (en) * | 2017-05-03 | 2017-09-01 | 成都定为电子技术有限公司 | A kind of JTAG remote debugging methods |
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| CN109426594A (en) * | 2017-08-25 | 2019-03-05 | 深圳市中兴微电子技术有限公司 | A kind of chip debugging apparatus, method and computer readable storage medium |
| CN110659037A (en) * | 2019-09-25 | 2020-01-07 | 苏州浪潮智能科技有限公司 | JTAG-based burning device |
| CN111858415A (en) * | 2020-07-30 | 2020-10-30 | 山东超越数控电子股份有限公司 | Multichannel and multiprotocol hardware acceleration method for data receiving and storing |
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| CN116483288A (en) * | 2023-06-21 | 2023-07-25 | 苏州浪潮智能科技有限公司 | Memory control equipment, method and device and server memory module |
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| WO2017190544A1 (en) * | 2016-05-05 | 2017-11-09 | 中兴通讯股份有限公司 | Data transmission cable and data transmission method |
| CN106527402A (en) * | 2016-12-02 | 2017-03-22 | 深圳市紫光同创电子有限公司 | FPGA debugging conversion equipment, system and method |
| CN107688528A (en) * | 2016-12-23 | 2018-02-13 | 北京国睿中数科技股份有限公司 | The debugging system and method for processor under simulation model |
| CN107122304A (en) * | 2017-05-03 | 2017-09-01 | 成都定为电子技术有限公司 | A kind of JTAG remote debugging methods |
| CN107122304B (en) * | 2017-05-03 | 2021-03-23 | 成都定为电子技术有限公司 | JTAG remote debugging method |
| CN109426594A (en) * | 2017-08-25 | 2019-03-05 | 深圳市中兴微电子技术有限公司 | A kind of chip debugging apparatus, method and computer readable storage medium |
| CN107608846B (en) * | 2017-08-30 | 2020-09-29 | 西安微电子技术研究所 | Debugging link and debugging method for embedded TAP interface of FPGA |
| CN107608846A (en) * | 2017-08-30 | 2018-01-19 | 西安微电子技术研究所 | A kind of debugging link and adjustment method that TAP interfaces are embedded for FPGA |
| CN108519953A (en) * | 2018-04-17 | 2018-09-11 | 长沙景美集成电路设计有限公司 | A kind of GPGPU debugging techniques realization based on JTAG |
| CN110659037A (en) * | 2019-09-25 | 2020-01-07 | 苏州浪潮智能科技有限公司 | JTAG-based burning device |
| CN110659037B (en) * | 2019-09-25 | 2021-03-09 | 苏州浪潮智能科技有限公司 | JTAG-based burning device |
| US20220317178A1 (en) * | 2019-09-25 | 2022-10-06 | Inspur Suzhou Intelligent Technology Co., Ltd | JTAG-Based Burning Device |
| US11874323B2 (en) | 2019-09-25 | 2024-01-16 | Inspur Suzhou Intelligent Technology Co., Ltd. | JTAG-based burning device |
| CN111858415A (en) * | 2020-07-30 | 2020-10-30 | 山东超越数控电子股份有限公司 | Multichannel and multiprotocol hardware acceleration method for data receiving and storing |
| CN111858415B (en) * | 2020-07-30 | 2024-03-15 | 超越科技股份有限公司 | Multi-channel multi-protocol hardware acceleration method for data receiving and storing |
| CN114035472A (en) * | 2021-11-09 | 2022-02-11 | 阳光学院 | Method and terminal for on-line programming of embedded programmable controller by CAN bus |
| CN114035472B (en) * | 2021-11-09 | 2024-05-10 | 阳光学院 | Method and terminal for on-line programming of CAN bus to embedded programmable controller |
| CN116881185A (en) * | 2023-06-14 | 2023-10-13 | 珠海妙存科技有限公司 | JTAG interface signal switching method, system, equipment, device and medium |
| CN116483288A (en) * | 2023-06-21 | 2023-07-25 | 苏州浪潮智能科技有限公司 | Memory control equipment, method and device and server memory module |
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