CN114531422A - Bus address automatic allocation and identification method, electronic device, storage medium and program product - Google Patents
Bus address automatic allocation and identification method, electronic device, storage medium and program product Download PDFInfo
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- CN114531422A CN114531422A CN202111647163.5A CN202111647163A CN114531422A CN 114531422 A CN114531422 A CN 114531422A CN 202111647163 A CN202111647163 A CN 202111647163A CN 114531422 A CN114531422 A CN 114531422A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004590 computer program Methods 0.000 claims description 11
- 230000006870 function Effects 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 2
- 238000004891 communication Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- General Engineering & Computer Science (AREA)
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Abstract
The invention provides a bus address automatic allocation and identification method, which comprises the following steps: the host sends a cascade command to the first bus to reset the addresses of all the slaves connected to the first bus; the master sends broadcast, configuration and handshake commands to the first bus in a circulating sequence, and waits for the slave to respond; according to the connection sequence of the devices on the second bus, the host sends an address command to the first slave machine through the second bus, the first slave machine receiving the address command responds to the first bus, after the first slave machine completes distribution, the first slave machine sends the address command to the second slave machine through the second bus, and the second slave machine receiving the address command responds to the first bus and executes circularly until all the slave machines complete address configuration. The invention relates to an electronic device, a storage medium, and a program product. The invention has the advantages of flexibility, low requirement on field operation personnel and low error rate, and avoids the condition of equipment loss caused by a bus competition mode.
Description
Technical Field
The present invention relates to the field of data communication technologies, and in particular, to a method for automatically allocating and identifying a bus address, an electronic device, a storage medium, and a program product.
Background
The RS485 bus needs to configure the device address before being used to carry out networking communication. Currently, RS485 bus address allocation methods include manual allocation and automatic allocation. The manual allocation means that personnel is required to perform address allocation on each slave machine one by one and then all the equipment is connected through the bus, the operation required is relatively complex, the method is inflexible, and the requirement on personnel operating on site is high. The automatic allocation means that each device of the bus can automatically complete the address configuration work in a non-manual mode; the method has low requirement on personnel and low error rate, and in order to realize the function, a bus competition mode is usually adopted in the industry, but equipment loss is easy to occur; meanwhile, the method cannot add new equipment and lacks a related identification mechanism.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an automatic bus address allocation and identification method, and solves the problems that the existing RS485 bus address allocation method is inflexible, has high requirements on field operation personnel, is easy to lose equipment, cannot add new equipment, and lacks a related identification mechanism.
The invention provides a bus address automatic allocation and identification method, which comprises the following steps:
sending a cascade command, wherein the host sends the cascade command to the first bus to reset the addresses of all the slaves connected to the first bus;
circularly sending commands, wherein the host sends broadcast, configuration and handshake commands to the first bus circularly and sequentially to wait for the slave to respond;
sending an address command, wherein according to the connection sequence of the devices on the second bus, the host sends the address command to the first slave through the second bus, the first slave receiving the address command responds to the first bus, and the slave not receiving the address command is silent; and circulating the steps until all the slave machines complete the address configuration.
Further, a specification protocol is further included before the step of sending the cascade command, and a unified command is set at the master and the slave.
Further, in the step of specifying the protocol, the unified command includes a start symbol, an address code, a function code, a start address, a data length, a CRC check, and an end symbol.
Further, a physical interface is also specified before the step of sending the cascade command, the host and the slave are both connected to the first bus, and the host and the slave are sequentially connected through the second bus.
Further, in the step of normalizing the physical interfaces, the master is connected with the receiving port of the first slave through a second bus, the sending port of the first slave is connected with the receiving port of the second slave through the second bus, and the step is executed in a circulating manner until all the slaves are connected.
And further, the method also comprises newly-added equipment, the host sends a read command aiming at the initial equipment to the first bus at intervals of preset time, and if the host responds, the host performs the operation of reallocating the address to the bus.
Further, the method also comprises a lost device, and in the process of reading and writing the slave by the host, if the slave does not respond and the preset number of reading times is accumulated without responding, the host performs the operation of reallocating the address to the bus.
An electronic device, comprising: a processor;
a memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for performing a bus address automatic assignment and identification method.
A computer-readable storage medium having stored thereon a computer program for executing by a processor a method for bus address automatic assignment and identification.
A computer program product comprising computer programs/instructions which, when executed by a processor, implement a method of bus address automatic assignment and identification.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a bus address automatic allocation and identification method, which has high flexibility, low requirement on field operation personnel and low error rate; according to the equipment connection sequence on the second bus, the address configuration is carried out on the next equipment by the previous equipment, the condition that the equipment is lost due to a bus competition mode is avoided, the conditions of newly adding the equipment and losing the equipment can be identified and the address can be distributed again, the actual use scene is fitted, and the actual requirement is met.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings. The detailed description of the present invention is given in detail by the following examples and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a connection between a master and a slave according to the present invention;
FIG. 2 is a flow chart of a method for automatically allocating and identifying bus addresses according to the present invention;
FIG. 3 is a flow chart of the steps of adding devices according to the present invention;
fig. 4 is a flow chart of the lost device steps of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
A bus address automatic allocation and identification method, as shown in FIG. 1 and FIG. 2, includes the following steps:
the protocol is standardized, and unified commands are set in the host and the slave, so that the master and the slave can realize the functions of cascade connection, configuration and handshake in the same bus network. As shown in table 1, the unified command includes a start symbol, an address code, a function code, a start address, a data length, a CRC check, and an end symbol.
TABLE 1 unified Command of Master and Slave settings
The standard physical interface connects both the master and the slave to the first bus (bus a of fig. 1), and the master and the slave are connected in sequence via the second bus (bus B of fig. 1). Specifically, the master is connected to the receive port of the first slave (slave 1 in fig. 1) through the second bus, the transmit port of the first slave is connected to the receive port of the second slave (slave 2 in fig. 1) through the second bus, and this step is executed in a loop until all the slaves are connected. In this embodiment, the first bus is an RS485 bus.
Sending a cascade command, wherein the host sends the cascade command to the first bus to reset the addresses of all the slaves connected to the first bus;
circularly sending commands, wherein the host sends broadcast, configuration and handshake commands to the first bus circularly and sequentially to wait for the slave to respond;
sending an address command, according to the connection sequence of the devices on the second bus, the master sends an address 01 command to the first slave through the second bus, the first slave receiving the address command responds to the first bus, the slaves (2, 3, …, N) not receiving the address command are silent, after the first slave completes the allocation, the first slave sends an address 02 command to the second slave through the second bus, the second slave receiving the address command responds to the first bus, and the slaves (3, …, N) not receiving the address command are silent; and circulating the steps until all the slave machines complete the address configuration.
After the addresses of the slave machines are distributed, the host machine knows how many slave machines exist in the current bus, and then a redistribution working flow is provided for the newly added equipment and the lost equipment.
As shown in fig. 3, the system further includes a new device, so that the bus can have an automatic identification function for a newly added slave, the host sends a read command for the initial device to the first bus every preset time, and if there is a response, the host performs an operation of reallocating an address to the bus.
As shown in fig. 4, the method further includes a lost device, and in the process of reading and writing the slave by the host, if it is found that the slave does not respond and the preset number of times of reading is accumulated without responding, the host performs an operation of reallocating an address to the bus.
The invention provides a bus address automatic allocation and identification method, which has high flexibility, low requirement on field operation personnel and low error rate; according to the equipment connection sequence on the second bus, the address configuration is carried out on the next equipment by the previous equipment, the condition that the equipment is lost due to a bus competition mode is avoided, the conditions of newly adding the equipment and losing the equipment can be identified and the address can be distributed again, the actual use scene is fitted, and the actual requirement is met.
An electronic device, comprising: a processor;
a memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for performing a bus address automatic assignment and identification method.
A computer-readable storage medium having stored thereon a computer program for executing by a processor a method for bus address automatic assignment and identification.
A computer program product comprising computer programs/instructions which, when executed by a processor, implement a method of bus address automatic assignment and identification.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those skilled in the art can readily practice the invention as shown and described in the drawings and detailed description herein; however, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims; meanwhile, any changes, modifications, and evolutions of the equivalent changes of the above embodiments according to the actual techniques of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (10)
1. A bus address automatic allocation and identification method is characterized by comprising the following steps:
sending a cascade command, wherein the host sends the cascade command to the first bus to reset the addresses of all the slaves connected to the first bus;
circularly sending commands, wherein the host sends broadcast, configuration and handshake commands to the first bus circularly and sequentially to wait for the slave to respond;
sending an address command, wherein according to the connection sequence of the devices on the second bus, the host sends the address command to the first slave through the second bus, the first slave receiving the address command responds to the first bus, and the slave not receiving the address command is silent; and circulating the steps until all the slave machines complete the address configuration.
2. A method for automatically assigning and identifying bus addresses as recited in claim 1, wherein: and a specification protocol is further included before the step of sending the cascade command, and unified commands are set at the master and the slave.
3. A method for automatically assigning and identifying bus addresses as claimed in claim 2, wherein: in the step of standardizing the protocol, the unified command comprises a start symbol, an address code, a function code, a start address, a data length, a CRC check and an end symbol.
4. A method for automatically assigning and identifying bus addresses as recited in claim 1, wherein: and before the step of sending the cascade command, a physical interface is also specified, the host and the slave are both connected to the first bus, and the host and the slave are sequentially connected through the second bus.
5. The method for automatically allocating and identifying bus addresses as claimed in claim 4, wherein: in the step of standardizing the physical interfaces, the host is connected with a receiving port of a first slave machine through a second bus, a sending port of the first slave machine is connected with a receiving port of a second slave machine through the second bus, and the step is executed in a circulating mode until all the slave machines are connected.
6. A method for automatically assigning and identifying bus addresses as recited in claim 1, wherein: the method also comprises newly-added equipment, wherein the host sends a read command aiming at the initial equipment to the first bus every preset time, and if a response exists, the host performs the operation of reallocating the address to the bus.
7. A method for automatically assigning and identifying bus addresses as recited in claim 1, wherein: and the host performs address reassignment operation on the bus if the host finds that the slave does not respond and accumulates the reading preset times without responding in the process of reading and writing the slave by the host.
8. An electronic device, characterized by comprising: a processor;
a memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for carrying out the method according to any one of claims 1-7.
9. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program is executed by a processor for performing the method according to any of claims 1-7.
10. A computer program product comprising computer programs/instructions, characterized in that the computer programs/instructions, when executed by a processor, implement the method according to any of claims 1-7.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111647163.5A CN114531422A (en) | 2021-12-30 | 2021-12-30 | Bus address automatic allocation and identification method, electronic device, storage medium and program product |
| PCT/CN2022/097534 WO2023123874A1 (en) | 2021-12-30 | 2022-06-08 | Automatic bus address allocation and identification method, electronic device, storage medium, and program product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111647163.5A CN114531422A (en) | 2021-12-30 | 2021-12-30 | Bus address automatic allocation and identification method, electronic device, storage medium and program product |
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| Publication Number | Publication Date |
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| CN114531422A true CN114531422A (en) | 2022-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111647163.5A Pending CN114531422A (en) | 2021-12-30 | 2021-12-30 | Bus address automatic allocation and identification method, electronic device, storage medium and program product |
Country Status (2)
| Country | Link |
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| CN (1) | CN114531422A (en) |
| WO (1) | WO2023123874A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115494553A (en) * | 2022-10-12 | 2022-12-20 | 中国科学院电工研究所 | Variable multi-electromagnetic-detection slave machine addressing method |
| CN116166594A (en) * | 2023-04-26 | 2023-05-26 | 闪极科技(深圳)有限公司 | IIC bus circuit of single-address multi-slave machine and transmission method and device thereof |
| WO2023123874A1 (en) * | 2021-12-30 | 2023-07-06 | 如果新能源科技(江苏)股份有限公司 | Automatic bus address allocation and identification method, electronic device, storage medium, and program product |
| CN116684389A (en) * | 2023-08-02 | 2023-09-01 | 苏州路之遥科技股份有限公司 | Address automatic allocation method and host, slave and communication equipment with same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116644012B (en) * | 2023-07-26 | 2023-12-22 | 深圳市逸云天电子有限公司 | Bus communication method, electronic equipment and computer readable storage medium |
| CN117880249B (en) * | 2024-03-11 | 2024-05-28 | 西安博康电子有限公司 | Automatic addressing method for differential communication bus unit |
| CN118101375B (en) * | 2024-04-26 | 2024-07-09 | 南京实点电子科技有限公司 | Token scheduling system and communication method based on RS485 bus and one master and multiple slaves |
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| CN113111018A (en) * | 2021-04-08 | 2021-07-13 | 深圳力维智联技术有限公司 | Bus device addressing method and computer readable storage medium |
| CN114531422A (en) * | 2021-12-30 | 2022-05-24 | 如果新能源科技(江苏)股份有限公司 | Bus address automatic allocation and identification method, electronic device, storage medium and program product |
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2021
- 2021-12-30 CN CN202111647163.5A patent/CN114531422A/en active Pending
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2022
- 2022-06-08 WO PCT/CN2022/097534 patent/WO2023123874A1/en unknown
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112055096A (en) * | 2020-08-07 | 2020-12-08 | 深圳市克莱沃电子有限公司 | Method and device for automatically setting communication address of equipment |
| CN113676359A (en) * | 2021-09-09 | 2021-11-19 | 广州安的电子科技有限公司 | Internet of things multi-device communication configuration method, communication device, program product and medium |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023123874A1 (en) * | 2021-12-30 | 2023-07-06 | 如果新能源科技(江苏)股份有限公司 | Automatic bus address allocation and identification method, electronic device, storage medium, and program product |
| CN115494553A (en) * | 2022-10-12 | 2022-12-20 | 中国科学院电工研究所 | Variable multi-electromagnetic-detection slave machine addressing method |
| CN115494553B (en) * | 2022-10-12 | 2024-06-18 | 中国科学院电工研究所 | Variable multi-electromagnetic detection slave machine addressing method |
| CN116166594A (en) * | 2023-04-26 | 2023-05-26 | 闪极科技(深圳)有限公司 | IIC bus circuit of single-address multi-slave machine and transmission method and device thereof |
| CN116684389A (en) * | 2023-08-02 | 2023-09-01 | 苏州路之遥科技股份有限公司 | Address automatic allocation method and host, slave and communication equipment with same |
| CN116684389B (en) * | 2023-08-02 | 2023-10-31 | 苏州路之遥科技股份有限公司 | Address automatic allocation method and host, slave and communication equipment with same |
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| Publication number | Publication date |
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| WO2023123874A1 (en) | 2023-07-06 |
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