CN114530414A - Method for manufacturing semiconductor chip - Google Patents
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- CN114530414A CN114530414A CN202210054875.4A CN202210054875A CN114530414A CN 114530414 A CN114530414 A CN 114530414A CN 202210054875 A CN202210054875 A CN 202210054875A CN 114530414 A CN114530414 A CN 114530414A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
The embodiment of the invention discloses a semiconductor chip manufacturing method, which comprises the following steps: forming a wafer group formed by laminating at least two wafer layers; forming a mask layer with a cutting pattern on at least one surface of the wafer group; and synchronously cutting at least two wafer layers in the wafer group along the cutting pattern.
Description
The present application is a divisional application of a patent having an application date of 2019, 03 and 29, an application number of 201910248959.X, entitled "semiconductor chip manufacturing method".
Technical Field
The embodiment of the invention relates to the field of integrated circuits, in particular to a semiconductor chip manufacturing method.
Background
In the integrated circuit industry, it is generally necessary to cut a wafer formed with circuit element structures into individual chips and then make the chips into semiconductor package structures with different functions, wherein the quality of the cut on the wafer directly affects the yield of the chips. The existing cutting technology has poor cutting quality, is easy to cause chip damage, and reduces the yield of chips. Therefore, it is desirable to provide a semiconductor chip manufacturing method capable of improving the dicing efficiency and the chip yield.
Disclosure of Invention
In view of the above, an embodiment of the present invention provides a method for manufacturing a semiconductor chip, including:
forming a wafer group formed by laminating at least two wafer layers;
forming a mask layer with a cutting pattern on at least one surface of the wafer group;
and synchronously cutting at least two wafer layers in the wafer group along the cutting pattern.
Optionally, the forming a mask layer with a cutting pattern on at least one surface of the wafer group includes at least one of:
forming a first mask layer with a cutting pattern on a first surface of the wafer group;
and forming a second mask layer with a cutting pattern on a second surface of the wafer group, wherein the second surface is the opposite surface of the first surface.
Optionally, the cutting pattern comprises:
a first type of cutting channel for simultaneously cutting at least two wafer layers;
a second type of dicing channel for individually dicing a layer of wafers.
Optionally, the synchronously cutting at least two wafer layers in the wafer group along the cutting pattern includes:
etching the wafer group along the cutting pattern by using plasma;
or the like, or, alternatively,
cutting a first portion of the group of wafers along the cutting pattern using plasma etching; and applying pressure on the surface of the wafer group to separate the wafer group from a second part corresponding to the first part.
Optionally, after said etching through the wafer set with plasma,
or the like, or, alternatively,
after the group of wafers is separated from the second portion corresponding to the first portion,
separating the different wafer layers.
Optionally, the forming a mask layer with a cutting pattern on at least one surface of the wafer group includes:
forming a barrier layer on at least one surface of the wafer group;
coating photoresist on the surface of the barrier layer;
and forming a cutting pattern on the photoresist.
Optionally, the method further comprises:
and after synchronously cutting at least two wafer layers in the wafer group along the cutting pattern, removing the mask layer on the surface of the wafer group.
Optionally, the gas from which the plasma is generated comprises at least one of: oxygen, nitrogen, chlorine-based gas, fluorine-based gas, inert gas.
Optionally, the material of the barrier layer comprises at least one of: amorphous carbon, silicon oxynitride, silicon nitride.
According to the manufacturing method of the semiconductor chip provided by the embodiment of the invention, a wafer group formed by laminating at least two wafer layers is formed; forming a mask layer with a cutting pattern on at least one surface of the wafer group; the manufacturing method provided by the embodiment of the invention has the advantages that the number of the shielding layers is reduced, the wafer cutting cost is reduced, and the wafer cutting efficiency is improved compared with the method for cutting each wafer layer independently; in addition, compared with the method for cutting a single-layer wafer, the embodiment of the invention forms a plurality of wafer layers into the wafer group, and when the wafer group is cut, the interaction between the wafer layers can play a role in buffering the acting force generated by cutting, thereby avoiding the damage of the wafer caused by overlarge cutting acting force, reducing the breakage rate and the process difficulty of the wafer, and improving the yield of chips.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor chip according to an embodiment of the present invention;
fig. 2 to fig. 5 are schematic diagrams illustrating a method for manufacturing a semiconductor chip according to an embodiment of the invention;
fig. 6 to 9 are schematic views illustrating another semiconductor chip manufacturing method according to an embodiment of the invention.
Detailed Description
The technical solution of the present invention will be further elaborated with reference to the drawings and the embodiments. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.
In the embodiments of the present application, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
The technical means described in the embodiments of the present invention may be arbitrarily combined without conflict.
Accordingly, as shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a semiconductor chip, including:
step S10: forming a wafer group formed by laminating at least two wafer layers;
step S20: forming a mask layer with a cutting pattern on at least one surface of the wafer group;
step S30: and synchronously cutting at least two wafer layers in the wafer group along the cutting pattern.
In an embodiment of the present invention, the step S10 may include at least one of:
the first method is as follows:
for at least two wafer layers, forming a first bonding region on one surface of each wafer layer, and forming a second bonding region on the opposite surface of the surface on which the first bonding region is formed; aligning and bonding the first bonding region of one wafer layer with the first bonding region or the second bonding region of the other wafer layer, so that the two wafer layers are electrically connected to form a laminated wafer group;
the second method comprises the following steps:
and carrying out melt adhesive bonding on at least two wafer layers. And when the glue melting bonding is carried out, at least one surface of each wafer layer is chemically treated to enable the treated surfaces to have adsorption force, and then at least two wafer layers are bonded through the treated surfaces to form a laminated wafer group.
In an embodiment of the invention, for a wafer group, before forming a mask layer, the method may include: and processing at least one surface of the wafer group by a chemical mechanical polishing mode to reduce the thickness of the wafer group. By thinning the thickness of the wafer group, the thickness required to be etched can be reduced, the cutting efficiency is improved, and the manufacturing efficiency of the semiconductor chip is further improved.
In some inventive embodiments, step S20 includes at least one of:
forming a first mask layer with a cutting pattern on a first surface of the wafer group;
and forming a second mask layer with a cutting pattern on a second surface of the wafer group, wherein the second surface is the opposite surface of the first surface.
In the embodiment of the invention, the mask layer can be formed on only one surface of the wafer group, and during cutting, only the single-side cutting is carried out on the surface of the wafer group with the mask layer; the mask layers may be formed on both opposite surfaces of the wafer group, i.e., the first mask layer and the second mask layer, wherein the cutting patterns of the first mask layer and the second mask layer may be the same or different. During cutting, the wafer group can be subjected to double-sided cutting through the first mask layer and the second mask layer.
With the increase of the thickness of the wafer group, the depth to be cut is deepened, the process difficulty of cutting through the wafer group from only one surface is gradually increased, and the deeper the cutting depth is, the cutting quality is gradually deteriorated. Therefore, the mask layers can be formed on the two opposite surfaces of the wafer group, the depth required to be cut when each surface is cut is reduced in a double-sided cutting mode, the process difficulty is reduced, the cutting efficiency and quality are improved, and the chip quality is further improved.
In some embodiments, the cutting pattern comprises:
a first type of cutting channel for simultaneously cutting at least two wafer layers;
a second type of dicing channel for individually dicing a layer of wafers.
In the embodiment of the invention, if the patterns to be cut are different between wafer layers, a mask layer simultaneously comprising a first type of cutting channels and a second type of cutting channels can be formed on at least one surface of the wafer group; simultaneously cutting at least two wafer layers in the wafer group along the first type cutting channel; and cutting a wafer layer along the second type of cutting channel to meet different cutting requirements.
In some inventive embodiments, step S20 includes:
forming a barrier layer on at least one surface of the wafer group;
coating photoresist on the surface of the barrier layer;
and forming a cutting pattern on the photoresist.
In this embodiment, the material of the barrier layer may include at least one of: amorphous carbon, silicon oxynitride, silicon nitride.
In the embodiment of the invention, the barrier layer material is used for protecting the wafer group, and the wafer group is ensured to be cut only according to the cutting pattern in the cutting process.
In this embodiment, the photoresist may be a positive photoresist or a negative photoresist. After the positive photoresist is exposed by ultraviolet light, an exposed area of the positive photoresist is easy to dissolve, and the exposed area is washed away in a developing solution, so that a pattern with the same shape as that of a mask is formed in the photoresist. After the negative photoresist is exposed by ultraviolet light, an exposure area of the negative photoresist is hardened and can not be dissolved, and after development, a pattern formed in the negative photoresist is opposite to the pattern of a mask.
The photoresist can transfer the pattern of the preset cutting channel into the photoresist from the mask, so that the wafer group can be conveniently etched according to the cutting pattern; in addition, the photoresist remaining on the surface of the wafer group can protect materials below the photoresist in subsequent processes.
In the embodiment of the invention, the photoresist is exposed, the cutting pattern is directly formed on the surface of the wafer group, and then the wafer group is subjected to plasma etching cutting according to the cutting pattern, the cutting mode is simple, the width of a cutting mark generated by cutting in the plasma etching mode is narrow, the cutting quality is high, the number of chips which can be arranged on the wafer and the yield of the chips are improved, and the wafer group formed by a plurality of wafer layers can be easily cut. In addition, the cutting method provided by the embodiment of the invention does not need to focus the wafer, so that the wafer group can be cut smoothly even if the wafer group comprises the opaque layer.
In some embodiments of the invention, the step S30 includes:
etching the wafer group along the cutting pattern by using plasma;
or the like, or, alternatively,
cutting a first portion of the group of wafers along the cutting pattern using plasma etching; and applying pressure on the surface of the wafer group to separate the wafer group from a second part corresponding to the first part.
In the embodiment of the invention, the wafer group is cut by plasma etching, so that the damage to the edge of the chip can be reduced, and the quality of the chip is improved.
When the thickness of the wafer group is smaller, the depth required to be cut is smaller, and a mode of directly penetrating the wafer group along the cutting pattern by using plasma etching can be adopted. With the increase of the thickness of the wafer group, the time required for penetrating the wafer group only by using a plasma etching method is increased, and after the first part of the wafer is subjected to plasma etching cutting, the depth of the second part to be cut in the wafer group is deeper, so that the cutting difficulty is higher, and the cutting quality is difficult to ensure. Thus, a first portion of the wafer stack may be diced prior to applying pressure to the surface of the wafer stack to separate a second portion of the wafer stack. Compared with the method of continuously separating the second part through ion etching, the method has the advantages that the time for separating the second part by applying pressure is short, the operation is simpler, the process difficulty is reduced, and the cutting efficiency of the wafer group is improved.
In the embodiment of the invention, when the wafer group is cut along the cutting pattern, the wafer group can be directly etched and penetrated to form mutually separated parts; or, the whole wafer group may not be completely cut, but only the wafer layer with the preset thickness is cut along the cutting pattern, that is, the first part of the wafer group is cut, and after the incomplete cutting, the wafer group is still a whole body, but a cut mark with a certain depth is cut on one surface with the cutting pattern. After the wafer group is subjected to incomplete cutting, pressure can be applied to one surface of the wafer group, so that the wafer group is separated from the second part corresponding to the first part, and the wafer group is split to form mutually separated parts.
In some inventive embodiments, the method further comprises:
after the group of wafers is etched through with the plasma,
or the like, or, alternatively,
and separating different wafer layers after the wafer group is separated from a second part corresponding to the first part.
In an embodiment of the present invention, the method for separating the wafer layer may include: and irradiating the penetrated wafer group or the second part of the separated wafer group by adopting ultraviolet rays, reducing the acting force between each wafer layer, and separating the wafer layers to form the mutually separated single-layer chips.
By bonding the wafer layers and separating the wafer layers after cutting and separating the wafer group, the wafer layers can be cut simultaneously, and compared with the method for cutting after forming the mask layer on each wafer layer, the method provided by the embodiment saves the number of the mask layers in the cutting process, reduces the process cost and improves the cutting efficiency.
In some inventive embodiments, the gas from which the plasma is generated comprises at least one of: oxygen, nitrogen, chlorine-based gas, fluorine-based gas, inert gas.
In embodiments of the invention, the chlorine-based gas may comprise a gas comprising elemental chlorine, such as: chlorine, boron chloride, carbon chloride, and the like.
In an embodiment of the present invention, the fluorine-based gas may include a gas containing fluorine element, such as: carbon fluoride, nitrogen fluoride, hydrogen fluoride, fluorine gas, and the like.
In an embodiment of the present invention, the inert gas may include: helium, argon, and the like.
In the embodiment of the present invention, the gas for generating the plasma may be one gas or a mixed gas including a plurality of gases, and the gas for generating the plasma may be selected according to the material of the wafer layer to be cut. During etching, due to the fact that materials forming each wafer layer structure are different, corresponding gas can be selected for cutting according to different materials needing etching in a segmented etching mode during cutting. For example: when etching of oxide is desired, a fluorine-based gas, such as carbon tetrafluoride (CF), may be used4) The active fluorine bombards the oxide to form a product which is easy to volatilize, so that an etching effect is achieved, and the generated product is pumped out of the etching reactor through a vacuum system; when etching silicon, chlorine gas can be used, and silicon chloride generated by the reaction of the chlorine gas and the silicon is easy to volatilize and can be pumped out through a vacuum system. In addition, during the etching process, some other gas, such as argon, may be added, and the argon atoms with larger mass may bombard the wafer layer to achieve the effect of physical etching.
In some inventive embodiments, the method further comprises:
and after synchronously cutting at least two wafer layers in the wafer group along the cutting pattern, removing the mask layer on the surface of the wafer group.
In the embodiment of the invention, the mask layer can be removed by a wet etching method. The chemical etching agent used varies depending on the material of the mask layer. The photoresist may be removed, for example, with acetic acid; when the barrier material is silicon nitride, hot phosphoric acid may be used to remove the barrier material.
Several specific examples are provided below in connection with any of the embodiments described above:
example 1:
in a semiconductor device manufacturing process, a process of dividing a wafer having a plurality of device regions into individual chips by a plurality of dividing lines is included. The manufacturing process typically includes a grinding step for adjusting the thickness of the wafer and a dicing step for dicing the wafer along the dicing lines to obtain individual chips.
In one aspect, the wafer may be cut by mechanical cutting, such as by using diamond as a saw blade. However, the kerf of the mechanical dicing is relatively wide, typically 200 to 300 μm, so that when the chips are arranged on the wafer, the interval between adjacent chips is relatively wide, which limits the number of chips that can be arranged on the wafer and reduces the packaging density. In addition, heat and debris are generated when mechanical cutting is performed, requiring cooling and cleaning during the cutting process; and the vibration and stress generated in the mechanical cutting process easily cause the wafer to be broken, so that the yield of chips is reduced.
On the other hand, the wafer can be cut by adopting a laser cutting mode. However, when laser dicing a wafer, it is necessary to focus the laser on the surface or inside the wafer. If the wafer has the opaque layer, the laser cutting cannot be performed. If the multilayer wafer is cut, laser is required to focus each layer of wafer, the process difficulty is high, the time consumption is long, and the yield is low.
A method of manufacturing a semiconductor chip is described below with reference to fig. 2 to 5, the method including:
bonding the first wafer 11 and the second wafer 12 to form an electrical connection between the first wafer 11 and the second wafer 12, so as to form a wafer group 10;
thinning the surface of the first wafer 11 not in contact with the second wafer 12, and thinning the surface of the second wafer 12 not in contact with the first wafer 11;
forming a barrier layer (hard mask)21 on the thinned surface of the second wafer 12 without the circuit structure, and forming a Photoresist (PR)22 on the surface of the barrier layer 21 to form a mask layer 20;
exposing the photoresist 22 to form at least one cutting street 30 in the mask layer 20 to form a cutting pattern;
the wafer group 10 is etched in a segmented mode and synchronously cut by utilizing plasma along the cutting pattern, and the wafer group 10 is cut completely to form mutually separated parts;
the mask layer 20 is removed and the separated portions are cleaned to form a semiconductor chip.
In the embodiment of the invention, the limitation that a mechanical cutting method can only cut a straight line can be avoided by applying the plasma cutting method, and any pattern defined by the photomask can be cut at one time so as to obtain crystal grains with any shape and size, so that chip products with various shapes, sizes and even functions can be placed in the same wafer, and the surface area of the wafer is utilized to the maximum extent. This is of great significance when multiple project wafers are delivered.
Example 2:
for the wafer layer with the light shielding layer, the semiconductor chip can also be manufactured by using the method provided by the embodiment of the invention. Another semiconductor chip manufacturing method is described below with reference to fig. 6 to 9, the method including:
bonding the first wafer 11 and the second wafer 12, and bonding the third wafer 13 and the second wafer 12, so that the first wafer 11 and the second wafer 12, and the second wafer 12 and the third wafer 13 are electrically connected to form a wafer group 10; wherein, the second wafer 12 and the third wafer 13 both include an opaque layer 14;
thinning the surface of the first wafer 11 not in contact with the second wafer 12, and thinning the surface of the third wafer 13 not in contact with the second wafer 12;
forming a barrier layer (hard mask)21 on the thinned surface of the third wafer 13, and forming a Photoresist (PR)22 on the surface of the barrier layer 21 to form a mask layer 20;
exposing the photoresist 22 to form at least one cutting street 30 in the mask layer 20 to form a cutting pattern;
the wafer group 10 is etched in a segmented manner and synchronously cut by using the plasma along the cutting pattern until the wafer group 10 is cut to a preset depth, namely, the first part of the wafer group 10 is cut, at the moment, the wafer group 10 is still a complete whole, but a cut mark with the preset depth is formed in the wafer group 10;
applying pressure to the surface of the wafer group 10 without the mask layer, so that the wafer group 10 is separated from the second portion corresponding to the first portion, and the wafer group 10 is completely separated to form mutually separated portions;
the mask layer 20 is removed and the separated portions are cleaned to form a semiconductor chip.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor chip, comprising:
forming a wafer group formed by laminating at least two wafer layers;
forming a mask layer with a cutting pattern on at least one surface of the wafer group, wherein the cutting pattern comprises a first type of cutting channel for simultaneously cutting the at least two wafer layers and a second type of cutting channel for separately cutting one wafer layer;
synchronously cutting at least two wafer layers in the wafer group along the first type cutting channel; and/or cutting one wafer layer along the second type cutting channel.
2. The method of claim 1, wherein forming a mask layer having a cutting pattern on at least one surface of the wafer group comprises at least one of:
forming a first mask layer with the cutting pattern on a first surface of the wafer group;
forming a second mask layer with the cutting pattern on a second surface of the wafer group, wherein the second surface is the opposite surface of the first surface;
forming a mask layer with the first type of cutting channels on one surface of the wafer group, and forming another mask layer with the second type of cutting channels on the other surface of the wafer group; wherein the one surface is an opposite face of the other surface.
3. The method of manufacturing according to claim 1, wherein said simultaneously dicing at least two wafer layers of said wafer group along said first type of dicing lane comprises:
etching and penetrating the wafer group by using plasma along the first type cutting channel;
or the like, or, alternatively,
cutting a first part of the wafer group along the first type of cutting channel by using plasma etching; and applying pressure on the surface of the wafer group to separate the wafer group from a second part corresponding to the first part.
4. The manufacturing method according to claim 3, characterized by comprising:
after the plasma etch is used to penetrate the wafer set,
or the like, or, alternatively,
after the group of wafers is separated from the second portion corresponding to the first portion,
separating the different wafer layers.
5. The method of manufacturing according to claim 1, wherein said individually cutting one of said wafer layers along said second type of cutting lane comprises:
and etching one wafer layer in the wafer group, which is relatively close to the mask layer comprising the second cutting channel, along the second cutting channel by using plasma.
6. A manufacturing method according to claim 3 or 5, wherein the gas generating the plasma comprises at least one of: oxygen, nitrogen, chlorine-based gas, fluorine-based gas, inert gas.
7. The method of claim 1, wherein forming a mask layer having a cutting pattern on at least one surface of the wafer group comprises:
forming a barrier layer on at least one surface of the wafer group;
coating photoresist on the surface of the barrier layer;
and forming a cutting pattern on the photoresist.
8. The method of manufacturing of claim 7, wherein the material of the barrier layer comprises at least one of: amorphous carbon, silicon oxynitride, silicon nitride.
9. The method of manufacturing of claim 1, further comprising:
and after synchronously cutting at least two wafer layers in the wafer group along the first type cutting channel, removing the mask layer on the surface of the wafer group.
10. The method of manufacturing of claim 1, further comprising:
and processing at least one surface of the wafer group by adopting chemical mechanical polishing before forming a mask layer with a cutting pattern on at least one surface of the wafer group.
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| CN201910248959.XA CN109979879B (en) | 2019-03-29 | 2019-03-29 | Semiconductor chip manufacturing method |
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| WO2001009932A1 (en) * | 1999-07-30 | 2001-02-08 | Nippon Sheet Glass Co., Ltd. | Method of dicing semiconductor wafer into chips, and structure of groove formed in dicing area |
| JP2003249465A (en) * | 2002-02-26 | 2003-09-05 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
| JP2004327798A (en) * | 2003-04-25 | 2004-11-18 | Toshiba Corp | Method of manufacturing semiconductor device |
| US20130095581A1 (en) * | 2011-10-18 | 2013-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thick window layer led manufacture |
| US9048283B2 (en) * | 2012-06-05 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding systems and methods for semiconductor wafers |
| JP2014204004A (en) * | 2013-04-05 | 2014-10-27 | Hoya株式会社 | Substrate assembly, method of manufacturing substrate assembly, and method of manufacturing chip package |
| CN104979187A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for dividing wafer |
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