JP2008159985A - Method for manufacturing semiconductor chip - Google Patents

Method for manufacturing semiconductor chip Download PDF

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JP2008159985A
JP2008159985A JP2006349189A JP2006349189A JP2008159985A JP 2008159985 A JP2008159985 A JP 2008159985A JP 2006349189 A JP2006349189 A JP 2006349189A JP 2006349189 A JP2006349189 A JP 2006349189A JP 2008159985 A JP2008159985 A JP 2008159985A
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Prior art keywords
semiconductor wafer
resist film
semiconductor
plasma
dicing
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Japanese (ja)
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Kiyoshi Arita
潔 有田
Hiroshi Haji
宏 土師
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2006349189A priority Critical patent/JP2008159985A/en
Priority to TW96150218A priority patent/TW200830392A/en
Priority to PCT/JP2007/075368 priority patent/WO2008081968A1/en
Publication of JP2008159985A publication Critical patent/JP2008159985A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor chip, which reduces the time required for plasma dicing, without causing a semiconductor wafer to break or so while being transferred prior to the plasma dicing, and improves the production efficiency of semiconductor chips. <P>SOLUTION: A resist film 6 is formed on the back surface 1q of a ground semiconductor wafer 1, and then the portions 6a, 1b of margins for cutting 6a, 1b, 1c, 3a along a dicing line 2 are removed by a blade 13 which is the mechanical cutting means. The thickness t of the margin left, for cutting 1c in the thickness direction of the semiconductor wafer 1, is made small to a degree that enables the semiconductor wafer 1 to be transferred without trouble, and then all the margins left for cutting 1c, 3a are removed through plasma etching. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、回路形成面に複数の半導体素子が形成された半導体ウェハを分割して複数の半導体チップを得る半導体チップの製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor chip by dividing a semiconductor wafer having a plurality of semiconductor elements formed on a circuit forming surface to obtain a plurality of semiconductor chips.

近年、半導体ウェハを個々の半導体チップに分割する新たな技術として、切断時のダメージが少ないプラズマダイシングが注目されてきている。プラズマダイシングは、半導体ウェハの回路形成面とは反対側の面（裏面）にレジスト膜を形成し、そのレジスト膜に半導体素子同士を区分するダイシングラインに沿った溝（境界溝）を形成した後、その溝が形成されたレジスト膜をマスクとして半導体ウェハにプラズマエッチングを施して半導体ウェハを個々の半導体チップに切り分けるというものである。このプラズマダイシングでは、一般にはフォトリソグラフィー技術を用いてマスクを作成するが、このフォトリソグラフィー技術を用いたマスク形成はコスト高であるため、マスクを用いることなく機械的切断手段によって半導体ウェハの表面に溝を形成し、その溝からプラズマダイシングを進行させるマスクレスタイプのプラズマダイシングが提案されている（特許文献１）。
特開２００３−１９７５６９号公報 In recent years, plasma dicing with little damage during cutting has attracted attention as a new technique for dividing a semiconductor wafer into individual semiconductor chips. In plasma dicing, a resist film is formed on the surface (back surface) opposite to the circuit forming surface of the semiconductor wafer, and a groove (boundary groove) along a dicing line for separating semiconductor elements is formed in the resist film. The semiconductor wafer is subjected to plasma etching using the resist film in which the groove is formed as a mask to divide the semiconductor wafer into individual semiconductor chips. In this plasma dicing, a mask is generally formed using a photolithography technique. However, since the mask formation using this photolithography technique is expensive, it is applied to the surface of a semiconductor wafer by a mechanical cutting means without using a mask. Maskless type plasma dicing has been proposed in which grooves are formed and plasma dicing is advanced from the grooves (Patent Document 1).
JP 2003-197569 A

しかしながら、上記特許文献１に示された方法では、プラズマダイシングによるエッチングレートは通常２μｍ／分程度であるので、溝加工後の切り代領域の厚さが厚すぎるとダイシング工程に要する時間がかかりすぎて生産効率が悪くなるという問題点がある。一方、溝加工後の切り代領域の厚さが薄過ぎると半導体ウェハが破損し易くなり、その後の半導体ウェハの搬送（プラズマエッチングのための真空チャンバ内への搬送等）が困難になるという問題点がある。   However, in the method disclosed in Patent Document 1, since the etching rate by plasma dicing is usually about 2 μm / min, if the thickness of the cutting margin region after the groove processing is too thick, it takes too much time for the dicing process. There is a problem that production efficiency deteriorates. On the other hand, if the thickness of the cutting allowance region after the groove processing is too thin, the semiconductor wafer is likely to be damaged, and the subsequent transport of the semiconductor wafer (such as transport into a vacuum chamber for plasma etching) becomes difficult. There is a point.

そこで本発明は、プラズマダイシング前の搬送時に半導体ウェハを破損等させることなく、プラズマダイシングに要する時間を短縮させて、半導体チップの生産効率を向上させることができる半導体チップの製造方法を提供することを目的とする。   Accordingly, the present invention provides a method for manufacturing a semiconductor chip that can reduce the time required for plasma dicing and improve the production efficiency of the semiconductor chip without damaging the semiconductor wafer during transport before plasma dicing. With the goal.

請求項１に記載の半導体チップの製造方法は、回路形成面に複数の半導体素子が形成された半導体ウェハを、半導体素子同士を区分するダイシングラインに沿って分割して複数の半導体チップを得る半導体チップの製造方法であって、半導体ウェハの回路形成面とは反対側の裏面を研削する裏面研削工程と、研削された半導体ウェハの裏面にレジスト膜を形成するレジスト膜形成工程と、ダイシングラインに沿ったレジスト膜の厚さ方向の切り代領域の全部及び半導体ウェハの厚さ方向の切り代領域のレジスト膜側の一部を機械的切断手段によって除去する溝加工工程と、レジスト膜をマスクとして半導体ウェハにプラズマエッチングを施し、ダイシングラインに沿った半導体ウェハの厚さ方向の残りの切り代領域の全部を除去するプラズマダイシング工程と、プラズマダイシング工程の後、半導体ウェハからレジスト膜を除去するレジスト膜除去工程とを含む。   The semiconductor chip manufacturing method according to claim 1, wherein a semiconductor wafer in which a plurality of semiconductor elements are formed on a circuit forming surface is divided along a dicing line that separates the semiconductor elements to obtain a plurality of semiconductor chips. A chip manufacturing method comprising: a back grinding process for grinding a back surface opposite to a circuit forming surface of a semiconductor wafer; a resist film forming process for forming a resist film on the ground semiconductor wafer; and a dicing line A groove processing step for removing all of the cut margin region in the resist film thickness direction along the resist film and a part of the cut margin region in the thickness direction of the semiconductor wafer on the resist film side by a mechanical cutting means, and using the resist film as a mask Plasma that performs plasma etching on a semiconductor wafer and removes all remaining cutting margin areas in the thickness direction of the semiconductor wafer along the dicing line And Ishingu step, after the plasma dicing process, and a resist film removing step of removing the resist film from a semiconductor wafer.

請求項２に記載の半導体チップの製造方法は、請求項１に記載の半導体チップの製造方法において、溝加工工程終了後のダイシングラインに沿った半導体ウェハの厚さ方向の残りの切り代領域の厚さが５０〜２００μｍである。   The method for manufacturing a semiconductor chip according to claim 2 is the method for manufacturing a semiconductor chip according to claim 1, wherein the remaining cutting margin region in the thickness direction of the semiconductor wafer along the dicing line after the grooving step is completed. The thickness is 50 to 200 μm.

本発明では、研削された半導体ウェハの裏面にレジスト膜を形成した後、ダイシングラインに沿った切り代領域の一部を機械的切断手段によって除去し、半導体ウェハの厚さ方向の残りの切り代領域の厚さを半導体ウェハの搬送に支障のない程度にまで薄くした後、残りの切り代領域の全部をプラズマエッチングによって除去する。このため、切り代領域の全てをプラズマエッチングによって除去して半導体ウェハを切り分ける場合よりもダイシングに要する時間を大幅に短縮させることができる。従って本発明によれば、プラズマダイシング前の搬送時に半導体ウェハを破損等させることなく、プラズマダイシングに要する時間を短縮させて、半導体チップの生産効率を大きく向上させることができる。   In the present invention, after forming a resist film on the back surface of the ground semiconductor wafer, a part of the cutting margin region along the dicing line is removed by a mechanical cutting means, and the remaining cutting margin in the thickness direction of the semiconductor wafer is removed. After reducing the thickness of the region to such an extent that does not hinder the transfer of the semiconductor wafer, the entire remaining cutting margin region is removed by plasma etching. For this reason, the time required for dicing can be significantly shortened compared to the case where the entire cutting margin region is removed by plasma etching to cut the semiconductor wafer. Therefore, according to the present invention, the semiconductor wafer production efficiency can be greatly improved by reducing the time required for plasma dicing without damaging the semiconductor wafer during transport before plasma dicing.

また、半導体ウェハにレジスト膜を形成したうえでプラズマエッチングを行うので、プラズマ雰囲気中の分解したラジカルが半導体ウェハの機械的切除部の近傍に集中してエッチングレートが向上し、高速なプラズマエッチングが実現できる。しかも、レジスト膜のレジストパターンは機械的切断手段による切り代除去とともに形成されるので、高価なフォトリソグラフィーは不要である。   In addition, since plasma etching is performed after forming a resist film on the semiconductor wafer, the decomposed radicals in the plasma atmosphere are concentrated in the vicinity of the mechanically cut portion of the semiconductor wafer, improving the etching rate and enabling high-speed plasma etching. realizable. Moreover, since the resist pattern of the resist film is formed together with the removal of the cutting allowance by the mechanical cutting means, expensive photolithography is not necessary.

また、半導体ウェハを半導体チップに切り分ける際の最終的な切断は切断時のダメージの小さいプラズマエッチングによって行われるので、レジスト膜が形成される面とは反対側の面（回路形成面）に脆弱な低誘電率層を有する半導体ウェハを切り分けるときには、本製造方法が特に有効である。   Further, since the final cutting when the semiconductor wafer is cut into semiconductor chips is performed by plasma etching with little damage at the time of cutting, it is vulnerable to a surface (circuit forming surface) opposite to the surface on which the resist film is formed. This manufacturing method is particularly effective when cutting a semiconductor wafer having a low dielectric constant layer.

以下、図面を参照して本発明の実施の形態について説明する。図１は本発明の一実施の形態において使用するブレード切断装置の斜視図、図２は本発明の一実施の形態において使用するプラズマ処理装置の断面図、図３は本発明の一実施の形態における半導体チップの製造方法の工程手順を示すフローチャート、図４、図５及び図６は本発明の一実施の形態における半導体チップの製造方法の工程説明図である。   Embodiments of the present invention will be described below with reference to the drawings. 1 is a perspective view of a blade cutting device used in an embodiment of the present invention, FIG. 2 is a cross-sectional view of a plasma processing apparatus used in an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4, FIG. 5 and FIG. 6 are process explanatory views of the semiconductor chip manufacturing method according to the embodiment of the present invention.

先ず、図１及び図２を用いて本発明の一実施の形態において使用するブレード切断装置１０及びプラズマ処理装置３０の構成について説明する。   First, the configuration of the blade cutting apparatus 10 and the plasma processing apparatus 30 used in the embodiment of the present invention will be described with reference to FIGS. 1 and 2.

図１において、ブレード切断装置１０は加工対象である半導体ウェハ１を水平姿勢に保持するウェハ保持部１１、ウェハ保持部１１の上方に移動自在に設けられた移動プレート１２、移動プレート１２に固定されてブレード１３を水平な回転軸（回転軸の延びる方向をＸ軸とする）まわりに回転自在に保持するブレード保持部１４、移動プレート１２に固定されたカメラ１５のほか、移動プレート１２を移動させるブレード移動機構１６、ブレード１３の回転駆動を行うブレード駆動機構１７、ウェハ保持部１１を移動（回転を含む）させるウェハ移動機構１８、これらの機構１６，１７，１８の作動制御を行う制御部１９、カメラ１５の撮像画像から半導体ウェハ１の位置認識を行う認識部２０、制御部１９に操作信号・入力信号を与える操作・入力部２１、制御部１９と繋がるワークデータ記憶部２２等を有して成る。   In FIG. 1, a blade cutting device 10 is fixed to a wafer holding unit 11 that holds a semiconductor wafer 1 to be processed in a horizontal posture, a moving plate 12 that is movably provided above the wafer holding unit 11, and a moving plate 12. In addition to the blade holder 14 that holds the blade 13 around a horizontal rotation axis (the X axis is the direction in which the rotation axis extends), the camera 15 that is fixed to the moving plate 12, the moving plate 12 is moved. A blade moving mechanism 16, a blade driving mechanism 17 that rotates the blade 13, a wafer moving mechanism 18 that moves (including rotation) the wafer holding unit 11, and a control unit 19 that controls the operation of these mechanisms 16, 17, 18. An operation signal / input signal is given to the recognition unit 20 for recognizing the position of the semiconductor wafer 1 from the captured image of the camera 15 and the control unit 19. Comprising a work-input unit 21, such as a work data storage unit 22 connected to the control unit 19.

ウェハ保持部１１は上面に半導体ウェハ１を固定保持する真空チャック等の固定保持具を有しており、半導体ウェハ１はこの固定保持具によりブレード１３による溝加工が行われる面を上に向けて固定保持される。ブレード移動機構１６は制御部１９より制御されて移動プレート１２をＸ軸方向及びＺ軸方向（上下方向）へ移動させ、移動プレート１２に固定されたブレード保持部１４及びカメラ１５を半導体ウェハ１の上方において移動させる。ブレード駆動機構１７は制御部１９より制御されてブレード１３を回転軸まわりに回転駆動し、ウェハ移動機構１８は制御部１９より制御されてウェハ保持部１１をＹ軸方向（Ｘ軸と直交する水平面内方向）に移動及びＺ軸と平行な上下回転軸まわりに回転させる。カメラ１５は直下に位置する半導体ウェハ１を赤外光により撮像する。認識部２０はカ
メラ１５の撮像画像から半導体ウェハ１の位置認識を行い、その結果得られた半導体ウェハ１の位置情報を制御部１９へ送信する。 The wafer holding unit 11 has a fixed holding tool such as a vacuum chuck for fixing and holding the semiconductor wafer 1 on the upper surface, and the semiconductor wafer 1 faces the surface on which the groove processing by the blade 13 is performed by the fixed holding tool upward. It is held fixed. The blade moving mechanism 16 is controlled by the control unit 19 to move the moving plate 12 in the X-axis direction and the Z-axis direction (vertical direction), and the blade holding unit 14 and the camera 15 fixed to the moving plate 12 are moved to the semiconductor wafer 1. Move upward. The blade driving mechanism 17 is controlled by the control unit 19 to rotate the blade 13 around the rotation axis, and the wafer moving mechanism 18 is controlled by the control unit 19 to move the wafer holding unit 11 in the Y-axis direction (horizontal plane orthogonal to the X axis). Move inward) and rotate around a vertical rotation axis parallel to the Z axis. The camera 15 images the semiconductor wafer 1 located immediately below with infrared light. The recognition unit 20 recognizes the position of the semiconductor wafer 1 from the captured image of the camera 15 and transmits the position information of the semiconductor wafer 1 obtained as a result to the control unit 19.

制御部１９は、認識部２０から送信された半導体ウェハ１の位置情報に基づいて半導体ウェハ１とブレード１３との位置関係を把握する。操作・入力部２１はオペレータの操作に応じ、各種入力信号を制御部１９に与える。ワークデータ記憶部２２には半導体ウェハ１を個々の半導体チップに切り分ける際の区分線となる格子状のダイシングライン２のデータが記憶されており、制御部１９はこのワークデータ記憶部２２に記憶されたダイシングライン２に沿ってブレード１３が半導体ウェハ１に対して相対的に移動するようにブレード移動機構１６及びウェハ移動機構１８の作動制御を行う。   The control unit 19 grasps the positional relationship between the semiconductor wafer 1 and the blade 13 based on the positional information of the semiconductor wafer 1 transmitted from the recognition unit 20. The operation / input unit 21 gives various input signals to the control unit 19 according to the operation of the operator. The work data storage unit 22 stores data of a lattice-shaped dicing line 2 that is a dividing line when the semiconductor wafer 1 is cut into individual semiconductor chips, and the control unit 19 stores the data in the work data storage unit 22. The blade movement mechanism 16 and the wafer movement mechanism 18 are controlled so that the blade 13 moves relative to the semiconductor wafer 1 along the dicing line 2.

図２において、プラズマ処理装置３０は真空チャンバ３１、真空チャンバ３１内に設けられた下部電極３２と上部電極３３、下部電極３２に高周波電圧を印加する高周波電源部３４、冷媒を下部電極３２内に循環させる冷却ユニット３５、上部電極３３内から真空チャンバ３１の外部に延び、真空チャンバ３１の外部において二股に分かれたガス供給路３６、二股に分かれたガス供給路３６の一方側の分岐路（第１分岐路３６ａとする）に接続された酸素ガス供給部３７、二股に分かれたガス供給路３６の他方側の分岐路（第２分岐路３６ｂとする）に接続されたフッ素系ガス供給部３８、第１分岐路３６ａ中に介装された第１開閉弁３９及び第１流量制御弁４０、第２分岐路３６ｂ中に介装された第２開閉弁４１及び第２流量制御弁４２から成っている。   In FIG. 2, the plasma processing apparatus 30 includes a vacuum chamber 31, a lower electrode 32 and an upper electrode 33 provided in the vacuum chamber 31, a high-frequency power supply unit 34 for applying a high-frequency voltage to the lower electrode 32, and a refrigerant in the lower electrode 32. The cooling unit 35 to be circulated, the inside of the upper electrode 33, extends to the outside of the vacuum chamber 31, and is divided into a bifurcated gas supply path 36 and a bifurcated gas supply path 36 on one side of the bifurcated gas supply path 36. An oxygen gas supply unit 37 connected to the first branch path 36a, and a fluorine-based gas supply section 38 connected to the other branch path (referred to as the second branch path 36b) of the bifurcated gas supply path 36. The first on-off valve 39 and the first flow control valve 40 interposed in the first branch path 36a, and the second on-off valve 41 and the second flow control valve 42 interposed in the second branch path 36b. It is made.

真空チャンバ３１の内部は半導体ウェハ１に対してプラズマ処理を行うための密閉空間となっている。下部電極３２は真空チャンバ３１内において半導体ウェハ１の保持面を上にして設けられており、上部電極３３はその下面が下部電極３２の上面と対向するように設けられている。   The inside of the vacuum chamber 31 is a sealed space for performing plasma processing on the semiconductor wafer 1. The lower electrode 32 is provided in the vacuum chamber 31 with the holding surface of the semiconductor wafer 1 facing upward, and the upper electrode 33 is provided such that the lower surface thereof faces the upper surface of the lower electrode 32.

下部電極３２の上面には真空チャックや静電吸引機構等から成るウェハ保持機構（図示せず）と電気絶縁性材料から成るリング状のフレーム３２ａが設けられており、半導体ウェハ１はプラズマ処理が施される面を上に向け、フレーム３２ａによって周囲が囲まれるように支持されて、ウェハ保持機構によって下部電極３２の上面に固定される。   On the upper surface of the lower electrode 32, a wafer holding mechanism (not shown) composed of a vacuum chuck, an electrostatic suction mechanism and the like and a ring-shaped frame 32a made of an electrically insulating material are provided. The semiconductor wafer 1 is subjected to plasma processing. The surface to be applied is faced up, supported by the frame 32a so as to be surrounded by the frame 32a, and fixed to the upper surface of the lower electrode 32 by the wafer holding mechanism.

酸素ガス供給部３７内には酸素ガス（酸素を主成分とする混合ガスであってもよい）が封入されており、その酸素ガスは、第１開閉弁３９が開弁されているとき（第２開閉弁４１は閉弁される）、第１分岐路３６ａ及びガス供給路３６を介して上部電極３３に供給される。酸素ガス供給部３７から上部電極３３に供給される酸素ガスの流量は、第１流量制御弁４０の開度調節によって行う。また、フッ素系ガス供給部３８内には例えば六弗化硫黄（ＳＦ６）等のフッ素系ガスが封入されており、そのフッ素系ガスは、第２開閉弁４１が開弁されているとき（第１開閉弁３９は閉弁される）、第２分岐路３６ｂ及びガス供給路３６を介して上部電極３３に供給される。フッ素系ガス供給部３８から上部電極３３に供給されるフッ素系ガスの流量は、第２流量制御弁４２の開度調節によって行う。 An oxygen gas (may be a mixed gas containing oxygen as a main component) is sealed in the oxygen gas supply unit 37, and the oxygen gas is supplied when the first on-off valve 39 is opened (first 2 on-off valve 41 is closed), and is supplied to upper electrode 33 via first branch path 36a and gas supply path 36. The flow rate of the oxygen gas supplied from the oxygen gas supply unit 37 to the upper electrode 33 is adjusted by adjusting the opening of the first flow control valve 40. Further, a fluorine-based gas such as sulfur hexafluoride (SF 6 ) is sealed in the fluorine-based gas supply unit 38, and the fluorine-based gas is used when the second on-off valve 41 is opened ( The first on-off valve 39 is closed), and is supplied to the upper electrode 33 via the second branch path 36 b and the gas supply path 36. The flow rate of the fluorine-based gas supplied from the fluorine-based gas supply unit 38 to the upper electrode 33 is adjusted by adjusting the opening of the second flow rate control valve 42.

上部電極３３の下面には平板状の多孔質プレート３３ａが設けられており、ガス供給路３６を介して供給された酸素ガスやフッ素系ガスは、この多孔質プレート３３ａを介して下部電極３２の上面に均一に吹き付けられる。   A flat plate-like porous plate 33a is provided on the lower surface of the upper electrode 33, and oxygen gas and fluorine-based gas supplied through the gas supply path 36 are supplied to the lower electrode 32 through the porous plate 33a. The top surface is evenly sprayed.

次に、図３のフローチャート及び図４、図５、図６の工程説明図を参照して半導体チップの製造方法を説明する。半導体ウェハ１の回路形成面１ｐには低誘電率層３が設けられており、回路形成面１ｐには低誘電率層３を絶縁層として複数の半導体素子４が形成されている（図４（ａ））。   Next, a method for manufacturing a semiconductor chip will be described with reference to the flowchart in FIG. 3 and the process explanatory diagrams in FIGS. 4, 5, and 6. A low dielectric constant layer 3 is provided on the circuit formation surface 1p of the semiconductor wafer 1, and a plurality of semiconductor elements 4 are formed on the circuit formation surface 1p using the low dielectric constant layer 3 as an insulating layer (FIG. 4 ( a)).

このように、回路形成面１ｐに複数の半導体素子４が形成された半導体ウェハ１を、半導体素子４同士を区分するダイシングライン２に沿って分割して複数の半導体チップ１′（図６（ｄ））を得るには、先ず図４（ｂ）に示すように、半導体ウェハ１の回路形成面１ｐに粘着質のシート状の保護テープ（例えばＵＶテープ）５を貼り付ける（図３に示す保護テープ貼付工程Ｓ１）。   In this way, the semiconductor wafer 1 on which the plurality of semiconductor elements 4 are formed on the circuit forming surface 1p is divided along the dicing line 2 that separates the semiconductor elements 4 from each other, and a plurality of semiconductor chips 1 ′ (FIG. 6 (d) 4), first, as shown in FIG. 4B, an adhesive sheet-like protective tape (for example, UV tape) 5 is attached to the circuit forming surface 1p of the semiconductor wafer 1 (the protection shown in FIG. 3). Tape application process S1).

保護テープ貼付工程Ｓ１が終了したら、図４（ｃ）に示すように、裏面研削装置５０を用いて半導体ウェハ１の回路形成面１ｐとは反対側の裏面１ｑを研削する（図３に示す裏面研削工程Ｓ２）。   When the protective tape sticking step S1 is completed, as shown in FIG. 4C, the back surface 1q opposite to the circuit forming surface 1p of the semiconductor wafer 1 is ground using the back surface grinding device 50 (the back surface shown in FIG. 3). Grinding step S2).

裏面研削装置５０は回転テーブル５１とこの回転テーブル５１の上方に設けられた回転砥石５２から成り、回転テーブル５１の上面には半導体ウェハ１が裏面１ｑを上方に向けて載置される。回転テーブル５１に半導体ウェハ１が載置されたら、回転砥石５２を半導体ウェハ１の裏面１ｑに上方から押し付けるとともに（図４（ｃ）中に示す矢印Ａ）、回転テーブル５１と回転砥石５２をそれぞれ上下軸まわりに回転させつつ（図４（ｃ）中に示す矢印Ｂ，Ｃ）、回転砥石５２を水平面内で揺動させる（図４（ｃ）中に示す矢印Ｄ）。これにより半導体ウェハ１の裏面１ｑは研削され、半導体ウェハ１は６００〜１５０μｍ程度の厚さにまで薄化される（図４（ｄ））。なお、裏面研削後の半導体ウェハ１の裏面１ｑには１μｍ程度の深さのダメージ層（単結晶ではなくなっている層）ができるので、裏面研削装置５０から取り外した半導体ウェハ１の裏面１ｑにポリッシングやプラズマエッチングを施してこのダメージ層を除去するようにする。   The back surface grinding device 50 includes a rotary table 51 and a rotary grindstone 52 provided above the rotary table 51, and the semiconductor wafer 1 is placed on the upper surface of the rotary table 51 with the back surface 1 q facing upward. When the semiconductor wafer 1 is placed on the rotary table 51, the rotary grindstone 52 is pressed against the back surface 1q of the semiconductor wafer 1 from above (arrow A shown in FIG. 4C), and the rotary table 51 and the rotary grindstone 52 are respectively moved. While rotating around the vertical axis (arrows B and C shown in FIG. 4C), the rotating grindstone 52 is swung in a horizontal plane (arrow D shown in FIG. 4C). Thereby, the back surface 1q of the semiconductor wafer 1 is ground, and the semiconductor wafer 1 is thinned to a thickness of about 600 to 150 μm (FIG. 4D). Since a damaged layer (a layer that is not a single crystal) having a depth of about 1 μm is formed on the back surface 1q of the semiconductor wafer 1 after the back surface grinding, polishing is performed on the back surface 1q of the semiconductor wafer 1 removed from the back surface grinding apparatus 50. The damaged layer is removed by plasma etching.

裏面研削工程Ｓ２が終了したら、図５（ａ）に示すように、半導体ウェハ１の裏面１ｑに感光性のレジスト膜６を形成する（図３に示すレジスト膜形成工程Ｓ３）。このレジスト膜６は、後に行うプラズマダイシング工程Ｓ６においてマスクとして機能するものである。   When the back surface grinding step S2 is completed, as shown in FIG. 5A, a photosensitive resist film 6 is formed on the back surface 1q of the semiconductor wafer 1 (resist film forming step S3 shown in FIG. 3). This resist film 6 functions as a mask in a plasma dicing step S6 to be performed later.

レジスト膜形成工程Ｓ３が終了したら、半導体ウェハ１をブレード切断装置１０のウェハ保持部１１に設置する。このとき半導体ウェハ１は、レジスト膜６が形成された裏面１ｑが上を向くようにする。そして、図５（ｂ），（ｃ）に示すように、ダイシングライン２に沿ったレジスト膜６の厚さ方向の切り代領域６ａの全部と、ダイシングライン２に沿った半導体ウェハ１の厚さ方向の切り代領域１ａのレジスト膜６側の一部１ｂを回転させたブレード１３によって研削して除去する（図３に示す溝加工工程Ｓ４）。これにより半導体ウェハ１は、ダイシングライン２に沿った切り代領域１ａのうち、低誘電率層３側に残った切り代領域１ｃによって半導体ウェハ１の面内方向に繋がった状態となる。   When the resist film forming step S3 is completed, the semiconductor wafer 1 is set on the wafer holding unit 11 of the blade cutting device 10. At this time, the semiconductor wafer 1 is set so that the back surface 1q on which the resist film 6 is formed faces upward. Then, as shown in FIGS. 5B and 5C, the entire cutting margin region 6 a in the thickness direction of the resist film 6 along the dicing line 2 and the thickness of the semiconductor wafer 1 along the dicing line 2. A portion 1b on the resist film 6 side of the direction margin region 1a is removed by grinding with the rotated blade 13 (groove processing step S4 shown in FIG. 3). As a result, the semiconductor wafer 1 is connected in the in-plane direction of the semiconductor wafer 1 by the cutting margin region 1c remaining on the low dielectric constant layer 3 side in the cutting margin region 1a along the dicing line 2.

ここで、前述のようにワークデータ記憶部２２にはダイシングライン２のデータが記憶されており、制御部１９はこのワークデータ記憶部２２に記憶されたダイシングライン２のデータ及びカメラ１５の撮像によって得られる半導体ウェハ１の位置に基づいて、移動プレート１２及びウェハ保持部１１を（すなわちブレード１３及び半導体ウェハ１を）移動させる。回転させたブレード１３を半導体ウェハ１に接触させた状態でウェハ保持部１１をＹ軸方向に移動させることによってＹ軸に平行な１つのダイシングライン２に沿った溝加工を行うことができるので、この溝加工を、移動プレート１２のＸ軸方向へのステップ状の移動と、ウェハ保持部１１をＺ軸まわりに９０度回転させる移動とを組み合わせることにより、格子状に配置された全てのダイシングライン２に沿った溝加工を行うことができる。   Here, as described above, the data of the dicing line 2 is stored in the work data storage unit 22, and the control unit 19 uses the data of the dicing line 2 stored in the work data storage unit 22 and the imaging of the camera 15. Based on the position of the obtained semiconductor wafer 1, the moving plate 12 and the wafer holding part 11 (namely, the blade 13 and the semiconductor wafer 1) are moved. Since the wafer holding unit 11 is moved in the Y-axis direction while the rotated blade 13 is in contact with the semiconductor wafer 1, groove processing along one dicing line 2 parallel to the Y-axis can be performed. All the dicing lines arranged in a grid pattern by combining this groove processing with a step-like movement of the moving plate 12 in the X-axis direction and a movement of rotating the wafer holder 11 about 90 degrees around the Z-axis. The groove processing along 2 can be performed.

上記溝加工工程Ｓ４では、ダイシングライン２に沿った半導体ウェハ１の厚さ方向の残りの切り代領域１ｃの厚さｔ（図５（ｃ）参照）が５０〜２００μｍ程度になるようにする。５０〜２００μｍという値は、この溝加工工程Ｓ４の後、次に行うウェハ搬入工程Ｓ
５において半導体ウェハ１を真空チャンバ３１に搬入する過程等において支障のない十分な強度を確保し得る値である。この範囲の値よりも厚さが小さいと、搬送中の半導体ウェハ１を破損等させてしまうおそれがあり、この範囲の値よりも厚さが大きいと、後に行うプラズマエッチング（プラズマダイシング工程Ｓ６）においてプラズマエッチングに要する時間が長くなってしまう不都合がある。なお、この溝加工工程Ｓ４によって、ダイシングライン２に沿ったレジスト膜６が除去されるので、レジスト膜６には後に行うプラズマエッチングで必要となるレジストパターンが形成されたことになる。 In the groove processing step S4, the thickness t (see FIG. 5C) of the remaining cutting margin region 1c in the thickness direction of the semiconductor wafer 1 along the dicing line 2 is set to about 50 to 200 μm. The value of 50 to 200 μm indicates the wafer carrying-in process S to be performed next after the groove processing process S4.
5 is a value that can ensure sufficient strength without any trouble in the process of carrying the semiconductor wafer 1 into the vacuum chamber 31. If the thickness is smaller than the value in this range, the semiconductor wafer 1 being transferred may be damaged. If the thickness is larger than the value in this range, plasma etching performed later (plasma dicing step S6). However, there is a disadvantage that the time required for plasma etching becomes long. In addition, since the resist film 6 along the dicing line 2 is removed by this groove processing step S4, a resist pattern necessary for plasma etching performed later is formed on the resist film 6.

溝加工工程Ｓ４が終了したら、半導体ウェハ１をブレード切断装置１０のウェハ保持部１１から取り外し、プラズマ処理装置３０の真空チャンバ３１内に搬入して、半導体ウェハ１を下部電極３２の上面に固定する（図３におけるウェハ搬入工程Ｓ５）。このとき、半導体ウェハ１は、レジスト膜６が形成された裏面１ｑが上方に向くようにする。   When the grooving step S4 is completed, the semiconductor wafer 1 is removed from the wafer holder 11 of the blade cutting device 10 and carried into the vacuum chamber 31 of the plasma processing apparatus 30 to fix the semiconductor wafer 1 to the upper surface of the lower electrode 32. (Wafer carrying-in process S5 in FIG. 3). At this time, the semiconductor wafer 1 is set so that the back surface 1q on which the resist film 6 is formed faces upward.

ウェハ搬入工程Ｓ５が終了したら、レジスト膜６をマスクとして半導体ウェハ１にフッ素系ガスによるプラズマエッチングを施す（図３におけるプラズマダイシング工程Ｓ６）。   When the wafer carry-in step S5 is completed, plasma etching with a fluorine-based gas is performed on the semiconductor wafer 1 using the resist film 6 as a mask (plasma dicing step S6 in FIG. 3).

このプラズマダイシング工程Ｓ６では、先ず、第１開閉弁３９を閉じた状態で第２開閉弁４１を開き、フッ素系ガス供給部３８から上部電極３３へフッ素系ガスを供給させる。これにより上部電極３３から多孔質プレート３３ａを介して半導体ウェハ１の上面にフッ素系ガスが吹き付けられる。この状態で高周波電源部３４を駆動して下部電極３２に高周波電圧を印加すると、下部電極３２と上部電極３３の間にフッ素系ガスのプラズマＰｆが発生する（図６（ａ））。   In the plasma dicing step S6, first, the second on-off valve 41 is opened with the first on-off valve 39 closed, and the fluorine-based gas is supplied from the fluorine-based gas supply unit 38 to the upper electrode 33. As a result, fluorine gas is blown from the upper electrode 33 onto the upper surface of the semiconductor wafer 1 through the porous plate 33a. When the high frequency power supply 34 is driven in this state and a high frequency voltage is applied to the lower electrode 32, a fluorine-based gas plasma Pf is generated between the lower electrode 32 and the upper electrode 33 (FIG. 6A).

発生したフッ素系ガスのプラズマＰｆは、溝加工工程Ｓ４においてレジスト膜６が除去された部分から半導体ウェハ１をエッチングするので、ダイシングライン２に沿った半導体ウェハ１の厚さ方向の残りの切り代領域（半導体ウェハ１の厚さ方向の切り代領域１ｃ及び低誘電率層３の厚さ方向の切り代領域３ａ）の全部が除去され、半導体ウェハ１はダイシングライン２に沿って一括して切り分けられてレジスト膜６付きの個々の半導体チップ１′に分割される（図６（ｂ））。なお、このフッ素系ガスのプラズマＰｆにより半導体ウェハ１のエッチングを行っている間は、冷却ユニット３５を駆動して冷媒を下部電極３２内に循環させ、プラズマの熱によって半導体ウェハ１が昇温するのを防止するようにする。   The generated fluorine-based gas plasma Pf etches the semiconductor wafer 1 from the portion where the resist film 6 has been removed in the groove processing step S4, so that the remaining cutting allowance in the thickness direction of the semiconductor wafer 1 along the dicing line 2 is obtained. All of the regions (the cutting margin region 1c in the thickness direction of the semiconductor wafer 1 and the cutting margin region 3a in the thickness direction of the low dielectric constant layer 3) are removed, and the semiconductor wafer 1 is collectively cut along the dicing line 2. Then, it is divided into individual semiconductor chips 1 ′ with a resist film 6 (FIG. 6B). During the etching of the semiconductor wafer 1 by the plasma Pf of the fluorine-based gas, the cooling unit 35 is driven to circulate the coolant in the lower electrode 32, and the temperature of the semiconductor wafer 1 is raised by the heat of the plasma. To prevent it.

プラズマダイシング工程Ｓ６が終了したら、続いて、真空チャンバ３１内に酸素ガスのプラズマＰｏを発生させて、半導体ウェハ１（切り分けられた各半導体チップ１′が保護テープ５によって繋がった状態のもの）の上面（裏面１ｑ）に残っているレジスト膜６の灰化除去を行う（図３に示すレジスト膜除去工程Ｓ７）。   When the plasma dicing step S6 is completed, an oxygen gas plasma Po is subsequently generated in the vacuum chamber 31, and the semiconductor wafer 1 (in a state where the separated semiconductor chips 1 'are connected by the protective tape 5). The resist film 6 remaining on the upper surface (back surface 1q) is removed by ashing (resist film removal step S7 shown in FIG. 3).

これには先ず、プラズマ処理装置３０の第２開閉弁４１を閉じた状態で第１開閉弁３９を開き、酸素ガス供給部３７から上部電極３３へ酸素ガスを供給させる。これにより上部電極３３から多孔質プレート３３ａを介して半導体ウェハ１の上面に酸素ガスが吹き付けられる。この状態で高周波電源部３４を駆動して下部電極３２に高周波電圧を印加すると、下部電極３２と上部電極３３の間に酸素ガスのプラズマＰｏが発生する（図６（ｃ））。この酸素ガスのプラズマＰｏは有機物であるレジスト膜６を灰化するので、半導体ウェハ１の（個々の半導体チップ１′の）裏面１ｑからレジスト膜６が除去される（図６（ｄ））。なお、このレジスト膜除去工程Ｓ７において、酸素ガスのプラズマＰｏによりレジスト膜６の灰化除去を行っている間は、冷却ユニット３５を駆動して冷媒を下部電極３２内に循環させ、プラズマの熱によって半導体ウェハ１が昇温するのを防止するようにする。   First, the first on-off valve 39 is opened with the second on-off valve 41 of the plasma processing apparatus 30 closed, and oxygen gas is supplied from the oxygen gas supply unit 37 to the upper electrode 33. As a result, oxygen gas is blown from the upper electrode 33 onto the upper surface of the semiconductor wafer 1 through the porous plate 33a. When the high frequency power supply 34 is driven in this state and a high frequency voltage is applied to the lower electrode 32, a plasma Po of oxygen gas is generated between the lower electrode 32 and the upper electrode 33 (FIG. 6C). Since this oxygen gas plasma Po ashes the organic resist film 6, the resist film 6 is removed from the back surface 1 q of the semiconductor wafer 1 (individual semiconductor chip 1 ′) (FIG. 6D). In the resist film removing step S7, while the resist film 6 is incinerated and removed by the plasma Po of oxygen gas, the cooling unit 35 is driven to circulate the refrigerant in the lower electrode 32, and the heat of the plasma. This prevents the temperature of the semiconductor wafer 1 from rising.

レジスト膜６が完全に灰化除去されたら、真空チャンバ３１内から半導体ウェハ１（切り分けられた半導体チップ１′がＵＶテープ３によって繋がった状態のもの）を搬出する（図３に示すウェハ搬出工程Ｓ８）。   When the resist film 6 is completely ashed and removed, the semiconductor wafer 1 (with the cut semiconductor chips 1 'connected by the UV tape 3) is unloaded from the vacuum chamber 31 (wafer unloading step shown in FIG. 3). S8).

これにより半導体チップ１′の製造は終了し、半導体ウェハ１を真空チャンバ３１から搬出した後、半導体ウェハ１の回路形成面１ｐに貼り付けられた保護テープ５を引き伸ばすと、切り分けられた半導体チップ１′を互いに引き離した状態にすることができる。そして、保護テープ５がＵＶテープであれば、その保護テープ５に紫外線を照射すればその粘着力が失われるので、半導体チップ１′はそれぞれ容易に保護テープ５から剥がすことができるようになる。   As a result, the manufacture of the semiconductor chip 1 ′ is completed. After the semiconductor wafer 1 is unloaded from the vacuum chamber 31, when the protective tape 5 attached to the circuit forming surface 1 p of the semiconductor wafer 1 is stretched, the cut semiconductor chip 1 is cut. ′ Can be separated from each other. If the protective tape 5 is a UV tape, the adhesive strength is lost if the protective tape 5 is irradiated with ultraviolet rays, so that the semiconductor chip 1 ′ can be easily peeled off from the protective tape 5.

以上説明したように、本実施の形態における半導体チップの製造方法では、研削された半導体ウェハ１の裏面１ｑにレジスト膜６を形成した後、ダイシングライン２に沿った切り代領域（６ａ，１ｂ，１ｃ，３ａ）の一部（６ａ，１ｂ）を機械的切断手段であるブレード１３によって除去し、半導体ウェハ１の厚さ方向の残りの切り代領域１ｃの厚さｔを半導体ウェハ１の搬送に支障のない程度まで薄くした後、残りの切り代領域（１ｃ，３ａ）の全部をプラズマエッチングによって除去する。このため、切り代領域の全て（６ａ，１ｂ，１ｃ，３ａ）をプラズマエッチングによって除去して半導体ウェハ１を切り分ける場合よりもダイシングに要する時間を大幅に短縮されることができる。従って本実施の形態における半導体チップの製造方法によれば、プラズマダイシング前の搬送時に半導体ウェハ１を破損等させることなく、プラズマダイシングに要する時間を短縮させて、半導体チップ１′の生産効率を大きく向上させることができる。   As described above, in the method of manufacturing a semiconductor chip in the present embodiment, after forming the resist film 6 on the back surface 1q of the ground semiconductor wafer 1, the cutting margin regions (6a, 1b, A part (6a, 1b) of 1c, 3a) is removed by the blade 13 which is a mechanical cutting means, and the thickness t of the remaining cutting margin region 1c in the thickness direction of the semiconductor wafer 1 is transferred to the semiconductor wafer 1. After thinning to the extent that there is no hindrance, the remaining cutting margin regions (1c, 3a) are all removed by plasma etching. For this reason, the time required for dicing can be significantly shortened compared with the case where all of the cutting allowance regions (6a, 1b, 1c, 3a) are removed by plasma etching and the semiconductor wafer 1 is cut. Therefore, according to the semiconductor chip manufacturing method of the present embodiment, the time required for plasma dicing is shortened and the production efficiency of the semiconductor chip 1 ′ is increased without damaging the semiconductor wafer 1 during transport before plasma dicing. Can be improved.

また、半導体ウェハ１にレジスト膜６を形成したうえでプラズマエッチングを行うので、プラズマ雰囲気中の分解したラジカルが半導体ウェハ１の機械的切除部の近傍に集中してエッチングレートが向上し（例えば２０〜２５μｍ／分）、高速なプラズマエッチングが実現できる。しかも、レジスト膜６のレジストパターンはブレード１３による切り代除去とともに形成されるので、高価なフォトリソグラフィーは不要である。ここで、半導体ウェハ１にレジスト膜６を形成することなく、ダイシングライン２に沿った半導体ウェハ１の表面（裏面１ｑ）の一部をブレード１３によって切除し、その後プラズマエッチングを実行するようにしても半導体ウェハ１をダイシングライン２に沿ってダイシングすることは可能であるが（前述の特許文献１）、この場合にはプラズマ雰囲気中の分解したラジカルは半導体ウェハ１のブレード１３による切除部の近傍だけでなく、半導体ウェハ１の表面（裏面１ｑ）全体に分散されるため、半導体ウェハ１のエッチングレートは２μｍ／分と非常に小さくなってしまう。   Further, since the plasma etching is performed after the resist film 6 is formed on the semiconductor wafer 1, the decomposed radicals in the plasma atmosphere are concentrated in the vicinity of the mechanically cut portion of the semiconductor wafer 1 to improve the etching rate (for example, 20 High speed plasma etching can be realized. Moreover, since the resist pattern of the resist film 6 is formed along with the removal of the cutting margin by the blade 13, expensive photolithography is not necessary. Here, without forming the resist film 6 on the semiconductor wafer 1, a part of the front surface (back surface 1q) of the semiconductor wafer 1 along the dicing line 2 is removed by the blade 13, and then plasma etching is performed. Although it is possible to dice the semiconductor wafer 1 along the dicing line 2 (Patent Document 1 described above), in this case, the decomposed radicals in the plasma atmosphere are in the vicinity of the portion cut by the blade 13 of the semiconductor wafer 1. In addition, since it is dispersed over the entire front surface (back surface 1q) of the semiconductor wafer 1, the etching rate of the semiconductor wafer 1 is as extremely small as 2 μm / min.

また、半導体ウェハ１を半導体チップ１′に切り分ける際の最終的な切断は切断時のダメージの小さいプラズマエッチングによって行われるので、本実施の形態に示したように、レジスト膜６が形成される面とは反対側の面（回路形成面１ｐ）に脆弱な低誘電率層３を有する半導体ウェハ１を切り分けるときには、本製造方法が特に有効である。   Further, since the final cutting when the semiconductor wafer 1 is cut into the semiconductor chip 1 ′ is performed by plasma etching with little damage at the time of cutting, the surface on which the resist film 6 is formed as shown in the present embodiment. This manufacturing method is particularly effective when the semiconductor wafer 1 having the fragile low dielectric constant layer 3 on the opposite surface (circuit formation surface 1p) is cut.

プラズマダイシング前の搬送時に半導体ウェハを破損等させることなく、プラズマダイシングに要する時間を短縮させて、半導体チップの生産効率を大きく向上させることができる。   The time required for plasma dicing can be shortened and the production efficiency of semiconductor chips can be greatly improved without damaging the semiconductor wafer during conveyance before plasma dicing.

本発明の一実施の形態において使用するブレード切断装置の斜視図The perspective view of the braid | blade cutting device used in one embodiment of this invention 本発明の一実施の形態において使用するプラズマ処理装置の断面図Sectional drawing of the plasma processing apparatus used in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の工程手順を示すフローチャートThe flowchart which shows the process sequence of the manufacturing method of the semiconductor chip in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor chip in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor chip in one embodiment of this invention 本発明の一実施の形態における半導体チップの製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor chip in one embodiment of this invention

符号の説明Explanation of symbols

１ 半導体ウェハ
１ａ 半導体ウェハの厚さ方向の切り代領域
１ｂ 半導体ウェハの厚さ方向の切り代領域のレジスト膜側の一部
１ｃ 半導体ウェハの厚さ方向の残りの切り代領域
１ｐ 回路形成面
１ｑ 裏面
１′ 半導体チップ
２ ダイシングライン
４ 半導体素子
６ レジスト膜
６ａ レジスト膜の厚さ方向の切り代領域
１３ ブレード（機械的切断手段） DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Cutting allowance area | region of the thickness direction of a semiconductor wafer 1b A part of resist film side of the cutting allowance area | region of the thickness direction of a semiconductor wafer 1c Remaining cutting allowance area | region of the thickness direction of a semiconductor wafer 1p Circuit formation surface 1q Back surface 1 'Semiconductor chip 2 Dicing line 4 Semiconductor element 6 Resist film 6a Cutting margin area in thickness direction of resist film 13 Blade (mechanical cutting means)

Claims (2)

回路形成面に複数の半導体素子が形成された半導体ウェハを、半導体素子同士を区分するダイシングラインに沿って分割して複数の半導体チップを得る半導体チップの製造方法であって、
半導体ウェハの回路形成面とは反対側の裏面を研削する裏面研削工程と、研削された半導体ウェハの裏面にレジスト膜を形成するレジスト膜形成工程と、ダイシングラインに沿ったレジスト膜の厚さ方向の切り代領域の全部及び半導体ウェハの厚さ方向の切り代領域のレジスト膜側の一部を機械的切断手段によって除去する溝加工工程と、レジスト膜をマスクとして半導体ウェハにプラズマエッチングを施し、ダイシングラインに沿った半導体ウェハの厚さ方向の残りの切り代領域の全部を除去するプラズマダイシング工程と、プラズマダイシング工程の後、半導体ウェハからレジスト膜を除去するレジスト膜除去工程とを含むことを特徴とする半導体チップの製造方法。 A semiconductor chip manufacturing method for obtaining a plurality of semiconductor chips by dividing a semiconductor wafer in which a plurality of semiconductor elements are formed on a circuit forming surface along a dicing line that separates the semiconductor elements,
A back surface grinding process for grinding the back surface of the semiconductor wafer opposite to the circuit forming surface, a resist film forming process for forming a resist film on the back surface of the ground semiconductor wafer, and a resist film thickness direction along the dicing line A groove processing step of removing all of the cutting margin region and a portion of the cutting margin region in the thickness direction of the semiconductor wafer on the resist film side by mechanical cutting means, and performing plasma etching on the semiconductor wafer using the resist film as a mask, A plasma dicing process for removing all remaining cutting margin regions in the thickness direction of the semiconductor wafer along the dicing line, and a resist film removing process for removing the resist film from the semiconductor wafer after the plasma dicing process. A method of manufacturing a semiconductor chip. 溝加工工程終了後のダイシングラインに沿った半導体ウェハの厚さ方向の残りの切り代領域の厚さが５０〜２００μｍであることを特徴とする請求項１に記載の半導体チップの製造方法。   2. The method of manufacturing a semiconductor chip according to claim 1, wherein the thickness of the remaining cutting allowance region in the thickness direction of the semiconductor wafer along the dicing line after completion of the groove processing step is 50 to 200 μm.
JP2006349189A 2006-12-26 2006-12-26 Method for manufacturing semiconductor chip Pending JP2008159985A (en)

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