CN114512541B - Method and device for etching trench gate of semiconductor substrate - Google Patents
Method and device for etching trench gate of semiconductor substrate Download PDFInfo
- Publication number
- CN114512541B CN114512541B CN202011285829.2A CN202011285829A CN114512541B CN 114512541 B CN114512541 B CN 114512541B CN 202011285829 A CN202011285829 A CN 202011285829A CN 114512541 B CN114512541 B CN 114512541B
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- substrate
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- groove
- trench gate
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 title claims abstract description 35
- 238000005530 etching Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004381 surface treatment Methods 0.000 claims abstract description 7
- 230000008878 coupling Effects 0.000 claims abstract 4
- 238000010168 coupling process Methods 0.000 claims abstract 4
- 238000005859 coupling reaction Methods 0.000 claims abstract 4
- 238000009616 inductively coupled plasma Methods 0.000 claims description 14
- 238000005086 pumping Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 5
- 239000012495 reaction gas Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Plasma & Fusion (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a trench gate etching method of a semiconductor substrate, which comprises the following steps: step one, forming a mask on the surface of a substrate; etching a groove towards the inside of the substrate by using transformer coupling plasma through a mask, wherein the radio frequency power of the transformer coupling plasma is controlled to be 5-7kW; step three, removing the mask; step four, carrying out surface etching on the substrate; and step five, carrying out surface treatment on the substrate and the groove. The method reduces the etching time of each wafer groove under the condition of ensuring the yield, and effectively improves the productivity. The invention also provides a semiconductor device prepared by the method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench gate etching method of a semiconductor substrate.
Background
When using Transformer Coupled Plasma (TCP) to etch trenches in a semiconductor substrate, the process parameters of TCP need to be tightly controlled to ensure that the etched trenches have good surface morphology and stable electrical properties. Excessive rf power and/or excessive reactive gas flow may cause damage to the trench surface morphology, such as defects of sharp corners or grooves formed at the top of the trench due to different etching rates of the oxide forming the mask and the silicon forming the substrate, and may even cause unstable electrical performance of the semiconductor. Thus, the process parameters are typically controlled in the prior art as: the radio frequency power was 1.25kW, the pumping rate was 1300L/S, and the reactant gas flow was 1600sccm. However, under the existing process parameters, for the product with deeper trench depth, the etching time is long, the production efficiency is low, and the productivity requirement cannot be met.
Therefore, how to improve the yield under the condition of ensuring the yield is a technical problem to be solved in the semiconductor production field.
Disclosure of Invention
In order to solve the existing technical problems, the application provides a trench gate etching method of a semiconductor substrate, which combines the existing TCP process parameters with surface etching, reduces the etching time of each wafer trench under the condition of ensuring the yield, and effectively improves the productivity. The invention also provides a semiconductor device prepared by the method.
According to the present invention, there is provided a trench gate etching method of a semiconductor substrate, comprising:
step one, forming a mask on the surface of a substrate;
etching a groove towards the inside of the substrate by using high-power transformer coupled plasma through the mask, wherein the radio frequency power of the transformer coupled plasma is preferably controlled to be 5-7kW;
step three, removing the mask;
step four, carrying out surface etching on the substrate; and
and fifthly, carrying out surface treatment on the substrate and the groove.
According to one embodiment of the invention, in step two, the rf power of the transformer coupled plasma is 6kW.
In step two, the reactive gas flow rate of the transformer coupled plasma is 2200-2600sccm according to one embodiment of the present invention.
In step two, the reactive gas flow rate of the transformer-coupled plasma is 2400sccm according to one embodiment of the present invention.
In step two, the pumping rate is controlled to 1400-1800L/S according to one embodiment of the present invention.
In step two, the pumping rate is controlled to 1600L/S according to one embodiment of the present invention.
According to one embodiment of the invention, in step two, the top of the trench is pointed adjacent to the substrate of the mask.
According to one embodiment of the invention, the mask is composed of an oxide.
According to one embodiment of the invention, the surface treatment includes a thermal oxidation treatment, oxide deposition, and oxide mechanical grinding.
According to the present invention, there is provided a semiconductor device manufactured using the above method.
By adopting the technical scheme, compared with the prior art, the invention has the following advantages:
1. according to the trench gate etching method, the rate of trench formation is improved by adjusting the technological parameters of TCP to 6kW of radio frequency power, 1600L/S of pumping rate and 2400sccm of reaction gas flow;
2. according to the trench gate etching method, the defect of uneven morphology such as sharp corners or grooves at the top ends of the trenches after the process parameter adjustment is further removed through surface etching, and therefore the yield is improved under the condition of ensuring the yield.
Drawings
FIG. 1 illustrates a flow chart of one embodiment of a trench gate etch method in accordance with the present invention;
fig. 2 shows a schematic diagram of a trench gate etching method according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 1 and 2 show a specific flow of a trench gate etching method of a semiconductor substrate according to the present invention and a schematic diagram of etching a trench gate using the method, respectively. Compared with the prior art, the trench gate etching method also adopts transformer coupled plasma to carry out etching, thereby the prior machine can still be used for etching operation without replacing the prior equipment. Specifically, the trench gate etching method according to the present invention generally comprises the steps of:
step one, a mask is formed on a surface of a substrate. In embodiments of the invention, the mask may be comprised of an oxide.
Step two, a high power transformer coupled plasma is used to etch a trench through the mask towards the interior of the substrate, wherein the radio frequency power of the transformer coupled plasma is preferably controlled to be 5-7kW. Further preferably, the pumping rate and the flow rate of the reaction gas may be controlled separately, for example, the pumping rate is adjusted to 1400-1800L/S and the flow rate of the reaction gas is adjusted to 2200-2600sccm, to further increase the etching rate. The above parameters are significantly improved over the operating parameters allowed in the prior art, such that the oxide comprising the mask and the silicon comprising the substrate are etched at a much different rate, resulting in sharp corners being easily formed at the top of the trench adjacent to the substrate of the mask.
And step three, removing the mask.
And step four, carrying out surface etching on the substrate. The surface etching is limited to removing a very thin layer of the substrate surface, so that the substrate part with sharp corners is removed, and the top ends of the grooves are smoothly transited.
And fifthly, carrying out surface treatment on the substrate and the groove. In embodiments of the present invention, the surface treatment may include a sequential thermal oxidation process, oxide deposition, and oxide mechanical polishing to uniformly cover the oxide layer on the substrate and trench surfaces.
The specific parameters and yield of trench gate preparation using the trench gate etching method and the existing method according to the present invention are shown in table 1:
TABLE 1
In table 1, examples 1-3 each used the method according to the present invention to etch the trench gate, and comparative examples used the prior art method to etch the trench gate, as can be seen from comparison: the yield of the semiconductors prepared in examples 1-3 was not lower than that of the comparative examples, i.e., the existing yield was ensured. And, although examples 1-3 increased the process of surface etching, the overall yield was not decreased by the addition of the process, but at least two times higher than the prior art, i.e., the yield was significantly increased, due to the significant increase in the etching rate.
The foregoing examples merely illustrate embodiments of the invention and are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (7)
1. A trench gate etching method of a semiconductor substrate, comprising:
step one, forming a mask on the surface of a substrate;
etching a groove towards the inside of the substrate through the mask by using transformer coupling plasma, wherein the radio frequency power of the transformer coupling plasma is controlled to be 5-7kW, the flow rate of reaction gas is 2200-2600sccm, and the pumping rate is 1400-1800L/S, so that the top end of the groove is in a sharp angle shape near the substrate of the mask;
step three, removing the mask;
step four, carrying out surface etching on the substrate to remove a layer of extremely thin substrate surface, so that the substrate part with sharp corners is removed, and the top end of the groove is smoothly transited; and
and fifthly, carrying out surface treatment on the substrate and the groove.
2. The method of claim 1, wherein in step two, the rf power of the transformer-coupled plasma is 6kW.
3. The method of claim 1, wherein in the second step, the reactive gas flow rate of the transformer-coupled plasma is 2400sccm.
4. The method according to claim 1, wherein in the second step, the pumping rate is controlled to 1600L/S.
5. The method of claim 1, wherein the mask is comprised of an oxide.
6. The method of claim 1, wherein the surface treatment comprises a thermal oxidation treatment, oxide deposition, and oxide mechanical grinding.
7. A semiconductor device manufactured using the method of any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011285829.2A CN114512541B (en) | 2020-11-17 | 2020-11-17 | Method and device for etching trench gate of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011285829.2A CN114512541B (en) | 2020-11-17 | 2020-11-17 | Method and device for etching trench gate of semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114512541A CN114512541A (en) | 2022-05-17 |
| CN114512541B true CN114512541B (en) | 2024-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011285829.2A Active CN114512541B (en) | 2020-11-17 | 2020-11-17 | Method and device for etching trench gate of semiconductor substrate |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5837615A (en) * | 1995-09-21 | 1998-11-17 | Lsi Logic Corporation | Integrated circuit device fabrication by plasma etching |
| US5980768A (en) * | 1997-03-07 | 1999-11-09 | Lam Research Corp. | Methods and apparatus for removing photoresist mask defects in a plasma reactor |
| US6673695B1 (en) * | 2002-02-01 | 2004-01-06 | Chartered Semiconductor Manufacturing Ltd. | STI scheme to prevent fox recess during pre-CMP HF dip |
| CN101097861A (en) * | 2006-06-29 | 2008-01-02 | 海力士半导体有限公司 | Method of fabricating recess gate in semiconductor device |
| CN105702550A (en) * | 2014-12-15 | 2016-06-22 | 朗姆研究公司 | Ion energy control by RF pulse shape |
| CN105719952A (en) * | 2014-12-22 | 2016-06-29 | 朗姆研究公司 | Integrated etch/clean for dielectric etch applications |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5061506B2 (en) * | 2006-06-05 | 2012-10-31 | 富士電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
-
2020
- 2020-11-17 CN CN202011285829.2A patent/CN114512541B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5837615A (en) * | 1995-09-21 | 1998-11-17 | Lsi Logic Corporation | Integrated circuit device fabrication by plasma etching |
| US5980768A (en) * | 1997-03-07 | 1999-11-09 | Lam Research Corp. | Methods and apparatus for removing photoresist mask defects in a plasma reactor |
| US6673695B1 (en) * | 2002-02-01 | 2004-01-06 | Chartered Semiconductor Manufacturing Ltd. | STI scheme to prevent fox recess during pre-CMP HF dip |
| CN101097861A (en) * | 2006-06-29 | 2008-01-02 | 海力士半导体有限公司 | Method of fabricating recess gate in semiconductor device |
| CN105702550A (en) * | 2014-12-15 | 2016-06-22 | 朗姆研究公司 | Ion energy control by RF pulse shape |
| CN109103064A (en) * | 2014-12-15 | 2018-12-28 | 朗姆研究公司 | Ion energy control is carried out by RF pulse shape |
| CN105719952A (en) * | 2014-12-22 | 2016-06-29 | 朗姆研究公司 | Integrated etch/clean for dielectric etch applications |
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| Publication number | Publication date |
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| CN114512541A (en) | 2022-05-17 |
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