CN114461178A - Random number generator, electronic device and operation method - Google Patents
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Abstract
A random number generator, an electronic device and a method of operation. The random number generator includes an entropy source circuit, an entropy extraction circuit, and an output circuit. The entropy source circuit includes a charging circuit including a first memristor cell and configured to charge a first node through the first memristor cell and to change a potential of the first node. The entropy extraction circuit is coupled to the entropy source circuit, and is configured to generate a periodic variation signal having a plurality of states, extract a time value at which the first node is charged to a target potential, and acquire a random value based on a current state of the periodic variation signal corresponding to the time value. The output circuit is coupled to the entropy extraction circuit and configured to receive and output the random value. The random number generator is optimized in circuit design, avoids using a complex external circuit, and effectively reduces the circuit area and power consumption overhead.
Description
Technical Field
Embodiments of the present disclosure relate to a random number generator, an electronic device, and a method of operation.
Background
Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are important security modules in hardware security chips. The entropy source circuit is the most core circuit in the security module. The entropy source circuit for the PUF has the function of generating a static true random number, so that the PUF can output a fixed true random number each time the PUF is used; the effect of the entropy source circuit for a TRNG is to generate dynamic true random numbers such that the TRNG outputs unpredictable true random numbers each time the TRNG is used.
Disclosure of Invention
At least one embodiment of the present disclosure provides a random number generator, including: an entropy source circuit comprising a charging circuit, wherein the charging circuit comprises a first memristor cell and is configured to charge a first node through the first memristor cell and to change a potential of the first node; an entropy extraction circuit, coupled to the entropy source circuit, configured to generate a periodically varying signal having a plurality of states, extract a time value at which the first node is charged to a target potential, and obtain a random value based on a current state of the periodically varying signal corresponding to the time value; and an output circuit coupled to the entropy extraction circuit and configured to receive and output the random value.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the entropy extraction circuit includes a comparison unit and a time extraction unit, the comparison unit is coupled to the first node and configured to compare the potential of the first node with the target potential to obtain a voltage comparison result; the time extraction unit is configured to generate the periodic variation signal, extract the time value at which the first node is charged to the target potential according to the voltage comparison result, and extract the current state of the periodic variation signal corresponding to the time value as the random value.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the time extraction unit includes an oscillation subunit configured to oscillate to generate the periodic variation signal, to be controlled to stop oscillation based on the voltage comparison result, and to extract the current state of the periodic variation signal at the time of stopping oscillation as the random value.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the time extraction unit further includes a logic control subunit, and the logic control subunit is configured to receive the first control signal and perform a logic operation with the voltage comparison result to control whether the oscillation subunit stops oscillating.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the oscillation subunit is a ring oscillator configured to periodically output a first state having a first voltage and a second state having a second voltage, the first voltage being higher than the second voltage.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output circuit includes a trigger unit configured to receive the random value and an edge trigger signal, and to output the random value in response to the edge trigger signal.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the trigger unit is coupled to the comparison unit, and configured to receive the voltage comparison result to obtain the edge trigger signal, and to output the random value in response to the edge trigger signal.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the output circuit further includes a buffering subunit, and the buffering subunit is configured to receive the voltage comparison result and perform a delay process on the voltage comparison result to generate the edge trigger signal.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the triggering unit is an edge D flip-flop, an input terminal of the edge D flip-flop is configured to receive the random value, a clock terminal of the edge D flip-flop is configured to receive the edge trigger signal, and an output terminal of the edge D flip-flop is configured to output the random value in response to the edge trigger signal.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the first memristor cell includes a first memristor and a first switching element, wherein the first switching element is controlled by a second control signal, the first memristor is electrically connected between a first voltage terminal and the first switching element, the first switching element is coupled with the first node, or the first switching element is electrically connected between the first voltage terminal and the first memristor, the first memristor is coupled with the first node.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the charging circuit further includes a second memristor cell coupled to the first node so as to be able to charge the first node through the second memristor cell and to change a potential of the first node.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the second memristor cell includes a second memristor and a second switching element, the second switching element being controlled by a third control signal, the second memristor being electrically connected between a second voltage terminal and the second switching element, the second switching element being coupled with the first node, or the second switching element being electrically connected between the second voltage terminal and the second memristor, the second memristor being coupled with the first node.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the first memristor and the second memristor include resistive random access memories.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the output circuit further includes a gating unit, wherein a control terminal of the gating unit is configured to receive the fourth control signal, a first input terminal of the gating unit is configured to receive the random value, and a second input terminal of the gating unit is configured to receive the voltage comparison result.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the output terminal of the gating unit is configured such that the gating unit outputs the random value when both the first voltage terminal and the second voltage terminal receive the same voltage, or outputs the voltage comparison result when the first voltage terminal and the second voltage terminal receive different voltages, respectively, to output the target divided voltage of the first node equal to the target potential, according to the control of the fourth control signal.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the charging circuit further includes a capacitor, one electrode of which is coupled to the first node.
At least one embodiment of the present disclosure further provides an electronic device, which includes the random number generator provided in any embodiment of the present disclosure.
For example, an electronic device provided in at least one embodiment of the present disclosure further includes: a control module configured to receive a main control signal and control operation of the random number generator according to the main control signal; a voltage providing module coupled with the entropy source circuit and configured to provide at least one voltage signal to the entropy source circuit.
At least one embodiment of the present disclosure further provides an operating method for a random number generator provided in at least one embodiment of the present disclosure, including: charging, by the entropy source circuit, the first node and causing the entropy extraction circuit to generate the periodically varying signal having the plurality of states for a clocking operation; causing the entropy extraction circuit to extract the time value at which the first node is charged to the target potential; causing the entropy extraction circuit to obtain the random value based on the current state of the periodic variation signal corresponding to the time value; receiving and outputting the random value through the output circuit.
At least one embodiment of the present disclosure further provides an operating method for a random number generator provided in at least one embodiment of the present disclosure, including: charging the first node through the first memristor cell and the second memristor cell to change a potential of the first node; causing the entropy extraction circuit to generate the periodically varying signal having the plurality of states for a clocking operation; causing the entropy extraction circuit to extract the time value at which the first node is charged to the target potential; causing the entropy extraction circuit to obtain the random value based on the current state of the periodic variation signal corresponding to the time value; receiving and outputting the random value through the output circuit.
At least one embodiment of the present disclosure further provides an operating method for a random number generator provided in at least one embodiment of the present disclosure, including: receiving, by the gating unit, the fourth control signal; in response to the first and second voltage terminals receiving the same voltage signal, charging the first node through the first and second memristor cells to change a potential of the first node, causing the entropy extraction circuit to generate the periodic variation signal having the plurality of states to perform a clocking operation, causing the entropy extraction circuit to extract the time value at which the first node is charged to the target potential, causing the entropy extraction circuit to acquire the random value based on the current state of the periodic variation signal corresponding to the time value, receiving and outputting the random value through the output circuit, and causing the gating unit to output the random value according to control of the fourth control signal; or in response to receiving the different voltages at the first voltage terminal and the second voltage terminal, respectively, charging the first node through the first memristor cell and the second memristor cell to change the potential of the first node, causing the entropy extraction circuit to generate the voltage comparison result when the first node is charged to the target potential, and causing the gating cell to output the voltage comparison result according to the control of the fourth control signal.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
Fig. 1 is a schematic block diagram of a random number generator provided in at least one embodiment of the present disclosure;
fig. 2 is a schematic diagram of a random number generator according to at least one embodiment of the present disclosure;
fig. 3 is a schematic diagram of a ring oscillator according to at least one embodiment of the present disclosure;
fig. 4 is a schematic diagram of another random number generator provided in at least one embodiment of the present disclosure;
fig. 5 is a schematic diagram of another random number generator provided in at least one embodiment of the present disclosure;
fig. 6 is a schematic diagram of another random number generator provided in at least one embodiment of the present disclosure;
fig. 7 is a schematic diagram of another random number generator provided in at least one embodiment of the present disclosure;
FIG. 8 is a schematic diagram of the embodiment of FIG. 7 with the random number generator operating in a TRNG mode;
FIG. 9 is a schematic diagram of the embodiment of FIG. 7 in which the random number generator operates in a PUF mode;
fig. 10 is a schematic view of an electronic device according to some embodiments of the present disclosure;
fig. 11 is a flowchart illustrating operations of an electronic device when a TRNG mode and a PUF mode of a random number generator are reusable according to some embodiments of the present disclosure;
FIG. 12 is a flow chart of a method of operation of a random number generator provided by some embodiments of the present disclosure;
FIG. 13 is a flow chart of another method of operation of a random number generator provided by some embodiments of the present disclosure; and
fig. 14 is a flowchart of a method of operation of yet another random number generator according to some embodiments of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The present disclosure is illustrated below by means of several specific examples. Detailed descriptions of known functions and known components may be omitted in order to keep the following description of the embodiments of the present disclosure clear and concise. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numeral in each drawing.
TRNG may generate Random numbers by extracting randomness in Complementary Metal Oxide Semiconductor (CMOS) circuits or novel devices, such as Resistive Random-Access memories (RRAMs). Random motion of ions in RRAM creates randomness, also known as "read noise". For example, a method of generating true random numbers based on TRNG of RRAM read noise includes: the resistance values of the RRAM are read twice continuously and are respectively recorded as r1 and r 2; comparing the sizes of r1 and r2, and if r1 is larger than r2, outputting 1; if r1 is less than r2, 0 is output; if r1 equals r2, the output remains unchanged. In order to realize the design, a high-precision analog-digital converter and a digital comparator are needed on the circuit, but the design increases the circuit area of the TRNG and increases the design complexity.
Furthermore, the inventors have noted that in the field of hardware security, compared to the entropy source circuit design dedicated to PUF or TRNG, the reusable entropy source circuit design of PUF and TRNG can generate true random numbers both dynamically and statically with a smaller circuit area. However, the design of the entropy source circuit which can be reused by the PUF and the TRNG usually uses an external circuit with a complex structure, so that the overhead on the circuit area and the power consumption is large.
At least one embodiment of the present disclosure provides a random number generator including an entropy source circuit, an entropy extraction circuit, and an output circuit. The entropy source circuit includes a charging circuit including a first memristor cell and configured to charge a first node through the first memristor cell and to change a potential of the first node. The entropy extraction circuit is coupled to the entropy source circuit, and is configured to generate a periodic variation signal having a plurality of states, extract a time value at which the first node is charged to a target potential, and acquire a random value based on a current state of the periodic variation signal corresponding to the time value. The output circuit is coupled to the entropy extraction circuit and configured to receive and output the random value.
At least one embodiment of the present disclosure further provides an electronic device corresponding to the random number generator.
At least one embodiment of the present disclosure further provides an operating method corresponding to the random number generator.
According to the random number generator, the electronic device and the operation method provided by at least one embodiment of the disclosure, circuit design is optimized, and random values can be directly obtained through the randomness of the extracted memristor and the generated periodic variation signals of multiple states, so that a complex external circuit is avoided, and the circuit area and power consumption overhead are effectively reduced; and in at least one embodiment of realizing the reusable entropy source circuit of the PUF and the TRNG, the design of the reusable entropy source circuit of the PUF and the TRNG is simplified, the circuit area is reduced, and the power consumption is reduced.
Some embodiments of the disclosure are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic block diagram of a random number generator according to at least one embodiment of the present disclosure.
For example, as shown in FIG. 1, the random number generator 100 includes an entropy source circuit 110, an entropy extraction circuit 120, and an output circuit 130. The entropy source circuit 110 includes a charging circuit 1101, the charging circuit 1101 including a first memristor cell (not shown in the figure), and configured to charge the first node N1 through the first memristor cell and change a potential of the first node N1. The entropy extraction circuit 120 is coupled to the entropy source circuit 110, and is configured to generate a periodically varying signal having a plurality of states, extract a time value at which the first node N1 is charged to a target potential, and acquire a random value based on a current state of the periodically varying signal corresponding to the time value. The output circuit 130 is coupled to the entropy extraction circuit 120 and is configured to receive and output the random value.
Fig. 2 is a schematic diagram of a random number generator according to at least one embodiment of the present disclosure.
For example, fig. 2 shows a circuit structure of a specific implementation example of the random number generator 100 shown in fig. 1. As shown in fig. 2, the entropy source circuit 110 includes a charging circuit that includes a first memristor cell 111. The entropy source circuit 110 charges the first node 112 through the first memristor cell 111, and thus the potential of the first node 112 may be changed, denoted as Vc。
For example, as shown in fig. 2, in an embodiment of the present disclosure, the first memristor cell 111 includes a first memristor R1 and a first switching element T1. The first switching element T1 is controlled by the second control signal. The control terminal WLT of the first switching element T1 is configured to receive the second control signal. In some examples, such as shown in fig. 2, the first memristor R1 is electrically connected between the first voltage terminal BLT and a first switching element T1, the first switching element T1 being coupled with the first node 112; in other examples, the first switching element T1 is electrically connected between the first voltage terminal BLT and a first memristor R1, the first memristor R1 being coupled with the first node 112.
In at least one embodiment of the present disclosure, the first memristor R1 may be, for example, a RRAM or the like. For example, in the case where the first memristor R1 is an RRAM, the first memristor R1 is a stacked structure prepared by a semiconductor process, including two opposing electrode layers (e.g., metal electrodes) and a memory material layer interposed between the two electrodes, which may further be a stacked structure including a combination of a plurality of material layers. For example, the combination of the material layers may result in a laminated structure of TiN/HfAlOx/TaOx/TiN or TiN/HfO2/TaOx/TiN or TiN/HfO2/TiN or TiN/HfZrOx/TaOx/TiN or TiN/HfAlZrOx/TaOx/TiN or TiN/SiO2TiN, etc., as embodiments of the present disclosure are not limited in this regard.
It should be noted that the first switch element T1 may be any suitable switch element, such as a metal-oxide semiconductor field effect transistor (MOSFET), a thin film transistor (tft), or another three-terminal switch element, which is not limited in this respect by the embodiments of the present disclosure.
For example, as shown in fig. 2, in at least one embodiment, the charging circuit further comprises at least one capacitor 113, one electrode of the capacitor 113 being coupled to (e.g., integrally formed with) the first node 112, and another electrode of the capacitor 113 being, for example, grounded. The entropy source circuit 110 charges the capacitance 113 through the first memristor cell 111 to change the potential V of the first node 112c(e.g., the potential relative to the other electrode). It should be noted that the capacitor 113 may also be another electronic component capable of charging the first node 112, and the embodiment of the disclosure is not limited thereto.
For example, as shown in fig. 2, the entropy extraction circuit 120 is coupled to the entropy source circuit 110, and includes a comparison unit 121 and a time extraction unit 122. The comparing unit 121 is coupled to the first node 112 and configured to compare the potential V of the first node 112cAnd a target potential VfComparing to obtain a voltage comparison result, which is marked as Vt。
For example, the comparing unit 121 may be implemented as a comparator (e.g., a dynamic low voltage comparator, etc.), or may be implemented as other electronic components capable of implementing a voltage comparing function, which is not limited in this embodiment of the disclosure.
For example, in some examples, such as shown in fig. 2, the negative (-) input terminal of the comparison unit 121 is electrically connected to the first node 112 and configured to receive the potential V of the first node 112cThe positive (+) input terminal of the comparing unit 121 is configured to receive the target potential Vf. At this time, when Vc<VfTime, voltage comparison result VtIs at a high level; when V isc>VfTime, voltage comparison result VtIs low.
For example, in other examples, a positive (+) input terminal of the comparing unit 121 is electrically connected to the first node 112 and configured to receive the potential V of the first node 112cThe negative (-) input terminal of the comparing unit 121 is configured to receive the target potential Vf. At this time, when Vc<VfTime, voltage comparison result VtIs low level; when V isc>VfTime, voltage comparison result VtIs high.
For example, the time extraction unit 122 is configured to generate a periodically varying signal having a plurality of states; the time extraction unit 122 compares the result V with the voltagetExtracting the potential V of the first node 112cIs charged to a target potential Vf(i.e., V)c＝Vf) Time value of (1), denoted as t0And extracting the time value t0The current state of the corresponding periodically varying signal is taken as a random value.
For example, the time extraction unit 122 includes an oscillation subunit 1221. The oscillator sub-unit 1221 is configured to oscillate to generate a periodically varying signal based on the voltage comparison result VtIs controlled to stop oscillation, and the current state of the periodically varying signal at the time of stopping oscillation is extracted as a random value.
For example, as shown in fig. 2, in at least one embodiment, the oscillation subunit 1221 may be implemented as a ring oscillator. The enable terminal EN of the oscillator subunit 1221 is configured to receive the voltage comparison result Vt. The output terminal OUT of the oscillator subunit 1221 is configured to periodically output a signal having a first voltageA first state and a second state having a second voltage. For example, the first state may be a high level, and the second state may be a low level; alternatively, the first state may be a low level, and the second state may be a high level; embodiments of the present disclosure are not limited in this regard.
For example, the oscillation subunit 1221 may be a ring oscillator, or may be other electronic components (e.g., a sine signal/triangular wave/square wave generator circuit, etc.) capable of generating a periodically varying signal and implementing oscillation control, and the embodiment of the present disclosure is not limited thereto.
Fig. 3 is a schematic diagram of a ring oscillator according to at least one embodiment of the present disclosure.
For example, as shown in fig. 3, I1 and I2 are inverter circuits, and I3, I4, and I5 are inverter circuits with enable terminals. When the voltage comparison result V of the enable terminal EN of the ring oscillator is inputtWhen the voltage is high, I3 and I4 are enabled, I5 is disabled, and then I1, I3 and I4 form a three-step ring oscillator circuit, and the output end OUT of the ring oscillator outputs a periodic change signal which continuously changes between a first state and a second state; when the voltage comparison result V of the enable terminal EN of the ring oscillator is inputtAt low level (i.e. at t)0At the moment), I5 is enabled, I3 and I4 are disabled, I1 and I5 form a latch circuit, and the periodically-varying signal output from the output terminal OUT of the ring oscillator is randomly latched in the first state or the second state, i.e., the output terminal OUT outputs a stable first state or second state signal. The specific design of the third-order ring oscillator circuit and the latch circuit can refer to the description in the field, and the detailed description is omitted here.
For example, as shown in fig. 2, the output circuit 130 is coupled to the entropy extraction circuit 120 and includes a trigger unit 131. The trigger unit 131 is configured to receive a random value and an edge trigger signal, and output the random value in response to the edge trigger signal.
For example, in some examples, as shown in fig. 2, the trigger unit 131 is coupled with the comparison unit 121 and configured to receive the voltage comparison result VtTo obtain edge trigger signals and to respond to edge trigger signalsNumber to output a random value; in other examples, the edge trigger signal received by the trigger unit may be a high-speed clock signal input by an external circuit.
In the embodiment shown in fig. 2, an edge trigger signal generated inside the random number generator is used instead of a high-speed clock signal input by an external circuit, so that the overall circuit area and power consumption overhead are reduced, and the application range of the random number generator is widened (for example, the random number generator can be applied to a chip which cannot provide the high-speed clock signal).
For example, in at least one example of the embodiment of fig. 2, the trigger unit 131 may be implemented as an edge D trigger. An input terminal D of the edge D flip-flop is configured to receive a random value, a clock terminal CLK of the edge D flip-flop is configured to receive an edge trigger signal, and an output terminal Q of the edge D flip-flop is configured to output a random value in response to the edge trigger signal.
For example, the trigger unit 131 may be an edge D trigger, and may also be other electronic components capable of implementing a function of outputting a random value in response to an edge trigger signal, which is not limited in this embodiment of the disclosure.
Fig. 4 is a schematic diagram of another random number generator according to at least one embodiment of the present disclosure.
For example, as shown in fig. 4, compared to fig. 2, the time extraction unit 122 of the random number generator 100 further includes a logic control subunit 1222. The logic control subunit 1222 is configured to receive the first control signal at its control terminal ROEN and compare the first control signal with the voltage comparison result VtA logic operation is performed to control whether the oscillation subunit 1221 stops oscillating. In the example shown in FIG. 4, the logical operation is an AND operation; in other examples, the logic operation may also be other logic operations that can achieve the above control effect, and the embodiments of the present disclosure are not limited thereto. The other structures and functions of the random number generator 100 shown in fig. 4 are substantially the same as those in fig. 2, and are not repeated herein.
Fig. 5 is a schematic diagram of another random number generator according to at least one embodiment of the present disclosure.
For example, as shown in FIG. 5, this follows in comparison to FIG. 4The output circuit 130 of the machine number generator 100 further comprises a buffer subunit 132. The buffer subunit 132 is configured to receive the voltage comparison result VtComparing the voltage with the result VtA delay process is performed to generate an edge trigger signal. The buffer subunit 132 may be implemented as a buffer circuit, for example, and the embodiment of the disclosure may not limit the specific implementation of the buffer subunit. The other structures and functions of the random number generator 100 shown in fig. 5 are substantially the same as those in fig. 4, and are not repeated herein.
For example, as shown in fig. 5, the input terminal of the buffer sub-unit 132 is electrically connected to the output terminal of the comparison unit 121, and the output terminal of the buffer sub-unit 132 is electrically connected to the clock terminal CLK of the edge D flip-flop. In the embodiment shown in FIG. 5, when the potential V of the first node 112 iscIs charged to a target potential Vf(i.e., V)c＝Vf) Time, voltage comparison result VtWhen the voltage is converted from high level to low level, the comparison unit 121 outputs the voltage comparison result VtIs an edge triggered signal (here a falling edge signal). The buffer subunit 132 receives the edge trigger signal and outputs the delayed edge trigger signal to the clock terminal CLK of the edge D flip-flop. The edge D flip-flop is responsive to the delayed edge trigger signal to output the random value received at the input terminal D from the output terminal Q.
It should be noted that, when the clock terminal CLK of the edge D flip-flop receives the edge trigger signal, the signal input to the input terminal D is kept stable for at least a period of time (i.e., a signal setup time, denoted as Tsetup) before the edge D flip-flop receives the edge trigger signal, so as to ensure that the edge D flip-flop can correctly sample the input signal. If the delay time of the buffer sub-unit 132 is Tpd, the design requirement of the buffer sub-unit 132 is to ensure that Tpd > Tsetup. Thus, the buffer subunit 132 ensures that the edge trigger signal output by the comparison unit 121 is firstly applied to the oscillator subunit 1221, so that the output of the oscillator subunit 1221 is firstly locked at a high or low level; meanwhile, the edge trigger signal is guaranteed to act on the edge D trigger after a period of time delay, and the edge D trigger is guaranteed to sample the stabilized output signal of the oscillator subunit 1221, thereby ensuring that the edge D trigger can correctly sample the input signal.
Fig. 6 is a schematic diagram of another random number generator according to at least one embodiment of the present disclosure.
For example, as shown in fig. 6, compared to fig. 5, the entropy source circuit 110 of the random number generator 100 also includes a second memristor cell 114. The second memristor cell 114 is coupled to the first node 112 to enable charging of the first node 112 by the second memristor cell 114 and to change a potential of the first node 112. The other structures and functions of the random number generator 100 shown in fig. 6 are substantially the same as those in fig. 5, and are not repeated herein.
For example, as shown in fig. 6, the second memristor cell 114 includes a second memristor R2 and a second switching element T2, the second switching element T2 being controlled by a third control signal. The control terminal WLB of the second switching element T2 is configured to receive the third control signal. The second memristor R2 is electrically connected between the second voltage terminal BLB and the second switching element T2. In some examples, such as shown in fig. 6, the second switching element T2 is coupled to the first node 112; in other examples, the second switching element T2 is electrically connected between the second voltage terminal BLB and a second memristor R2, the second memristor R2 being coupled with the first node 112.
In at least one embodiment of the present disclosure, the second memristor R2 may be, for example, a RRAM or the like. The situation where the second memristor R2 is an RRAM is the same as the first memristor R1, and is not described herein again.
It should be noted that the second switching element T2 may be any suitable switching element, such as a metal-oxide semiconductor field effect transistor (MOSFET), a thin film transistor (tft), or another three-terminal switching element, which is not limited in this respect by the embodiments of the present disclosure.
In the embodiment shown in fig. 6, compared with the case that the entropy source circuit 110 only includes 1T1R, the 2T2R is adopted to fully utilize the randomness of resistance variation of memristors (such as RRAM read noise), and has better and easier-to-extract physical randomness than that of a CMOS circuit, so that the randomness of circuit output is effectively improved.
Also, it is noted that, not limited to the embodiment of fig. 5, for example, based on the embodiments shown in fig. 2, 4 and 5, a second memristor cell may also be added similar to the case of fig. 6, thereby more effectively improving the randomness of the circuit output than the case of including only 1T 1R.
Fig. 7 is a schematic diagram of another random number generator according to at least one embodiment of the present disclosure.
For example, as shown in fig. 7, compared to fig. 6, the output circuit 130 of the random number generator 100 further includes a gating unit 133. The control terminal CTR of the gating unit 133 is configured to receive the fourth control signal, the first input terminal of the gating unit 133 is configured to receive the random value, and the second input terminal of the gating unit 133 is configured to receive the voltage comparison result Vt. The output terminal of the gating unit 133 is configured such that the gating unit 133 outputs a random value when the first voltage terminal BLT and the second voltage terminal BLB both receive the same voltage according to the control of the fourth control signal, and at this time, the random number generator 100 operates in the TRNG mode; alternatively, the first voltage terminal BLT and the second voltage terminal BLB receive different voltages respectively to have a target divided voltage at the first node 112 equal to the target potential VfTime, output voltage comparison result VtAt this time, the random number generator 100 operates in the PUF mode. The other structures and functions of the random number generator 100 shown in fig. 7 are substantially the same as those in fig. 6, and are not repeated herein. For example, the gating unit 133 may include a multiplexing selection circuit, such as an alternative selection circuit.
It should be noted that the gating unit 133 gates the first input terminal when the fourth control signal is at a low level, and gates the second input terminal when the fourth control signal is at a high level; or, the second input terminal is gated when the fourth control signal is at a low level, and the first input terminal is gated when the fourth control signal is at a high level.
For example, the random number generator 100 provided in the above embodiment realizes reusability of two operation modes, TRNG and PUF. Compared with a random number generator dedicated to the TRNG or the PUF, in the embodiment of the present disclosure, the random number generator that the TRNG and the PUF can reuse can implement the same function in a smaller circuit area, thereby saving the overhead of the circuit area and the power consumption.
Fig. 8 is a schematic diagram of the embodiment of fig. 7 in which the random number generator operates in a TRNG mode.
For example, as shown in fig. 8, the first voltage terminal BLT and the second voltage terminal BLB both receive the same voltage (e.g., as shown in fig. 8, BLT and BLB both receive 200 mV); the control terminal WLT of the first switching element T1 and the control terminal WLB of the second switching element T2 receive a second control signal and a third control signal (e.g., as shown in fig. 8, the second control signal and the third control signal are both 1) to turn on the first switching element T1 and the second switching element T2, respectively; the control terminal CTR of the gating unit 133 receives a fourth control signal (e.g., as shown in fig. 8, the fourth control signal is 0) to gate the first input terminal; the logic control subunit 1222 receives the first control signal (e.g., as shown in fig. 8, the first control signal is 1) at the control terminal ROEN thereof. At this time, the random number generator 100 operates in the TRNG mode.
For example, as shown in FIG. 8, the entropy source circuit 110 charges a capacitance 113 through a first memristor cell 111 and a second memristor cell 114 to change a potential V of a first node 112c. The negative (-) of the comparing unit 121 receives the potential V of the first node 112 to the input terminalcThe positive (+) input terminal of the comparing unit 121 is configured to receive the target potential Vf(e.g., V)f＝100mV)。
For example, as shown in fig. 8, in the TRNG mode, in the first stage, the potential V of the first node 112cLess than the target potential Vf(i.e., V)c<Vf) The voltage comparison result V output by the comparison unit 121tAt a high level, the enable terminal EN of the oscillator subunit 1221 receives a high level signal, the oscillator subunit 1221 is enabled, and the output terminal OUT outputs a periodic variation signal that continuously transitions between a first state and a second state; at the end of the first phase (i.e. when Vc＝VfTime), voltage comparison result VtThe voltage is converted from high level to low level, and the comparison unit 121 outputs the voltage comparison result VtFor an edge trigger signal (here, a falling edge signal), the buffer subunit 132 receives the edge trigger signal; in the second stage, the potential V of the first node 112cIs charged to be greater than a target potential Vf(i.e., V)c>Vf) The voltage comparison result V output by the comparison unit 121tIs low (i.e. at t)0At the moment), the enable terminal EN of the oscillator subunit 1221 receives a low-level signal, the oscillator subunit 1221 is disabled, the oscillator subunit 1221 stops oscillating, and the periodically varying signal output by the output terminal OUT is randomly locked in the first state or the second state, that is, the output terminal OUT outputs a stable first state or second state signal; after the delay time Tpd of the buffer sub-unit 132, the buffer sub-unit 132 outputs the delayed edge trigger signal to the clock terminal CLK of the flip-flop unit 131, the input terminal D of the flip-flop unit 131 samples the stable first state or second state signal as a random value and outputs the random value to the first input terminal of the gating unit 133 at the output terminal Q in response to the edge trigger signal, and the output terminal of the gating unit 133 outputs the random value.
Note that the potential V of the first node 112 iscThe relationship with the charging time t is, for example, as shown in formula (1):
Vc＝Vs(1-e(-t/RC)) Formula (1)
Wherein, VsIs the equivalent supply voltage (corresponding to the voltage received by BLT and BLB), R is the equivalent resistance (corresponding to the resistance of the first memristor R1 and the second memristor R2), and C is the capacitance value of the capacitance 113. As can be seen from the formula (1), in the TRNG mode, the potential V of the first node 112cIs charged to a target potential VfTime value t of0Affected by the randomness of the resistance changes of the first memristor R1 and the second memristor R2 (e.g., RRAM read noise), the final stable state of the oscillating sub-unit 1221 is affected. The random value output by the random number generator 100 has strong randomness.
Fig. 9 is a schematic diagram of the embodiment of fig. 7 in which the random number generator operates in the PUF mode.
For example, as shown in fig. 9, the first voltage terminal BLT and the second voltage terminal BLB respectively receive different voltages (e.g., as shown in fig. 9, BLT receives 200mV, and BLB receives 0V); the control terminal WLT of the first switching element T1 and the control terminal WLB of the second switching element T2 receive the second control signal and the third control signal (for example, as shown in fig. 9, the second control signal and the third control signal are both 1) to turn on the first switching element T1 and the second switching element T2, respectively; the control terminal CTR of the gating unit 133 receives a fourth control signal (for example, as shown in fig. 9, the fourth control signal is 1) to gate the second input terminal; the logic control subunit 1222 receives the first control signal (e.g., the first control signal is 0 as shown in fig. 9) at the control terminal ROEN thereof. At this time, the random number generator 100 operates in the PUF mode.
For example, as shown in FIG. 9, the entropy source circuit 110 charges a capacitance 113 through a first memristor cell 111 and a second memristor cell 114 to change a potential V of a first node 112c. The negative (-) of the comparing unit 121 receives the potential V of the first node 112 to the input terminalcThe positive (+) input terminal of the comparing unit 121 is configured to receive the target potential Vf(e.g., V)f＝100mV)。
For example, as shown in fig. 9, in PUF mode, the resistances of the first memristor R1 and the second memristor R2 are denoted as rr1 and rr2, respectively, when the random number generator 100 outputs a random result by comparing the magnitudes of rr1 and rr 2. It is known that BLT receives 200mV and BLB receives 0V due to the voltage division of the resistors when rr1<rr2, the potential V of the first node 112cGreater than the target potential Vf(i.e., V)c>100mV), the voltage comparison result V output by the comparison unit 121 is obtainedtAt low level, the gating unit 133 outputs low level; when rr1>rr2, the potential V of the first node 112cLess than target potential Vf(i.e., V)c<100mV), the voltage comparison result V output by the comparison unit 121 is obtainedtAt high level, the gating unit 133 outputs high level.
In an embodiment such as that shown in fig. 9, the entropy source circuit 110 generates a random result by the differential resistance values of the two memristors, reduces the influence of data forgetting (retentivity) and read disturb (read disturb) of the RRAM on the storage reliability, has better data retention capability and robustness than 1T1R, and thus can significantly reduce the error rate of the circuit.
Fig. 10 is a schematic view of an electronic device according to some embodiments of the present disclosure.
For example, as shown in fig. 10, the electronic device 1 includes a random number generator 100, a control module 200, and a voltage providing module 300 provided by at least one embodiment of the present disclosure. The control module 200 is configured to receive a main control signal WDCTR and control the operation of the random number generator 100 according to the main control signal WDCTR. The voltage providing module 300 is coupled to the entropy source circuit 110 in the random number generator 100 and is configured to provide at least one voltage signal to the entropy source circuit 110, e.g., configured to receive a main control signal WDCTR and provide at least one voltage signal to the entropy source circuit 110 according to the main control signal WDCTR.
For example, taking the random number generator 100 in fig. 7 as an example, the voltage providing module 300 provides different voltage signals to the BLB by setting the main control signal WDCTR to 0 or 1; the control module 200 provides a different first control signal to ROEN and a different fourth control signal to CTR. Thus, by setting the main control signal WDCTR, the random number generator 100 can be controlled to operate in the TRNG mode or the PUF mode.
For example, as shown in table 1, when WDCTR is equal to 0, the voltage signal of the input BLB is 200mV, the first control signal of the input ROEN is 1, and the fourth control signal of the input CTR is 0, and at this time, the random number generator 100 operates in the TRNG mode; when WDCTR is equal to 1, the voltage signal of the input BLB is 0V, the first control signal of the input ROEN is 0, and the fourth control signal of the input CTR is 1, and at this time, the random number generator 100 operates in the PUF mode.
TABLE 1 WDCTR vs. random number generator mode of operation
For example, the voltage providing module 300 may be implemented by a digital circuit or an analog circuit; the control module 200 may be implemented by a digital circuit or an analog circuit, such as a CPU, a Programmable Logic Controller (PLC), etc.; embodiments of the present disclosure are not limited in this regard.
For example, in some embodiments, the electronic device 1 further comprises an output module. The output module is configured to generate random numbersRandom value (or voltage comparison result V) output by the device 100c) An operation is performed to obtain an intermediate number, and a random number is generated from the intermediate number. For example, the operation includes modulo-2LOperation, the intermediate number is a random number and the intermediate number is 2LCarry the number, L is a positive integer. For example, in some examples, L is 1, i.e., the operation includes a modulo-2 operation, the intermediate number is a 2-ary number, e.g., the output module is to a random value (or voltage comparison result V)c) Modulo-2 arithmetic is performed to obtain an intermediate number of 0 or 1, which is a random number in 2-ary form. For example, in other examples, L is 2, i.e., the operation includes a modulo-4 operation, the intermediate number is a 4-ary number, e.g., the output module is to a random value (or voltage comparison result V)c) Modulo-4 arithmetic is performed to obtain an intermediate number 0, 1, 2 or 3, the intermediate number 0, 1, 2 or 3 being a random number in 4-ary form.
For example, in the above embodiment, in the TRNG mode, the random number generator 100 extracts the time value t0The current state of the corresponding periodic variation signal is taken as a random value, so that the random value has dynamic randomness, and the output module digitalizes the random value to obtain a dynamic random number; in the PUF mode, the voltage comparison result V output by the random number generator 100cIs a random result output by comparing the magnitudes of rr1 and rr2, and thus the voltage comparison result VcHas static randomness, and the output module compares the voltage with the result VcDigitized to obtain static random numbers.
Fig. 11 is a flowchart of an electronic device when the TRNG mode and the PUF mode of the random number generator are reusable according to some embodiments of the present disclosure, for example, corresponding to the embodiments shown in fig. 7 to 9.
For example, as shown in fig. 11, when WDCTR is 0, the random number generator 100 operates in the TRNG mode and outputs a random value having dynamic randomness, and the electronic device 1 extracts the dynamic randomness and digitizes a random variable corresponding to the random value to generate a dynamic random number; when WDCTR is 1, the random number generator 100 operates in the PUF mode and outputs the voltage comparison result V having static randomnesscThe electronic device 1 extracts the static randomnessAnd comparing the voltage with the result VcThe corresponding random variables are digitized to generate static random numbers.
Fig. 12 is a flow chart of a method of operation of a random number generator according to some embodiments of the present disclosure, e.g., corresponding to the embodiment shown in fig. 2.
For example, as shown in fig. 12, in at least one embodiment of the present disclosure, the operation method of the random number generator 100 includes the following steps S110 to S140.
Step S110: charging the first node 112 by the entropy source circuit 110 and causing the entropy extraction circuit 120 to generate a periodically varying signal having a plurality of states for clocking operations;
step S120: causing the entropy extraction circuit 120 to extract a time value at which the first node 112 is charged to the target potential;
step S130: causing the entropy extraction circuit 120 to obtain a random value based on the current state of the periodically varying signal corresponding to the time value;
step S140: the random value is received and output through the output circuit 130.
For example, as shown in FIG. 2, the entropy source circuit 110 charges a capacitance 113 through a first memristor cell 111 to change a potential V of a first node 112c. In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112cAnd a target potential VfComparing to obtain a voltage comparison result Vt(ii) a The time extraction unit 122 generates a periodically varying signal having a plurality of states and compares the result V according to the voltagetExtracting the potential V of the first node 112cIs charged to a target potential Vf(i.e., V)c＝Vf) Time value t of0Extracting the time value t0The current state of the corresponding periodically varying signal is taken as a random value. In the output circuit 130, the trigger unit 131 receives a random value and an edge trigger signal, and outputs the random value in response to the edge trigger signal.
In the embodiment of fig. 2, for example, the edge trigger signal generated inside the random number generator is used to replace the high-speed clock signal input by the external circuit, so that the overall circuit area and power consumption overhead are reduced, and the application range of the random number generator is widened (for example, the random number generator can be applied to a chip which cannot provide the high-speed clock signal).
Fig. 13 is a flow chart of another method of operation of a random number generator provided in some embodiments of the present disclosure, e.g., corresponding to the embodiment shown in fig. 6.
For example, as shown in FIG. 13, in some embodiments, when the entropy source circuit 110 of the random number generator 100 includes both the first memristor cell 111 and the second memristor cell 114, such as the embodiments shown in FIG. 6 or FIG. 7, the method of operation of the random number generator 100 includes the following steps S210-S250.
Step S210: charging a first node 112 through a first memristor cell 111 and a second memristor cell 114 to change a potential of the first node 112;
step S220: causing the entropy extraction circuit 120 to generate a periodically varying signal having a plurality of states for a clocking operation;
step S230: causing the entropy extraction circuit 120 to extract a time value at which the first node 112 is charged to the target potential;
step S240: the entropy extraction circuit 120 is caused to acquire a random value based on the current state of the periodically varying signal corresponding to the time value;
step S250: the random value is received and output through the output circuit 130.
For example, as shown in FIG. 6, the entropy source circuit 110 charges a capacitance 113 through a first memristor cell 111 and a second memristor cell 114 to change a potential V of a first node 112c. In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112cAnd a target potential VfComparing to obtain a voltage comparison result Vt(ii) a The time extraction unit 122 generates a periodically varying signal having a plurality of states and compares the result V according to the voltagetExtracting the potential V of the first node 112cIs charged to a target potential Vf(i.e., V)c＝Vf) Time value t of0Extracting the time value t0The current state of the corresponding periodically varying signal is taken as a random value. In the output circuit 130The trigger unit 131 receives a random value and an edge trigger signal, and outputs a random value in response to the edge trigger signal.
In the embodiment shown in fig. 6, compared with the case that the entropy source circuit 110 only includes 1T1R, the 2T2R is adopted to fully utilize the randomness of resistance variation of memristors (such as RRAM read noise), and has better and easier-to-extract physical randomness than that of a CMOS circuit, so that the randomness of circuit output is effectively improved.
Fig. 14 is a flow chart of yet another method of operation of a random number generator provided in some embodiments of the present disclosure, e.g., corresponding to the embodiment shown in fig. 7.
For example, as shown in fig. 14, in other embodiments, when the entropy source circuit 110 of the random number generator 100 includes both the first memristor cell 111 and the second memristor cell 114, and the output circuit 130 includes the gating cell 133, so that both TRNG and PUF operation modes are reusable, such as the embodiment shown in fig. 7, the operation method of the random number generator 100 includes the following steps S300, S311 to S315(TRNG operation mode), and S321 to S323(PUF operation mode).
Step S300: the gating unit 133 receives the fourth control signal;
in response to the first voltage terminal and the second voltage terminal receiving the same voltage signal:
step S311: charging a first node 112 through a first memristor cell 111 and a second memristor cell 114 to change a potential of the first node 112;
step S312: causing the entropy extraction circuit 120 to generate a periodically varying signal having a plurality of states for a clocking operation;
step S313: causing the entropy extraction circuit 120 to extract a time value at which the first node 112 is charged to the target potential;
step S314: the entropy extraction circuit 120 is caused to acquire a random value based on the current state of the periodically varying signal corresponding to the time value;
step S315: receiving and outputting the random value through the output circuit 130;
step S316: causing the gating unit 133 to output a random value according to the control of the fourth control signal;
alternatively, in response to receiving different voltages at the first voltage terminal and at the second voltage terminal, respectively:
step S321: charging a first node 112 through a first memristor cell 111 and a second memristor cell 114 to change a potential of the first node 112;
step S322: causing the entropy extraction circuit 120 to generate a voltage comparison result when the first node 112 is charged to the target potential;
step S323: the gate unit 133 is caused to output the voltage comparison result according to the control of the fourth control signal.
For example, the random number generator 100 shown in fig. 7 is taken as an example. For example, as shown in fig. 8, the control terminal CTR of the gating unit 133 receives the fourth control signal to gate the first input terminal, and the first voltage terminal BLT and the second voltage terminal BLB both receive the same voltage, at which time the random number generator 100 operates in the TRNG mode. The entropy source circuit 110 charges the capacitance 113 through the first memristor cell 111 and the second memristor cell 114 to change the potential V of the first node 112c. In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112cAnd a target potential VfComparing to obtain a voltage comparison result Vt(ii) a The time extraction unit 122 generates a periodically varying signal having a plurality of states and compares the result V according to the voltagetExtracting the potential V of the first node 112cIs charged to a target potential Vf(i.e., V)c＝Vf) Time value t of0Extracting the time value t0The current state of the corresponding periodically varying signal is taken as a random value. In the output circuit 130, the trigger unit 131 receives a random value and an edge trigger signal, and outputs the random value in response to the edge trigger signal; the output terminal of the gating unit 133 outputs the random value.
For example, as shown in fig. 9, the control terminal CTR of the gating unit 133 receives the fourth control signal to gate the second input terminal, and the first voltage terminal BLT and the second voltage terminal BLB respectively receive different voltages, at which time the random number generator 100 operates in the PUF mode. The entropy source circuit 110 is connected to the first memristor cell 111 and the second memristorThe unit 114 charges the capacitor 113 to change the potential V of the first node 112c. In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112cAnd a target potential VfComparing to obtain a voltage comparison result Vt. In the output circuit 130, the output terminal of the gating unit 133 outputs the voltage comparison result Vt。
In embodiments such as those shown in fig. 7-9, random number generator 100 implements the reusability of both TRNG and PUF modes of operation. Compared with the random number generator special for the TRNG or the PUF, the random number generator reusable for the TRNG and the PUF can achieve the same function in a smaller circuit area, and therefore the circuit area and the power consumption overhead are saved.
For the present disclosure, there are the following points to be explained:
(1) in the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to general designs.
(2) Features of the disclosure in the same embodiment and in different embodiments may be combined with each other without conflict.
The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and shall be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (12)
1. A random number generator, comprising:
an entropy source circuit comprising a charging circuit, wherein the charging circuit comprises a first memristor cell and is configured to charge a first node through the first memristor cell and to change a potential of the first node;
an entropy extraction circuit, coupled to the entropy source circuit, configured to generate a periodically varying signal having a plurality of states, extract a time value at which the first node is charged to a target potential, and obtain a random value based on a current state of the periodically varying signal corresponding to the time value; and
an output circuit coupled to the entropy extraction circuit and configured to receive and output the random value.
2. The random number generator of claim 1, wherein the entropy extraction circuit includes a comparison unit and a time extraction unit,
the comparison unit is coupled with the first node and configured to compare the potential of the first node with the target potential to obtain a voltage comparison result;
the time extraction unit is configured to generate the periodic variation signal, extract the time value at which the first node is charged to the target potential according to the voltage comparison result, and extract the current state of the periodic variation signal corresponding to the time value as the random value.
3. The random number generator of claim 2, wherein the time extraction unit comprises an oscillation subunit,
the oscillation subunit is configured to oscillate to generate the periodic variation signal, is controlled to stop oscillation based on the voltage comparison result, and extracts the current state of the periodic variation signal at the time of stopping oscillation as the random value.
4. The random number generator of claim 2, wherein the output circuit comprises a trigger unit,
the trigger unit is configured to receive the random value and an edge trigger signal, and to output the random value in response to the edge trigger signal.
5. The random number generator of claim 7, wherein the output circuit further comprises a buffering subunit configured to receive the voltage comparison result, delay the voltage comparison result to generate the edge trigger signal.
6. The random number generator of claim 10, wherein the charging circuit further comprises a second memristor cell,
the second memristor cell is coupled with the first node so that the first node can be charged by the second memristor cell and changes a potential of the first node.
7. The random number generator of claim 13, wherein the output circuit further comprises a gating cell, wherein,
the control terminal of the gating unit is configured to receive a fourth control signal, the first input terminal of the gating unit is configured to receive the random value, and the second input terminal of the gating unit is configured to receive the voltage comparison result.
8. The random number generator of claim 14, wherein the output of the gating unit is configured to output the random value when the first voltage terminal and the second voltage terminal both receive the same voltage, or,
and outputting the voltage comparison result when the first voltage end and the second voltage end respectively receive different voltages so as to enable the target voltage division of the first node to be equal to the target potential.
9. An electronic device comprising a random number generator as claimed in any of claims 1 to 16.
10. A method of operation for a random number generator according to any of claims 1 to 16, comprising:
charging, by the entropy source circuit, the first node and causing the entropy extraction circuit to generate the periodically varying signal having the plurality of states for a clocking operation;
causing the entropy extraction circuit to extract the time value at which the first node is charged to the target potential;
causing the entropy extraction circuit to obtain the random value based on the current state of the periodic variation signal corresponding to the time value;
receiving and outputting the random value through the output circuit.
11. A method of operation for a random number generator according to claim 11, comprising:
charging the first node through the first memristor cell and the second memristor cell to change a potential of the first node;
causing the entropy extraction circuit to generate the periodically varying signal having the plurality of states for a clocking operation;
causing the entropy extraction circuit to extract the time value at which the first node is charged to the target potential;
causing the entropy extraction circuit to obtain the random value based on the current state of the periodic variation signal corresponding to the time value;
receiving and outputting the random value through the output circuit.
12. A method of operation for a random number generator according to claim 15, comprising:
receiving, by the gating unit, the fourth control signal;
in response to the first and second voltage terminals receiving the same voltage signal, charging the first node through the first and second memristor cells to change a potential of the first node, causing the entropy extraction circuit to generate the periodic variation signal having the plurality of states to perform a timing operation, causing the entropy extraction circuit to extract the time value at which the first node is charged to the target potential, causing the entropy extraction circuit to acquire the random value based on the current state of the periodic variation signal corresponding to the time value, receiving and outputting the random value through the output circuit, and causing the gating unit to output the random value according to control of the fourth control signal; or,
in response to receiving the different voltages at the first voltage terminal and the second voltage terminal respectively, charging the first node through the first memristor cell and the second memristor cell to change the potential of the first node, causing the entropy extraction circuit to generate the voltage comparison result when the first node is charged to the target potential, causing the gating cell to output the voltage comparison result according to control of the fourth control signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210138347.7A CN114461178A (en) | 2022-02-15 | 2022-02-15 | Random number generator, electronic device and operation method |
| PCT/CN2022/078597 WO2023155240A1 (en) | 2022-02-15 | 2022-03-01 | Random number generator, electronic device, and operating method |
Applications Claiming Priority (1)
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| CN202210138347.7A CN114461178A (en) | 2022-02-15 | 2022-02-15 | Random number generator, electronic device and operation method |
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| Publication Number | Publication Date |
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| CN114461178A true CN114461178A (en) | 2022-05-10 |
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| CN202210138347.7A Pending CN114461178A (en) | 2022-02-15 | 2022-02-15 | Random number generator, electronic device and operation method |
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| CN (1) | CN114461178A (en) |
| WO (1) | WO2023155240A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115766029A (en) * | 2022-11-11 | 2023-03-07 | 武汉科技大学 | Multifunctional PUF circuit based on memristor and use method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4837549B2 (en) * | 2006-12-28 | 2011-12-14 | Ｆｄｋ株式会社 | Physical random number generator and physical random number generator |
| US9189201B2 (en) * | 2011-09-20 | 2015-11-17 | Qualcomm Incorporated | Entropy source with magneto-resistive element for random number generator |
| US10168994B2 (en) * | 2017-04-11 | 2019-01-01 | Intel Corporation | Random number generator including entropy source |
| CN110989972B (en) * | 2019-12-05 | 2021-11-30 | 清华大学 | Random number generation method and random number generator |
| CN111461312B (en) * | 2020-03-26 | 2022-04-22 | 华中科技大学 | Random neuron discarding based on memristor |
| CN111562901B (en) * | 2020-04-30 | 2023-09-22 | 清华大学 | Random number generator and random number generation method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115766029A (en) * | 2022-11-11 | 2023-03-07 | 武汉科技大学 | Multifunctional PUF circuit based on memristor and use method thereof |
| CN115766029B (en) * | 2022-11-11 | 2024-04-05 | 武汉科技大学 | Memristor-based multifunctional PUF circuit and use method thereof |
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| Publication number | Publication date |
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| WO2023155240A1 (en) | 2023-08-24 |
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