CN111562901B - Random number generator and random number generation method - Google Patents
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Abstract
A random number generator and a random number generation method. The random number generator includes: a resistive random access memory; a resistance perturbation circuit coupled to the resistive random access memory and configured to perform n resistance perturbation operations on the resistive random access memory to perturb a resistance value of the resistive random access memory such that the resistance value of the resistive random access memory becomes a perturbed resistance value, each of the n resistance perturbation operations including performing a set operation and a reset operation on the resistive random access memory, n being a positive integer; and the coding circuit is coupled to the resistance change memory and is configured to code the disturbed resistance value of the resistance change memory to generate a random number. The random number generator utilizes the nonlinear characteristic of the resistive random access memory, can realize self calibration, has the advantages of high reliability, small circuit area, low power consumption and high speed, and is very suitable for large-scale parallelism.
Description
Technical Field
Embodiments of the present disclosure relate to a random number generator and a random number generation method.
Background
The random number generators can be categorized into pseudo random number generators (Pseudo Random Number Generator, PRNG) and true random number generators (True Random Number Generator, TRNG). TRNG can generate random numbers by extracting randomness in Complementary Metal Oxide Semiconductor (CMOS) circuits or new devices, such as Resistive Random Access Memories (RRAM). Compared to PRNGs, TRNGs are able to generate random number sequences that are infinitely long and theoretically unpredictable, with higher security and better randomness.
Disclosure of Invention
At least one embodiment of the present disclosure provides a random number generator including: a resistive random access memory; a resistance perturbation circuit coupled to the resistive random access memory and configured to perform n resistance perturbation operations on the resistive random access memory to perturb a resistance value of the resistive random access memory such that the resistance value of the resistive random access memory becomes a perturbed resistance value, each of the n resistance perturbation operations including performing a set operation and a reset operation on the resistive random access memory, n being a positive integer; an encoding circuit, coupled to the resistive random access memory, is configured to encode a perturbed resistance value of the resistive random access memory to generate a random number.
For example, in the random number generator provided in at least one embodiment of the present disclosure, when a resistance perturbation operation is performed once, the resistance perturbation circuit is configured to perform the reset operation on the resistance random access memory and perform the set operation on the resistance random access memory on which the reset operation is performed, so as to perturb the resistance value of the resistance random access memory.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the resistance perturbation circuit includes a set operation sub-circuit and a reset operation sub-circuit; the set operation subcircuit is configured to apply a set pulse to the resistive switching memory to perform the set operation; the reset operation subcircuit is configured to apply a reset pulse to the resistive switching memory to perform the reset operation.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the resistance perturbation circuit is configured to perform the n resistance perturbation operations on the resistance random access memory so that the perturbed resistance value of the resistance random access memory is in a resistance symmetric region.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the encoding circuit includes a pressurizing sub-circuit, a speed measuring sub-circuit, and an output sub-circuit; the voltage application sub-circuit is coupled to the resistive random access memory and is configured to apply a control voltage to a word line end of the resistive random access memory and a read voltage to a bit line end of the resistive random access memory so as to control a source line end output current of the resistive random access memory; the speed measurement sub-circuit is coupled to the resistive random access memory and is configured to measure and output an energy storage speed under the condition of energy storage by utilizing the current output by the source terminal of the resistive random access memory; the output sub-circuit is coupled to the speed measurement sub-circuit and configured to generate the random number based on the stored energy speed.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the speed measurement subcircuit includes a power storage subcircuit, a comparison subcircuit, a clock pulse generation subcircuit, and a counting subcircuit; the energy storage sub-circuit is coupled to the resistance change memory and is configured to store energy by utilizing the current output by the source terminal of the resistance change memory so as to obtain energy storage voltage; the comparison sub-circuit is coupled to the energy storage sub-circuit and is configured to compare the energy storage voltage with a reference voltage to obtain a voltage comparison result; the clock generation sub-circuit is configured to generate a clock; the counting sub-circuit is coupled to the comparing sub-circuit and the clock pulse generating sub-circuit, configured to count the clock pulses, and responsive to the voltage comparison result indicating that the stored voltage exceeds the reference voltage, stop counting and output a current count value as the stored speed.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output sub-circuit is configured to operate on the current count value to obtain an intermediate number, and generate the random number according to the intermediate number.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the operation includes modulo 2 L Calculating, wherein the intermediate number is used as the random number and is 2 L And (3) carrying out number making, wherein L is a positive integer.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the counting sub-circuit includes a 1-bit counter configured to output a 1-bit 2-ary number as the current count value, and the output sub-circuit is configured to output the current count value as the random number.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the encoding circuit includes a pressing sub-circuit, an analog-to-digital conversion sub-circuit, and an output sub-circuit; the voltage application sub-circuit is coupled to the resistive random access memory and is configured to apply a control voltage to a word line end of the resistive random access memory and a read voltage to a bit line end of the resistive random access memory so as to control a source line end output current of the resistive random access memory; the analog-to-digital conversion sub-circuit is coupled to the resistance change memory and is configured to convert the current output by the source terminal of the resistance change memory into a digital signal value; the output sub-circuit is coupled to the analog-to-digital conversion sub-circuit and is configured to generate the random number from the digital signal value.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output subcircuit is configured to operate on the digital signal value to obtain an intermediate number, and to generate the random number from the intermediate number.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the operation includes modulo 2 L Calculating, wherein the intermediate number is used as the random number and is 2 L And (3) carrying out number making, wherein L is a positive integer.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output sub-circuit includes a register configured to register the digital signal value and take the lowest L bits of the digital signal value as the intermediate number.
For example, at least one embodiment of the present disclosure provides for the random number generator to further include a control circuit coupled to the resistance perturbation circuit and the encoding circuit configured to control the resistance perturbation circuit and the encoding circuit to generate a predetermined number of random numbers.
At least one embodiment of the present disclosure further provides a method for generating a random number, including: performing n resistance perturbation operations on a first resistive random access memory to perturb a resistance value of the first resistive random access memory such that the resistance value of the first resistive random access memory becomes a first perturbed resistance value, each of the n resistance perturbation operations including performing a set operation and a reset operation on the first resistive random access memory, n being a positive integer; a first perturbed resistance value of the first resistive memory is encoded to generate a first random number.
For example, in a method provided by at least one embodiment of the present disclosure, each of the n resistance perturbation operations includes: the reset operation is performed on the first resistive random access memory, and the set operation is performed on the first resistive random access memory on which the reset operation is performed, so as to disturb the resistance value of the first resistive random access memory.
For example, in a method provided by at least one embodiment of the present disclosure, performing the set operation includes: applying a set pulse to the first resistive random access memory; performing the reset operation includes: and applying a reset pulse to the first resistive random access memory.
For example, in a method provided in at least one embodiment of the present disclosure, performing n resistance perturbation operations on a first resistive random access memory to perturb a resistance value of the first resistive random access memory such that the resistance value of the first resistive random access memory becomes a first perturbed resistance value, including: and executing the n resistance perturbation operations on the first resistance random access memory so that the first perturbed resistance value of the first resistance random access memory is in a resistance symmetric region.
For example, in a method provided by at least one embodiment of the present disclosure, encoding a first perturbed resistance value of the first resistive memory to generate a first random number includes: applying a control voltage to a word line terminal of the first resistive random access memory and a read voltage to a bit line terminal of the first resistive random access memory to control a source line terminal output current of the first resistive random access memory; storing energy by utilizing the current output by the source terminal of the first resistive random access memory to measure and output an energy storage speed; and generating the first random number according to the energy storage speed.
For example, in a method provided by at least one embodiment of the present disclosure, storing energy using the current output from a source terminal of the first resistive random access memory to measure and output an energy storage speed includes: storing energy by utilizing the current output by the source terminal of the first resistive random access memory to obtain energy storage voltage; comparing the energy storage voltage with a reference voltage to obtain a voltage comparison result; generating a clock pulse; and counting the clock pulses, stopping counting and outputting a current count value as the energy storage speed in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage.
For example, in a method provided by at least one embodiment of the present disclosure, generating the first random number according to the energy storage speed includes: and calculating the current count value to obtain an intermediate number, and generating the first random number according to the intermediate number.
For example, in a method provided by at least one embodiment of the present disclosure, encoding a first perturbed resistance value of the first resistive memory to generate a first random number includes: applying a control voltage to a word line terminal of the first resistive random access memory and a read voltage to a bit line terminal of the first resistive random access memory to control a source line terminal output current of the first resistive random access memory; converting the current output by the source terminal of the first resistive random access memory into a digital signal value; and generating the first random number according to the digital signal value.
For example, in a method provided by at least one embodiment of the present disclosure, generating the first random number from the digital signal value includes: and calculating the digital signal value to obtain an intermediate number, and generating the first random number according to the intermediate number.
For example, at least one embodiment of the present disclosure provides a method further comprising: performing m1 resistance perturbation operations on a second resistive random access memory to perturb a resistance value of the second resistive random access memory such that the resistance value of the second resistive random access memory becomes a second perturbed resistance value, each of the m1 resistance perturbation operations including performing a set operation and a reset operation on the second resistive random access memory, the first resistive random access memory and the second resistive random access memory being different, m1 being a positive integer; encoding a second perturbed resistance value of the second resistive memory to generate a second random number.
For example, at least one embodiment of the present disclosure provides a method further comprising: performing m2 resistance perturbation operations on the first resistive random access memory to perturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a third perturbed resistance value, each of the m2 resistance perturbation operations including performing a set operation and a reset operation on the first resistive random access memory, m2 being a positive integer; encoding a third perturbed resistance value of the first resistive memory to generate a third random number.
For example, in a method provided by at least one embodiment of the present disclosure, the first perturbed resistance value and the third perturbed resistance value are different.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
FIG. 1 is a schematic block diagram of a random number generator provided in at least one embodiment of the present disclosure;
FIG. 2A illustrates a schematic diagram of one example of a resistive random access memory;
FIG. 2B illustrates a schematic diagram of performing a set operation on a resistive switching memory;
FIG. 2C illustrates a schematic diagram of a reset operation performed on a resistive random access memory;
FIG. 3A illustrates a schematic diagram of a set operation and a reset operation versus resistance change of a resistive switching memory;
FIG. 3B is a schematic diagram illustrating the relationship of the resistance perturbation operation and the resistance change of the resistive random access memory;
FIGS. 4A and 4B illustrate perturbed resistance values of a resistive random access memory;
FIG. 5 is a schematic block diagram of one example of a random number generator provided by at least one embodiment of the present disclosure;
FIG. 6 is a schematic block diagram of a speed measurement subcircuit provided by at least one embodiment of the present disclosure;
FIG. 7 is a schematic diagram of one example of a random number generator provided in accordance with at least one embodiment of the present disclosure;
FIG. 8 illustrates a schematic diagram of a random number generated by a random number generator provided by at least one embodiment of the present disclosure;
FIG. 9 is a schematic block diagram of another example of a random number generator provided by at least one embodiment of the present disclosure;
FIG. 10 is a schematic diagram of another example of a random number generator provided by at least one embodiment of the present disclosure;
FIG. 11 is a flow chart of a method for generating random numbers according to at least one embodiment of the present disclosure;
fig. 12 is a flowchart of an example of a method for generating a random number according to at least one embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Currently, the technology for implementing TRNG is mainly implemented in the following ways: (1) CMOS thermal noise; (2) RRAM (or Magnetic Random Access Memory (MRAM)) switching speed; (3) RRAM (or MRAM) switching threshold; (4) RRAM read noise. For the design of TRNG using modes (1) (2) (3), additional calibration circuitry is required to ensure that TRNG can operate in the expected state to generate high entropy random numbers. First, the use of calibration circuitry increases power consumption; second, many applications require TRNGs to be able to operate in parallel to reach very high speeds, and the use of calibration circuits exacerbates the contradiction between speed and area. Therefore, implementing the TRNG design with the modes (1) (2) (3) increases power consumption and makes it difficult to achieve a balance between circuit area and speed.
The design for realizing TRNG by the above-described mode (4) includes: reading the resistance value of the RRAM twice in succession; comparing the resistance values read twice; outputting 1 if the resistance value read for the first time is larger than the resistance value read for the second time; outputting 0 if the resistance value read for the first time is smaller than the resistance value read for the second time; if the resistance value of the first reading is equal to the resistance value of the second reading, the output is kept unchanged. For the implementation of TRNG design using the above-described approach (4), uncontrollability of RRAM read noise may result in failure to generate random numbers with high randomness. For example, for a portion of the RRAM, the read noise may be too small to be detected by the circuit. For example, for a portion of the RRAM, the read noise may be initially large, but become small after a period of time. Therefore, it is difficult to ensure reliability in the design of TRNG by the above-described method (4).
The index for evaluating TRNG includes speed, reliability, circuit area, power consumption, and the like, wherein speed refers to the number of random numbers (bits/second) generated per second; reliability refers to whether unpredictable random numbers can be generated at different temperatures, voltages and working durations; the circuit area refers to the size of the area occupied by the device; power consumption refers to the energy (joules per bit (J/bit)) required to generate a random number per bit.
In summary, the existing TRNGs respectively have corresponding disadvantages.
At least one embodiment of the present disclosure provides a random number generator including: a resistive random access memory; a resistance perturbation circuit coupled to the resistive random access memory and configured to perform n resistance perturbation operations on the resistive random access memory to perturb a resistance value of the resistive random access memory such that the resistance value of the resistive random access memory becomes a perturbed resistance value, each of the n resistance perturbation operations including performing a set operation and a reset operation on the resistive random access memory, n being a positive integer; and the coding circuit is coupled to the resistance change memory and is configured to code the disturbed resistance value of the resistance change memory to generate a random number.
At least one embodiment of the present disclosure further provides a method for generating a random number corresponding to the above random number generator.
The random number generator and the random number generation method provided by the embodiment of the disclosure can realize self-calibration by utilizing the nonlinear characteristic of the resistive random access memory, have the advantages of high reliability, small circuit area, low power consumption and high speed, and are very suitable for large-scale parallelism. It should be noted that, in the embodiments of the present disclosure, self-calibration means that no human intervention is required, and the resistance value of the resistive random number generator in the resistive random number memory may spontaneously fluctuate within a specific range.
Embodiments of the present disclosure and examples thereof are described in detail below with reference to the attached drawing figures.
Fig. 1 is a schematic block diagram of a random number generator provided in at least one embodiment of the present disclosure. As shown in fig. 1, the random number generator 100 includes a resistance change memory 110, a resistance perturbation circuit 120, and an encoding circuit 130. The resistance perturbation circuit 120 is coupled to the resistive random access memory 110 and configured to perform n resistance perturbation operations on the resistive random access memory 110 to perturb the resistance value of the resistive random access memory 110 such that the resistance value of the resistive random access memory 110 becomes a perturbed resistance value, each of the n resistance perturbation operations including performing a set operation and a reset operation on the resistive random access memory 110, n being a positive integer; the encoding circuit 130 is coupled to the resistive random access memory 110 and configured to encode the perturbed resistance value of the resistive random access memory 110 to generate a random number.
For example, the random number generator is a true random number generator, and the generated random number is a true random number.
It should be noted that the random number may be a random number in a 2-system form (i.e., the random number is 0 or 1), or may be another random number, for example, a random number in a 4-system, a 10-system, a 16-system, or the like. In the embodiments of the present disclosure, in order to more clearly describe the technical solutions of the present disclosure, the description will be given by taking the case that the random number refers to the random number in the form of 2-ary, unless otherwise specified.
For example, fig. 2A illustrates a schematic diagram of one example of a resistance change memory, fig. 2B illustrates a schematic diagram of performing a set operation on the resistance change memory, and fig. 2C illustrates a schematic diagram of performing a reset operation on the resistance change memory. The structure of the resistive random access memory and the set and reset operations are described below in conjunction with fig. 2A-2C.
For example, the resistive random access memory may employ a 1T1R structure. As shown in fig. 2A, the resistive random access memory includes a transistor M1 and a resistive element R1, where a gate of the transistor M1 is connected to a word line terminal WL, a first pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a negative pole) of the resistive element R1, and a first pole (e.g., a positive pole) of the resistive element R1 is connected to a bit line terminal BL, and a second pole of the transistor M1 may be a source and configured to be connected to a source line terminal SL. If the transistor M1 is an N-type transistor, as shown in FIG. 2A and FIG. 2B, for the set operation, a voltage V is applied to the word line terminal WL of the resistive random access memory WL A control voltage of high level, a voltage V applied to a bit line terminal BL of the resistive random access memory BL For the SET (SET) pulse, a voltage V is applied to the source terminal SL of the resistive random access memory SL Is a low level voltage (e.g., ground). As shown in fig. 2A and 2C, for the reset operation, a voltage V is applied to the word line terminal WL of the resistive random access memory WL A control voltage of high level, a voltage V applied to a source terminal SL of the resistive random access memory SL For RESET (RESET) pulses, a voltage V is applied to the bit line terminal BL of the resistive memory BL Is a low level voltage (e.g., ground).
It should be noted that, in the embodiments of the present disclosure, in order to distinguish between two poles of a transistor except a gate, one of the poles is directly described as a first pole, and the other pole is a second pole.
For example, the transistor M1 may be a thin film transistor or a field effect transistor (e.g., a MOS field effect transistor) or other switching devices having the same characteristics, and the source and drain of the transistor employed may be symmetrical in structure, so that the source and drain thereof may be indistinguishable in structure. For example, the transistor M1 may be an N-type transistor as shown in fig. 2A-2C, the disclosure is not limited thereto, and the transistor M1 may be a P-type transistor. For clarity and consistency, the following embodiments will be described using N-type transistors as examples of the transistor M1.
For example, the number n of resistance perturbation operations for perturbing the resistance value of the resistance change memory 110 may be determined according to the actual situation. For example, in the case where n is equal to 1 (i.e., one random number can be generated for each resistance perturbation operation), the total time of the resistance perturbation operation is the shortest, and the random number generator generates the random number at the fastest speed. For example, the random number generation speed of each resistive random number memory is 1Mbit/s.
For example, when one resistance perturbation operation is performed, the resistance perturbation circuit 120 is configured to perform a reset operation on the resistance variable memory, and perform a set operation on the resistance variable memory on which the reset operation is performed, to perturb the resistance value of the resistance variable memory. For example, when one resistance perturbation operation is performed, the resistance perturbation circuit 120 may also be configured to perform a set operation on the resistance random access memory and perform a reset operation on the resistance random access memory on which the set operation is performed, to perturb the resistance value of the resistance random access memory. For clarity and consistency, the following embodiments will be described by taking an example in which a reset operation is performed and then a set operation is performed.
It should be noted that each resistance perturbation operation may also include performing a set operation and a reset operation multiple times, or performing a set operation and a reset operation single time. The embodiments of the present disclosure do not particularly limit the order and the number of set operations and reset operations in the resistance perturbation operation.
For example, as shown in fig. 1, in at least one embodiment of the present disclosure, the resistance perturbation circuit 120 includes a set operation subcircuit 121 and a reset operation subcircuit 122; the set operation sub-circuit 121 is configured to apply a set pulse to the resistance change memory to perform a set operation; the reset operation sub-circuit 122 is configured to apply a reset pulse to the resistance change memory to perform a reset operation.
It should be noted that, in the embodiment of the present disclosure, performing the resistance perturbation operation on the resistive random access memory is different from performing the conventional read/write operation on the resistive random access memory. First, the resistance value variation range of the resistance change memory corresponding to the resistance value disturbance operation is different from the resistance value variation range of the resistance change memory corresponding to the conventional read-write operation. For example, the resistance perturbation operation aims to make the resistance value of the resistive random access memory fluctuate in a small amplitude, and the resistance value of the resistive random access memory corresponding to the resistance perturbation operation changes in a small range, for example, 50kΩ to 100kΩ; the conventional read-write operation aims to make the resistance value of the resistive random access memory change obviously, and the conventional read-write operation corresponds to the resistance value of the resistive random access memory with a large change range, for example, 20k omega to 1M omega. Secondly, the amplitudes of the set pulse and the reset pulse corresponding to the resistance disturbance operation are different from the amplitudes of the set pulse and the reset pulse corresponding to the conventional read-write operation. For example, when the resistance perturbation operation is performed, the pulse width (set pulse and reset pulse) is 50 nanoseconds (ns), V for the set operation BL =1.6 volts (V), V WL ＝1.5V，V SL =0v; for reset operation, V SL ＝1.1V，V WL ＝5.0V，V BL =0v. For example, when performing conventional read and write operations, the pulse width is 50 nanoseconds (ns), V for set operations BL ＝2.5V，V WL ＝1.8V，V SL =0v; for reset operation, V SL ＝2.0V，V WL ＝5.0V，V BL ＝0V。
For example, fig. 3A illustrates a schematic diagram of the relationship of the set operation and the reset operation with the change in resistance value of the resistive random access memory, with the abscissa being the number of applied pulses, i.e., the number of pulses, and the ordinate being the normalized resistance value. In the example shown in fig. 3A, 200 reset operations and 200 set operations are consecutively performed on the resistive random access memory, i.e., 200 reset pulses and 200 set pulses are consecutively appliedPunching, wherein for reset operation V SL ＝1.3V，V WL ＝5.0V，V BL =0v; for the set operation, V BL ＝1.5V，V WL ＝1.7V，V SL =0v. As shown in fig. 3A, the reset operation increases the resistance value of the resistive random access memory, the set operation decreases the resistance value of the resistive random access memory, but the greater the resistance value of the resistive random access memory, the weaker the effect of the reset operation, and the stronger the effect of the set operation, and vice versa. In the embodiment of the disclosure, the characteristic that the resistance value of the resistive random access memory is nonlinear under the action of a set operation and a reset operation is called as the nonlinear characteristic of the resistive random access memory.
For example, fig. 3B illustrates a schematic diagram of the relationship of the resistance perturbation operation to the change in resistance value of the resistive random access memory, with the abscissa being the number of applied resistance perturbation operations (labeled as the number of cycles in fig. 3B) and the ordinate being the normalized resistance value. In the example shown in fig. 3B, 50 resistance perturbation operations are continuously performed on the resistance change memory, one resistance perturbation operation including one RESET operation and an immediately subsequent SET (SET) operation. As shown in fig. 3B, when the resistance value of the resistive random access memory is large (e.g., the resistance value is larger than the dark stripe section shown in fig. 3B) based on the nonlinear characteristics of the resistive random access memory, the effect of the set operation is stronger than the effect of the reset operation, and the resistance value disturbance operation causes the resistance value of the resistive random access memory to decrease (e.g., gradually decrease to the dark stripe section shown in fig. 3B); when the resistance value of the resistive random access memory is smaller (for example, the resistance value is smaller than the dark stripe section shown in fig. 3B), the effect of the set operation is weaker than the effect of the reset operation, and the resistance value perturbation operation causes the resistance value of the resistive random access memory to increase (for example, gradually increasing to the dark stripe section shown in fig. 3B); when the resistance value of the resistance change memory is in the intermediate range (for example, the resistance value is in the dark stripe section in fig. 3B), the effect of the set operation and the effect of the reset operation are equivalent, and the resistance value disturbance operation causes the resistance value of the resistance change memory to fluctuate in a small extent within the intermediate range (for example, fluctuate in the dark stripe section shown in fig. 3B). In the embodiments of the present disclosure, the above-described intermediate range is referred to as a resistance symmetric region of the resistive random access memory.
For example, in at least one embodiment of the present disclosure, the resistance perturbation circuit 120 is configured to perform n resistance perturbation operations on the resistive random access memory 110 such that the perturbed resistance value of the resistive random access memory is in a region of resistance symmetry.
For example, fig. 4A and 4B illustrate perturbed resistance values of a resistive memory, with the abscissa being the number of resistive perturbation operations applied (labeled as number of cycles in fig. 4A and 4B) and the ordinate being the resistance value (kΩ). In the example shown in fig. 4A, 10000 times of resistance perturbation operations are continuously performed on the resistance change memory, one resistance perturbation operation including one reset operation and one set operation immediately after the other, wherein for the reset operation, V SL ＝1.1V，V WL ＝5.0V，V BL =0v; for the set operation, V BL ＝1.6V，V WL ＝1.5V，V SL =0v. As shown in fig. 4A, the range of the resistance symmetric region (the dark stripe region shown in fig. 4A) is 50-100kΩ, and the disturbed resistance value of the resistive random access memory sometimes jumps out of the resistance symmetric region, but based on the nonlinear characteristics of the resistive random access memory, the disturbed resistance value of the resistive random access memory returns to the resistance symmetric region after several times of resistance disturbance operations. For example, fig. 4B intercepts a change in the resistance value of the resistive random access memory of fig. 4A. As shown in fig. 4B, when the resistance value of the resistive random access memory is greater than 1000kΩ, performing less than 10 times of resistive perturbation operations on the resistive random access memory, the resistance value of the resistive random access memory will be in the symmetric region of the resistance value (50-100 kΩ); when the resistance value of the resistive random access memory deviates from the symmetric region less (for example, the resistance value corresponding to the 7 th resistive perturbation operation in fig. 4B), the resistance value of the resistive random access memory returns to the symmetric region after only one resistive perturbation operation is performed on the resistive random access memory.
Therefore, in the embodiment of the disclosure, based on the nonlinear characteristic of the resistive random access memory, the disturbed resistance value of the resistive random access memory can return to the resistance value symmetrical region again after jumping out of the resistance value symmetrical region through the resistance value disturbance operation, that is, the random number generator in the embodiment of the disclosure can realize self calibration without an additional calibration circuit, so that the resistive random access memory has the advantages of small circuit area and low power consumption. In addition, the self-calibration can avoid the problem that the randomness of random numbers obtained by a subsequent coding circuit is low due to the fact that the disturbed resistance value of the resistance change memory is too small, namely the random number generator in the embodiment of the disclosure has the advantage of high reliability; the self-calibration can also avoid the problem that the speed of a subsequent encoding circuit for obtaining random numbers is slow due to overlarge disturbed resistance value of the resistance change memory, namely the random number generator in the embodiment of the disclosure has the advantage of high speed.
For example, in some embodiments, the resistance value of the resistive memory 110 may be in a region of resistance symmetry prior to performing a resistive perturbation operation on the resistive memory 110.
For example, fig. 5 is a schematic block diagram of one example of a random number generator provided by at least one embodiment of the present disclosure. As shown in fig. 5, the encoding circuit 130 includes a pressing sub-circuit 131, a speed measuring sub-circuit 132, and an output sub-circuit 133. The voltage applying sub-circuit 131 is coupled to the resistive random access memory 110 and configured to apply a control voltage to the word line terminal WL of the resistive random access memory 110 and a read voltage to the bit line terminal BL of the resistive random access memory 110 to control the source line terminal SL of the resistive random access memory 110 to output a current; the speed measurement sub-circuit 132 is coupled to the resistive random access memory 110 and configured to measure and output a stored energy speed while storing energy by using the current output from the source terminal SL of the resistive random access memory 110; the output sub-circuit 133 is coupled to the speed measurement sub-circuit 132 and is configured to generate a random number based on the stored energy speed. In this example, different perturbed resistance values will result in different currents, which in turn will result in different energy storage speeds, and thus different random numbers.
For example, fig. 6 is a schematic block diagram of a speed measurement sub-circuit provided by at least one embodiment of the present disclosure. As shown in fig. 6, the speed measurement sub-circuit 132 includes a tank sub-circuit 132-1, a comparison sub-circuit 132-2, a clock pulse generation sub-circuit 132-3, and a count sub-circuit 132-4; the energy storage sub-circuit 132-1 is coupled to the resistive random access memory 110 and is configured to store energy by using the current output by the source terminal SL of the resistive random access memory 110 to obtain an energy storage voltage; the comparing sub-circuit 132-2 is coupled to the energy storing sub-circuit 132-1 and is configured to compare the energy storing voltage with the reference voltage to obtain a voltage comparison result; the clock generation sub-circuit 132-3 is configured to generate clock pulses; the counting sub-circuit 132-4 is coupled to the comparing sub-circuit 132-2 and the clock generation sub-circuit 132-3, and is configured to count the clock and stop counting and output the current count value as the energy storage speed in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage.
For example, fig. 7 is a schematic diagram of one example of a random number generator provided by at least one embodiment of the present disclosure. In the example shown in fig. 7, the energy storage sub-circuit 132-1 may be implemented as a capacitor C (it should be noted that the energy storage sub-circuit 132-1 may include one or more capacitors), the comparison sub-circuit 132-2 may be implemented as a comparator, and the counting sub-circuit 132-4 may be implemented as a counter. As shown in fig. 7, a control voltage is applied to the word line terminal WL of the resistive random access memory and a read voltage is applied to the bit line terminal BL of the resistive random access memory to control the source line terminal SL of the resistive random access memory to output a current. The current charges the capacitor C, causing the stored voltage (i.e., the voltage at node 1) to rise gradually. The comparator compares the stored voltage with the reference voltage, and when the stored voltage exceeds the reference voltage, the output of the comparator outputs a voltage comparison result (i.e., the signal at node 2) that is inverted, for example, from the positive power supply voltage to the negative power supply voltage (e.g., 0V). The clock signal end CLK of the counter receives clock pulses, the enable end EN of the counter receives a voltage comparison result, and counts the clock pulses in response to the voltage comparison result being positive power supply voltage; and stopping counting in response to the voltage comparison result being the negative power supply voltage and outputting the current count value as the energy storage speed. For example, the pulse width of the read voltage and the control voltage is 1us, the read voltage is 0.2V, the control voltage is 5.0V, the capacitance value of the capacitor C is 10pF, the reference voltage is 0.1V, and the frequency of the clock pulse is 300MHz.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output sub-circuit 133 is configured to operate on a current count value to obtain an intermediate number, and generate a random number from the intermediate number. For example, the operation includes modulo 2 L Calculating, wherein the intermediate number is used as a random number and is 2 L And (3) carrying out number making, wherein L is a positive integer. For example, in some embodimentsL is 1, i.e., the operation includes a modulo-2 operation, the intermediate number is a 2-ary number, for example, the output sub-circuit 133 performs a modulo-2 operation on the current count value to obtain an intermediate number 0 or 1, which is a random number in the form of a 2-ary number. For example, in some embodiments, L is 2, i.e., the operation includes a modulo-4 operation, and the intermediate number is a 4-ary number, e.g., the output sub-circuit 133 modulo-4 operates on the current count value to obtain an intermediate number 0, 1, 2, or 3, which is a random number in the form of a 4-ary number.
For example, in a random number generator provided by at least one embodiment of the present disclosure, the counting sub-circuit 132-4 includes a 1-bit counter (i.e., a 1-bit counter) configured to output a 1-bit 2-ary number as a current count value, and the output sub-circuit 133 is configured to output the current count value as a random number.
For example, fig. 8 illustrates a schematic diagram of a random number generated by a random number generator provided by at least one embodiment of the present disclosure. Fig. 8 shows a random number array obtained by simultaneously performing the above-described resistance perturbation operation on a plurality of resistance random memories, and fig. 8 shows a 100 k-bit random number in which the black dots represent 1 and the white dots represent 0. As shown in fig. 8, the black dots and white dots are uniformly distributed, that is, the random numbers generated by the random number generator provided by the embodiment of the present disclosure have good randomness.
For example, fig. 9 is a schematic block diagram of another example of a random number generator provided by at least one embodiment of the present disclosure. As shown in fig. 9, the encoding circuit 230 includes a pressing sub-circuit 231, an analog-to-digital conversion sub-circuit 232, and an output sub-circuit 233. The voltage applying sub-circuit 231 is coupled to the resistive random access memory 210 and configured to apply a control voltage to a word line terminal of the resistive random access memory 210 and a read voltage to a bit line terminal of the resistive random access memory 210 to control a source line terminal output current of the resistive random access memory 210; the analog-to-digital conversion sub-circuit 232 is coupled to the resistive random access memory 210 and configured to convert the current output from the source terminal of the resistive random access memory 210 into a digital signal value; the output sub-circuit 233 is coupled to the analog-to-digital conversion sub-circuit 232 and is configured to generate a random number from the digital signal value. In this example, different perturbed resistance values will result in different currents, which in turn will result in different digital signal values, thereby generating different random numbers.
For example, fig. 10 is a schematic diagram of another example of a random number generator provided by at least one embodiment of the present disclosure. As shown in fig. 10, analog-to-digital conversion sub-circuit 232 may be implemented as a high-precision analog-to-digital converter. In the example shown in fig. 10, a control voltage is applied to the word line terminal WL of the resistive random access memory and a read voltage is applied to the bit line terminal BL of the resistive random access memory to control the source line terminal output current of the resistive random access memory. The high precision analog-to-digital converter converts the current into a multi-bit 2-ary digital signal value in a 2-ary form. For example, the pulse width of the read voltage and the control voltage is 1us, the read voltage is 0.2V, and the control voltage is 5.0V.
For example, the output sub-circuit 233 is configured to operate on the digital signal value to obtain an intermediate number, and generate a random number from the intermediate number. For example, the operation includes modulo 2 L Calculating, wherein the intermediate number is used as a random number and is 2 L And (3) carrying out number making, wherein L is a positive integer. For example, in some embodiments, L is 1, i.e., the operation comprises a modulo-2 operation, and the intermediate number is a 2-ary number, i.e., the output sub-circuit 233 performs a modulo-2 operation on the digital signal value to obtain an intermediate number 0 or 1, which is a random number in the form of a 2-ary number. For example, in some embodiments, L is 2, i.e., the operation includes a modulo-4 operation, and the intermediate number is a 4-ary number, i.e., the output sub-circuit 233 performs a modulo-4 operation on the digital signal value, and may result in an intermediate number of 0, 1, 2, or 3, where the intermediate number of 0, 1, 2, or 3 is a random number in the form of a 4-ary number.
For example, in some embodiments, output subcircuit 233 includes a register configured to register a digital signal value, and to take the lowest L bits of the digital signal value as the intermediate number. For example, as shown in fig. 10, the register is an N-bit register, and N is a positive integer equal to or greater than L. In the present embodiment, the process of the register registering the digital signal value and taking the lowest L bits of the digital signal value as the intermediate number corresponds to the modulo 2 L And (5) calculating.
For example, at least one embodiment of the present disclosure provides for the random number generator further to include a control circuit coupled to the resistance perturbation circuit and the encoding circuit configured to control the resistance perturbation circuit and the encoding circuit to generate a predetermined number of random numbers. For example, in the case where the random number generator includes one resistance random number memory, the control circuit is configured to control the resistance perturbation circuit and the encoding circuit to repeatedly perform corresponding resistance perturbation operations on the resistance random number memory to generate a predetermined number of random numbers. For example, in the case where the random number generator includes a plurality of resistance change memories, the control circuit is configured to control the resistance perturbation circuit and the encoding circuit to repeatedly perform the corresponding resistance perturbation operation on one of the plurality of resistance change memories to generate a predetermined number of random numbers, or to control the resistance perturbation circuit and the encoding circuit to repeatedly perform the corresponding resistance perturbation operation on the plurality of resistance change memories to generate a predetermined number of random numbers.
For example, the control circuitry may be implemented in software, hardware, firmware, or any combination thereof. In some embodiments, the control circuit includes code and programs stored in the memory; the processor may execute the code and program to implement some or all of the functions of the control circuitry described above, and in some embodiments the control circuitry may be a dedicated hardware device for carrying out some or all of the functions of the control circuitry described above.
In the random number generator provided by the embodiment of the disclosure, the random number generator generates the random number by applying perturbation to the resistive random access memory, causing random fluctuation of the resistance value of the resistive random access memory, and directly encoding the resistance value of the resistive random access memory. Since the resistance value of the resistive random number memory can be spontaneously controlled below a specific range (e.g., 100kΩ), random number encoding can be completed in a very short time (e.g., 1 microsecond), and thus the random number generator can operate at high speed (i.e., speed. Gtoreq.1 Mbit/s); in addition, the random number generator can realize self calibration by utilizing the nonlinearity of the resistance random number memory, and an additional calibration circuit is not needed, so that the design of the random number generator is simple and is very suitable for massive parallelism; finally, under small voltage operating conditions, the characteristics of the resistive random number memory are little affected by the environment and its durability (i.e., endance), and thus, the random number generator provided by the embodiments of the present disclosure has high reliability.
At least one embodiment of the present disclosure also provides a method for generating a random number, which may be used in the random number generator 100 provided in the embodiment of the present disclosure, and fig. 11 is a flowchart of the method for generating a random number. As shown in fig. 11, the random number generation method includes steps S310 and S320.
Step S310: performing n resistance perturbation operations on the first resistive random access memory to perturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a first perturbed resistance value, each of the n resistance perturbation operations including performing a set operation and a reset operation on the first resistive random access memory, n being a positive integer;
step S320: a first perturbed resistance value of the first resistive memory is encoded to generate a first random number.
For example, in a method provided by at least one embodiment of the present disclosure, each of the n resistance perturbation operations includes: and performing a reset operation on the first resistive random access memory, and performing a set operation on the first resistive random access memory on which the reset operation is performed, so as to disturb the resistance value of the first resistive random access memory.
For example, in a method provided by at least one embodiment of the present disclosure, performing a set operation includes: applying a set pulse to the first resistive random access memory; performing the reset operation includes: a reset pulse is applied to the first resistive random access memory.
For example, in a method provided in at least one embodiment of the present disclosure, performing n resistance perturbation operations on a first resistive random access memory to perturb a resistance value of the first resistive random access memory such that the resistance value of the first resistive random access memory becomes a first perturbed resistance value, includes: and executing n resistance perturbation operations on the first resistive random access memory so that the first perturbed resistance value of the first resistive random access memory is in a resistance symmetric region.
For example, fig. 12 is a flowchart of one example of a method for generating a random number provided in at least one embodiment of the present disclosure. In this example, a first perturbed resistance value of a first resistive memory is encoded to generate a first random number, including steps S321, S322, and S323.
S321: applying a control voltage to a word line terminal of the first resistive random access memory and a read voltage to a bit line terminal of the first resistive random access memory to control a source line terminal output current of the first resistive random access memory;
s322: storing energy by utilizing the current output by the source terminal of the first resistive random access memory to measure and output the energy storage speed;
s323: and generating a first random number according to the energy storage speed.
For example, in a method provided by at least one embodiment of the present disclosure, storing energy using a current output from a source terminal of a first resistive random access memory to measure and output an energy storage speed includes: storing energy by utilizing the current output by the source terminal of the first resistive random access memory to obtain energy storage voltage; comparing the stored energy voltage with a reference voltage to obtain a voltage comparison result; generating a clock pulse; the clock pulses are counted, and in response to the voltage comparison result indicating that the stored voltage exceeds the reference voltage, the counting is stopped and the current count value is output as the stored speed.
For example, in a method provided by at least one embodiment of the present disclosure, generating a first random number according to an energy storage speed includes: and calculating the current count value to obtain an intermediate number, and generating a first random number according to the intermediate number. For example, the operation includes modulo 2 L Calculating, wherein the intermediate number is used as a random number and is 2 L And (3) carrying out number making, wherein L is a positive integer.
For example, in a method provided by at least one embodiment of the present disclosure, encoding a first perturbed resistance value of a first resistive memory to generate a first random number includes: applying a control voltage to a word line terminal of the first resistive random access memory and a read voltage to a bit line terminal of the first resistive random access memory to control a source line terminal output current of the first resistive random access memory; converting the current output by the source terminal of the first resistive random access memory into a digital signal value; a first random number is generated from the digital signal value.
For example, in a method provided by at least one embodiment of the present disclosure, generating a first random number from a digital signal value includes: calculating the digital signal value to obtain an intermediate number according toThe intermediate number generates a first random number. For example, the operation includes modulo 2 L Calculating, wherein the intermediate number is used as a random number and is 2 L And (3) carrying out number making, wherein L is a positive integer.
For example, at least one embodiment of the present disclosure provides a method further comprising: performing m1 resistance perturbation operations on the second resistive random access memory to perturb the resistance value of the second resistive random access memory so that the resistance value of the second resistive random access memory becomes a second perturbed resistance value, each of the m1 resistance perturbation operations including performing a set operation and a reset operation on the second resistive random access memory, the first resistive random access memory and the second resistive random access memory being different, and m1 being a positive integer; a second perturbed resistance value of the second resistive memory is encoded to generate a second random number. That is, in embodiments of the present disclosure, a resistance perturbation operation may be performed on different resistive random access memories to generate a plurality of random numbers.
For example, at least one embodiment of the present disclosure provides a method further comprising: performing m2 resistance perturbation operations on the first resistive random access memory to perturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a third perturbed resistance value, each of the m2 resistance perturbation operations including performing a set operation and a reset operation on the first resistive random access memory, m2 being a positive integer; a third perturbed resistance value of the first resistive memory is encoded to generate a third random number. That is, in the embodiment of the present disclosure, the resistance perturbation operation may be repeatedly performed on the same resistance random access memory to generate a plurality of random numbers.
For example, in some embodiments, n, m1, and m2 may be the same (e.g., all 1), and n, m1, and m2 may also be different from one another. n, m1 and m2 may be set according to practical situations.
For example, the first random number and the second random number may together form a sequence of random numbers, and the first random number and the third random number may together form a sequence of random numbers.
For example, in a method provided by at least one embodiment of the present disclosure, the first perturbed resistance value and the third perturbed resistance value are different. For example, the first perturbed resistance value and the second perturbed resistance value may also be different. However, the present disclosure is not limited thereto, and any two of the first, second, and third perturbed resistance values may be the same, or the first, second, and third perturbed resistance values may be the same.
Regarding the technical effects of the random number generation method in the different embodiments, reference may be made to the technical effects of the random number generator provided in the embodiments of the present disclosure, and a detailed description thereof will be omitted.
The following points need to be described:
(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.
(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.
The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.
Claims (24)
1. A random number generator comprising:
a resistive random access memory;
a resistance perturbation circuit coupled to the resistive random access memory and configured to perform n resistance perturbation operations on the resistive random access memory to perturb a resistance value of the resistive random access memory such that the resistance value of the resistive random access memory becomes a perturbed resistance value and the perturbed resistance value is in a resistance symmetric region, wherein each of the n resistance perturbation operations comprises performing a set operation and a reset operation on the resistive random access memory, wherein n is a positive integer, wherein an effect of the set operation and an effect of the reset operation are equivalent in a case where the resistance value of the resistive random access memory is in the resistance symmetric region, and the resistance perturbation operation causes the resistance value of the resistive random access memory to fluctuate within the resistance symmetric region;
An encoding circuit, coupled to the resistive random access memory, is configured to encode a perturbed resistance value of the resistive random access memory to generate a random number.
2. The random number generator according to claim 1, wherein, when a resistance perturbation operation is performed once, the resistance perturbation circuit is configured to perform the reset operation on the resistance change memory, and perform the set operation on the resistance change memory on which the reset operation is performed, to perturb a resistance value of the resistance change memory.
3. The random number generator of claim 1, wherein the resistance perturbation circuit comprises a set operation subcircuit and a reset operation subcircuit; wherein,,
the set operation subcircuit is configured to apply a set pulse to the resistive switching memory to perform the set operation;
the reset operation subcircuit is configured to apply a reset pulse to the resistive switching memory to perform the reset operation.
4. A random number generator according to any one of claims 1-3, wherein the encoding circuit comprises a stress sub-circuit, a speed measurement sub-circuit and an output sub-circuit; wherein,,
the voltage application sub-circuit is coupled to the resistive random access memory and is configured to apply a control voltage to a word line end of the resistive random access memory and a read voltage to a bit line end of the resistive random access memory so as to control a source line end output current of the resistive random access memory;
The speed measurement sub-circuit is coupled to the resistive random access memory and is configured to measure and output an energy storage speed under the condition of energy storage by utilizing the current output by the source terminal of the resistive random access memory;
the output sub-circuit is coupled to the speed measurement sub-circuit and configured to generate the random number based on the stored energy speed.
5. The random number generator of claim 4, wherein the speed measurement sub-circuit comprises a power storage sub-circuit, a comparison sub-circuit, a clock pulse generation sub-circuit, and a count sub-circuit; wherein,,
the energy storage sub-circuit is coupled to the resistance change memory and is configured to store energy by utilizing the current output by the source terminal of the resistance change memory so as to obtain energy storage voltage;
the comparison sub-circuit is coupled to the energy storage sub-circuit and is configured to compare the energy storage voltage with a reference voltage to obtain a voltage comparison result;
the clock generation sub-circuit is configured to generate a clock;
the counting sub-circuit is coupled to the comparing sub-circuit and the clock pulse generating sub-circuit, configured to count the clock pulses, and responsive to the voltage comparison result indicating that the stored voltage exceeds the reference voltage, stop counting and output a current count value as the stored speed.
6. A random number generator according to claim 5, wherein the output sub-circuit is configured to operate on the current count value to derive an intermediate number and to generate the random number from the intermediate number.
7. The random number generator of claim 6, wherein the operation comprises modulo 2 L Calculating, wherein the intermediate number is used as the random number and is 2 L And (3) carrying out number making, wherein L is a positive integer.
8. The random number generator of claim 5, wherein said counting sub-circuit comprises a 1-bit counter configured to output a 1-bit 2-ary number as said current count value,
the output sub-circuit is configured to output the current count value as the random number.
9. A random number generator according to any one of claims 1-3, wherein the encoding circuit comprises a stress sub-circuit, an analog to digital conversion sub-circuit and an output sub-circuit; wherein,,
the voltage application sub-circuit is coupled to the resistive random access memory and is configured to apply a control voltage to a word line end of the resistive random access memory and a read voltage to a bit line end of the resistive random access memory so as to control a source line end output current of the resistive random access memory;
The analog-to-digital conversion sub-circuit is coupled to the resistance change memory and is configured to convert the current output by the source terminal of the resistance change memory into a digital signal value;
the output sub-circuit is coupled to the analog-to-digital conversion sub-circuit and is configured to generate the random number from the digital signal value.
10. The random number generator of claim 9, wherein the output sub-circuit is configured to operate on the digital signal value to obtain an intermediate number and to generate the random number from the intermediate number.
11. The random number generator of claim 10, wherein the operation comprises modulo 2 L Calculating, wherein the intermediate number is used as the random number and is 2 L And (3) carrying out number making, wherein L is a positive integer.
12. The random number generator of claim 11, wherein the output sub-circuit includes a register configured to register the digital signal value and take a lowest L bit of the digital signal value as the intermediate number.
13. A random number generator according to any of claims 1-3, further comprising a control circuit coupled to the resistance perturbation circuit and the encoding circuit, configured to control the resistance perturbation circuit and the encoding circuit to generate a predetermined number of random numbers.
14. A method of generating a random number, comprising:
performing n resistance perturbation operations on a first resistive random access memory to perturb a resistance value of the first resistive random access memory such that the resistance value of the first resistive random access memory becomes a first perturbed resistance value and the first perturbed resistance value is in a resistance symmetric region, wherein each of the n resistance perturbation operations comprises performing a set operation and a reset operation on the first resistive random access memory, wherein n is a positive integer, wherein in a case where the resistance value of the first resistive random access memory is in the resistance symmetric region, an effect of the set operation and an effect of the reset operation are equivalent, and the resistance perturbation operation causes the resistance value of the first resistive random access memory to fluctuate within the resistance symmetric region;
a first perturbed resistance value of the first resistive memory is encoded to generate a first random number.
15. The method of claim 14, wherein each of the n resistive perturbation operations comprises: the reset operation is performed on the first resistive random access memory, and the set operation is performed on the first resistive random access memory on which the reset operation is performed, so as to disturb the resistance value of the first resistive random access memory.
16. The method of claim 14, wherein performing the set operation comprises: applying a set pulse to the first resistive random access memory;
performing the reset operation includes: and applying a reset pulse to the first resistive random access memory.
17. The method of any of claims 14-16, wherein encoding the first perturbed resistance value of the first resistive memory to generate a first random number comprises:
applying a control voltage to a word line terminal of the first resistive random access memory and a read voltage to a bit line terminal of the first resistive random access memory to control a source line terminal output current of the first resistive random access memory;
storing energy by utilizing the current output by the source terminal of the first resistive random access memory to measure and output an energy storage speed;
and generating the first random number according to the energy storage speed.
18. The method of claim 17, wherein storing energy using the current output at the source terminal of the first resistive memory to measure and output an energy storage speed comprises:
storing energy by utilizing the current output by the source terminal of the first resistive random access memory to obtain energy storage voltage;
comparing the energy storage voltage with a reference voltage to obtain a voltage comparison result;
Generating a clock pulse;
and counting the clock pulses, stopping counting and outputting a current count value as the energy storage speed in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage.
19. The method of claim 18, wherein generating the first random number from the energy storage speed comprises: and calculating the current count value to obtain an intermediate number, and generating the first random number according to the intermediate number.
20. The method of any of claims 14-16, wherein encoding the first perturbed resistance value of the first resistive memory to generate a first random number comprises:
applying a control voltage to a word line terminal of the first resistive random access memory and a read voltage to a bit line terminal of the first resistive random access memory to control a source line terminal output current of the first resistive random access memory;
converting the current output by the source terminal of the first resistive random access memory into a digital signal value;
and generating the first random number according to the digital signal value.
21. The method of claim 20, wherein generating the first random number from the digital signal value comprises: and calculating the digital signal value to obtain an intermediate number, and generating the first random number according to the intermediate number.
22. The method of claim 14, further comprising:
performing m1 resistance perturbation operations on a second resistive random access memory to perturb a resistance value of the second resistive random access memory so that the resistance value of the second resistive random access memory becomes a second perturbed resistance value, wherein each resistance perturbation operation of the m1 resistance perturbation operations comprises performing a set operation and a reset operation on the second resistive random access memory, the first resistive random access memory and the second resistive random access memory being different, wherein m1 is a positive integer;
encoding a second perturbed resistance value of the second resistive memory to generate a second random number.
23. The method of claim 14, further comprising:
performing m2 resistance perturbation operations on the first resistive random access memory to perturb a resistance value of the first resistive random access memory such that the resistance value of the first resistive random access memory becomes a third perturbed resistance value, wherein each of the m2 resistance perturbation operations includes performing a set operation and a reset operation on the first resistive random access memory, wherein m2 is a positive integer;
encoding a third perturbed resistance value of the first resistive memory to generate a third random number.
24. The method of claim 23, wherein the first perturbed resistance value and the third perturbed resistance value are different.
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| CN202010366615.1A CN111562901B (en) | 2020-04-30 | 2020-04-30 | Random number generator and random number generation method |
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| CN106209099A (en) * | 2016-06-28 | 2016-12-07 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
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