CN114448434A

CN114448434A - Interstage gain error calibration method of pipeline ADC (analog to digital converter), circuit thereof and pipeline ADC

Info

Publication number: CN114448434A
Application number: CN202210110389.XA
Authority: CN
Inventors: 贾涵博; 郭轩; 吴旦昱; 周磊; 武锦; 刘新宇
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2022-05-06

Abstract

The invention provides an interstage gain error calibration method of a pipeline ADC (analog to digital converter), a circuit thereof and the pipeline ADC. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC and the sub-DAC, the residual difference voltage is maintained to be +/-1/2V_refWithin the method, the requirement on the linearity of the to-be-calibrated pipeline-level operational amplification signal can be greatly relieved. For a high-precision ADC, a better interstage gain calibration effect is realized. Meanwhile, the interstage gain error calibration method can also perform pseudo-random noise jitter injection in opposite directions simultaneously through the sub ADC and the sub DAC on the basis of completing interstage gain calibration, can achieve a good frequency spectrum scattering effect, and improvesThe overall dynamic range of the up-flow stage ADC.

Description

Interstage gain error calibration method of pipeline ADC (analog to digital converter), circuit thereof and pipeline ADC

Technical Field

The invention relates to the technical field of analog-to-digital conversion, in particular to an interstage gain error calibration method of a pipeline ADC (analog-to-digital converter), a circuit thereof and the pipeline ADC.

Background

Analog-to-digital converters (ADCs) are used to convert analog signals into digital signals and are widely used in the fields of wireless communication, high-end test equipment, image and voice processing, and the like. With the development of advanced processes and design technologies and the expansion of application scenarios, the demand for high-speed and high-precision ADCs is increasingly significant. Pipelined ADCs can achieve a good tradeoff between speed and accuracy, and thus pipeline, or pipeline-time interleaved architectures, are typically employed for ultra-high speed high accuracy ADCs. Fig. 1 shows a block diagram of a pipeline stage ADC and one of the pipeline stages in a channel. The working principle is as follows: firstly, the sampling and holding circuit samples the output signal of the previous stage pipeline stage or the signal of the analog input. And then the sub-ADC performs analog-to-digital conversion on the sampling signal to generate a corresponding digital code and sends the digital code to the sub-DAC of the pipeline stage. And then subtracting and amplifying the output signal of the sub-DAC from the input signal of the pipeline stage, and transmitting the amplified output signal to the next pipeline stage for repeating the process.

The pipeline stage ADC performs serial processing on the input analog signal through each pipeline stage, so that high-throughput fast conversion can be realized. However, a drawback of this architecture is that precise analog signal processing must be performed at each pipeline stage to ensure that the signal is not distorted at subsequent pipeline stages. In particular, precise gains are required between each pipeline stage. In a common switched capacitor type pipeline stage, the limited gain of the operational amplifier open loop in each pipeline stage can seriously affect the gain of the pipeline stage. Inter-stage gain errors can cause jumps in the transfer characteristics of the ADC, resulting in partial loss of the output code, thereby degrading DNL (Differential Nonlinearity), i.e., inter-stage gain errors can seriously affect the linearity of the overall ADC. And the open-loop gain of the operational amplifier is influenced by the temperature and voltage change, and accurate and effective calibration cannot be carried out by adopting a foreground calibration method.

Disclosure of Invention

The invention provides an interstage gain error calibration method of a production line ADC (analog to digital converter), a circuit thereof and the production line ADC, and a flow to be calibrated is determinedExtracting gain error between stages to maintain residual voltage at + -1/2V_refWithin the range, the requirement on the linearity of the operational amplification signal of the pipeline stage to be calibrated can be greatly relieved, the overflow phenomenon of residual voltage is avoided, and a better interstage gain calibration effect is realized; meanwhile, a better frequency spectrum scattering effect can be realized, and the whole dynamic range of the pipeline ADC is improved.

In a first aspect, the present invention provides a method for calibrating an inter-stage gain error of a pipeline ADC, where the pipeline ADC includes a multi-stage pipeline stage, the multi-stage pipeline stage includes a pipeline stage to be calibrated for completing n-bit digital code conversion and a pipeline stage located at a subsequent stage of the pipeline stage to be calibrated, and the pipeline stage to be calibrated includes a sub-ADC and a sub-DAC. The interstage gain error calibration method comprises the following steps:

inputting a sampling signal into a pipeline stage to be calibrated;

injection of m pairs of sub-ADC pseudo-random noise into sub-ADC with a value of +1/a_i*V_refAt the same time of the pseudo random noise, m pairs of sub-DAC pseudo random noise with the size of-1/b are injected into the sub-DAC_i*V_refThe pseudo random noise of (2); or, the I-th pair of pseudo random noise of m pairs of sub ADCs is injected into the sub ADCs with the size of-1/a_i*V_refThe sub-DAC is injected with m sub-DAC pseudo-random noise with the i-th pair size of +1/b_i*V_refThe pseudo random noise of (2); wherein m is a positive integer, the ith sub-ADC pseudo-random noise and the ith sub-DAC pseudo-random noise correspond to the same ith group of pseudo-random noise sequences, and a_i＝b_i*2^n-1；

According to m, n, ± 1/a_i*V_refDetermining a signal range available for calibration;

and when the sampling signal of the pipeline stage to be calibrated is in a signal range which can be used for calibration, determining the actual gain coefficient of the pipeline stage to be calibrated according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage and the ideal gain coefficient of the pipeline stage to be calibrated.

In the scheme, pseudo-random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC and the sub-DAC, and the actual gain coefficient of the pipeline stage to be calibrated is determined based on a sampling signal interval division mode of the pipeline stage to be calibrated, so that interstage gain errors are extracted. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC and the sub-DAC, the residual difference voltage is maintained to be +/-1/2V_refWithin the range, the requirement of linearity under the signal of the operational amplifier of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow is avoided. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also perform pseudo-random noise jitter injection in opposite directions through the sub ADC and the sub DAC on the basis of completing interstage gain calibration, so that a good spectrum scattering effect can be achieved, and the whole dynamic range of the pipelined ADC is enlarged.

In a specific embodiment, in terms of m, n, ± 1/a_i*V_refDetermining a range of signals available for calibration includes: according to m, n, ± 1/a_i*V_refAnd calculating the signal range of the sampling signal influenced by the pseudo random noise of the ith sub-DAC only and not influenced by the pseudo random noise of the ith sub-ADC, and taking the signal range as the signal range which can be used for calibration. The sampling signal input into the pipeline stage to be calibrated is only affected by the injection of the sub-DAC pseudo-random noise sequence. Calibration may be initiated when the sampled signal is within a signal range that is available for calibration. Namely, only the sampling signal which can be used in the calibration range is subjected to corresponding correlation operation, which is equivalent to the case that only the sub-DAC injects the pseudo-random noise sequence, so that the inter-stage gain coefficient can be extracted. During calibration, the equivalent injection is a pseudo-random noise sequence unrelated to the sampling signal, so that the operation of the sub-ADCs and the whole pipeline ADC is not interfered. Because the pseudo-random noise sequence passes through the same path as the sub-DAC signal, the same non-ideal condition can be met, so that the actual gain coefficient of the pipeline stage to be calibrated can be detected, and the inter-stage gain error can be extracted.

In a specific embodiment, m is 1; in accordance withAccording to m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration is specifically:

wherein k is 0, ± 1, ± 2, ·, and ± (2)^n-1-1). The circuit structure of the running algorithm is simplified by injecting only one pair of pseudo random noise to the sub ADC and the sub DAC.

In a specific embodiment, m > 1; according to m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration is specifically:

wherein k is 0, ± 1, ± 2, ·, and ± (2)^n-1-1). At least two pairs of pseudo-random noise are injected into the sub-ADC and the sub-DAC simultaneously, so that the spectrum scattering effect can be improved, and the whole dynamic range of the pipeline ADC is further improved.

In a specific embodiment, an LMS algorithm is used to determine an actual gain coefficient of the pipeline stage to be calibrated according to an ideal digital code of the i-th group of pseudo-random noise sequences corresponding to the weights, a post-stage digital output code output by the post-stage pipeline stage, and an ideal gain coefficient of the pipeline stage to be calibrated. By adopting an LMS convergence iteration mode and combining a pseudo-random noise jitter injection technology and related operation, the interstage gain error is extracted, and the accuracy of the obtained actual gain coefficient of the pipeline stage to be calibrated is improved.

In a specific embodiment, determining the actual gain coefficient of the pipeline stage to be calibrated by using the LMS algorithm includes: performing iterative operation according to the following formula:

ra_es[j+1]＝ra_es[j]+μ*D_PN*(D_R-D_PN*ra_es[j]/ra)

wherein j represents the number of iterations counted from 0; ra represents an ideal interstage gain coefficient; ra (ra)_esRepresenting estimated inter-stage gain coefficient, ra_es[j]And ra_es[j+1]Respectively representing an estimated interstage gain coefficient generated by the jth iteration and an estimated interstage gain coefficient generated by the j +1 th iteration; d_PNAn ideal digital code representing the corresponding weight of the ith group of pseudo-random noise sequences; d_RA post-stage digital output code output by the post-stage pipeline stage; μ denotes the convergence step factor. And ra is judged after each iterative calculation_es[j+1]And ra_es[j]Whether the difference value between the two is less than a set threshold value; if not, continuing to perform the next iteration; otherwise, will ra_es[j+1]As the actual gain coefficient of the pipeline stage to be calibrated. By judging ra once after each iteration_es[j+1]And ra_es[j]And if the difference value is smaller than the set threshold value, stopping iterative computation only when the difference value is smaller than the set threshold value, thereby improving the accuracy of the obtained actual gain coefficient of the pipeline stage to be calibrated.

In a specific embodiment, the inter-stage gain error calibration method further includes: according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the ideal gain coefficient and the actual gain coefficient of the pipeline stage to be calibrated, the post-stage digital output code output by the post-stage pipeline stage is calibrated to obtain the calibrated post-stage digital output code, and the post-stage digital output code output by the post-stage pipeline stage is calibrated by using the actual gain coefficient of the pipeline stage to be calibrated, so that the analog-to-digital conversion accuracy of the pipeline stage ADC is improved.

In a second aspect, the present invention further provides an inter-stage gain error calibration circuit of a pipeline ADC, where the pipeline ADC includes a multi-stage pipeline stage, the multi-stage pipeline stage includes a pipeline stage to be calibrated for completing n-bit digital code conversion, and a pipeline stage located at a subsequent stage of the pipeline stage to be calibrated, and the pipeline stage to be calibrated includes a sub-ADC and a sub-DAC. The interstage gain error calibration circuit comprises: the device comprises a sample-hold module, a pseudo-random noise injection module, a calibration signal determination module and a gain coefficient calibration module. The sampling and holding module is used for acquiring a sampling signal and inputting the sampling signal into a pipeline stage to be calibrated. The pseudo-random noise injection module is used for injecting m pairs of sub-ADCs into the sub-ADCsThe magnitude of the ith pair of noise is +1/a_i*V_refAt the same time of the pseudo random noise, m pairs of sub-DAC pseudo random noise with the size of-1/b are injected into the sub-DAC_i*V_refThe pseudo random noise of (2); or the pseudo random noise injection module is used for injecting m pairs of sub-ADC pseudo random noise into the sub-ADC, wherein the size of the ith pair is-1/a_i*V_refThe sub-DAC is injected with m sub-DAC pseudo-random noise with the i-th pair size of +1/b_i*V_refThe pseudo random noise of (2); wherein m is a positive integer, the ith sub-ADC pseudo-random noise and the ith sub-DAC pseudo-random noise correspond to the same ith group of pseudo-random noise sequences, and a_i＝b_i*2^n-1. The calibration signal determining module is used for determining the calibration signal according to m, n, +/-1/a_i*V_refThe signal range available for calibration is determined. And the gain coefficient calibration module is used for determining the actual gain coefficient of the pipeline stage to be calibrated according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage and the ideal gain coefficient of the pipeline stage to be calibrated when the sampling signal input into the pipeline stage to be calibrated is in the signal range available for calibration.

In the scheme, pseudo-random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC and the sub-DAC, and the actual gain coefficient of the pipeline stage to be calibrated is determined based on a sampling signal interval division mode of the pipeline stage to be calibrated, so that interstage gain errors are extracted. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC and the sub-DAC, the residual difference voltage is maintained to be +/-1/2V_refWithin the range, the requirement of linearity under the signal of the operational amplifier of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow is avoided. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also perform pseudo-random noise jitter injection in opposite directions simultaneously through the sub ADC and the sub DAC on the basis of completing interstage gain calibration, so that a good frequency spectrum scattering effect can be achieved, and the whole dynamic range of the pipeline stage ADC is enlarged.

In a specific embodiment, the sub-ADC includes: is composed of 2ⁿ-2 comparators comprising (n-1) 5-bit pipelined ADC and two additional thresholds of +/- (2)ⁿ-1)/2ⁿ*V_refThe comparator of (1). The sub-DAC includes: is composed of 2ⁿThe device comprises an (n-1) 5bit pipeline DAC consisting of 2 capacitors and two additional capacitors with the same size as the capacitance value. The pseudo-random noise injection module injects m pairs of sub-ADC pseudo-random noise with the sizes of +/-1/a respectively to the i-th pairs of the sub-ADC by changing the threshold of the sub-ADC comparator_i*V_refOf the pseudo random noise. A pseudo-random noise capacitor is also arranged in the pseudo-random noise injection module; the pseudo-random noise injection module injects m pairs of sub-DAC pseudo-random noise with the sizes of +/-1/b respectively to the sub-DAC through the pseudo-random noise capacitor_i*V_refOf the pseudo random noise. Pseudo-random noise jitter injection in opposite directions is simultaneously performed from the sub-ADC and the sub-DAC, two ends of a transmission curve of a pipeline stage to be calibrated can be folded, and residual voltage overflow caused by the pseudo-random noise injection of the sub-DAC is avoided.

In one embodiment, the calibration signal determination module determines the calibration signal based on m, n, ± 1/a_i*V_refAnd calculating the signal range of the sampling signal influenced by the pseudo random noise of the ith sub-DAC only and not influenced by the pseudo random noise of the ith sub-ADC, and taking the signal range as the signal range which can be used for calibration. The sampling signal input into the pipeline stage to be calibrated is only affected by the injection of the sub-DAC pseudo-random noise sequence. Calibration may be initiated when the sampled signal is within a signal range that is available for calibration. Namely, only the sampling signal which can be used in the calibration range is subjected to corresponding correlation operation, which is equivalent to the case that only the sub-DAC injects the pseudo-random noise sequence, so that the inter-stage gain coefficient can be extracted. During calibration, the pseudo-random noise sequence irrelevant to the sampling signal is equivalently injected, so that the operation of the sub-ADC and the whole pipeline ADC is not interfered. Because the pseudo-random noise sequence passes through the same path as the sub-DAC signal, the same non-ideal condition can be met, so that the actual gain coefficient of the pipeline stage to be calibrated can be detected, and the inter-stage gain error can be extracted.

In a specific embodiment, m is 1; the calibration signal determining module determines the calibration signal according to m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration is specifically:

In a specific embodiment, m > 1; the calibration signal determining module determines the calibration signal according to m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration is specifically:

wherein k is 0, ± 1, ± 2^n-1-1). At least two pairs of pseudo-random noise are injected into the sub-ADC and the sub-DAC simultaneously, so that the spectrum scattering effect can be improved, and the whole dynamic range of the pipeline ADC is further improved.

In a specific embodiment, the gain coefficient calibration module determines the actual gain coefficient of the pipeline stage to be calibrated by using an LMS algorithm according to the ideal digital code of the corresponding weight of the i-th group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated. By adopting an LMS convergence iteration mode and combining a pseudo-random noise jitter injection technology and related operation, the interstage gain error is extracted, and the accuracy of the obtained actual gain coefficient of the pipeline stage to be calibrated is improved.

In one specific embodiment, the gain factor calibration module comprises: an LMS algorithm iteration module and a threshold judgment module. The LMS algorithm iteration module is used for carrying out iteration operation according to the following formula:

ra_es[j+1]＝ra_es[j]+μ*D_PN*(D_R-D_PN*ra_es[j]/ra)

wherein j represents the number of iterations counted from 0; ra represents an ideal interstage gain coefficient; ra (ra)_esRepresenting estimated inter-stage gain coefficient, ra_es[j]And ra_es[j+1]Respectively representing an estimated interstage gain coefficient generated by the jth iteration and an estimated interstage gain coefficient generated by the j +1 th iteration; d_PNAn ideal digital code representing the corresponding weight of the ith group of pseudo-random noise sequences; d_RA post-stage digital output code output by the post-stage pipeline stage; μ denotes the convergence step factor. The threshold judgment module is used for judging ra after each iterative computation_es[j+1]And ra_es[j]Whether the difference value between the two is less than a set threshold value; if not, the next iteration is continued by the LMS algorithm iteration module; otherwise, the threshold judging module will ra_es[j+1]As the actual gain coefficient of the pipeline stage to be calibrated. By judging ra once after each iteration_es[j+1]And ra_es[j]And if the difference value between the two values is smaller than the set threshold value, stopping iterative computation only when the difference value is smaller than the set threshold value, thereby improving the accuracy of the obtained actual gain coefficient of the pipeline stage to be calibrated.

In a specific embodiment, the interstage gain error calibration circuit further includes a digital output code calibration module, where the digital output code calibration module is configured to calibrate a post-stage digital output code output by a post-stage pipeline stage according to an ideal digital code weighted correspondingly by the ith group of pseudo-random noise sequences, an ideal gain coefficient and an actual gain coefficient of the pipeline stage to be calibrated, to obtain the calibrated post-stage digital output code, and calibrate the post-stage digital output code output by the post-stage pipeline stage by using the actual gain coefficient of the pipeline stage to be calibrated, so as to improve analog-to-digital conversion accuracy of the pipeline stage ADC.

In a third aspect, the present invention further provides a pipeline ADC, where the pipeline ADC includes a multi-stage pipeline stage, and the multi-stage pipeline stage includes a pipeline stage to be calibrated for completing n-bit digital code conversion, and a pipeline stage located at a stage subsequent to the pipeline stage to be calibrated, where the pipeline stage to be calibrated includes a sub-ADC and a sub-DAC. The pipeline ADC also comprises the above-mentionedAn interstage gain error calibration circuit of any pipeline ADC. Pseudo-random noise jitter injection in opposite directions is carried out simultaneously from the sub-ADC and the sub-DAC, and the actual gain coefficient of the pipeline stage to be calibrated is determined based on a sampling signal interval division mode of the pipeline stage to be calibrated, so that inter-stage gain errors are extracted. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC and the sub-DAC, the residual difference voltage is maintained to be +/-1/2V_refWithin the range, the requirement of linearity under the signal of the operational amplifier of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow is avoided. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also perform pseudo-random noise jitter injection in opposite directions simultaneously through the sub ADC and the sub DAC on the basis of completing interstage gain calibration, so that a good frequency spectrum scattering effect can be achieved, and the whole dynamic range of the pipeline stage ADC is enlarged.

Drawings

FIG. 1 is a block diagram of a pipeline stage ADC and one of the pipeline stages in a channel;

fig. 2 is a flowchart of an inter-stage gain error calibration method for a pipeline ADC according to an embodiment of the present invention;

fig. 3 is a block diagram of a part of modules of an inter-stage gain error calibration circuit of a pipeline ADC according to an embodiment of the present invention;

fig. 4 is a block diagram of a part of an inter-stage gain error calibration circuit of another pipelined ADC according to an embodiment of the present invention;

fig. 5 is a circuit block diagram of a sub-ADC in a pipeline stage to be calibrated according to an embodiment of the present invention;

fig. 6 is a transmission curve diagram when the sub-DAC and the sub-ADC perform pseudo random noise injection simultaneously according to an embodiment of the present invention;

fig. 7 is a graph of the transmission curve of the prior art showing only the injection of pseudo random noise by the sub-DAC;

fig. 8 is a graph of the transmission curve of the prior art showing only the injection of pseudo random noise by the sub-ADC;

fig. 9 is a simulated spectrum diagram of an inter-stage gain after calibration by using the inter-stage gain error calibration method of the pipeline ADC according to the embodiment of the present invention;

fig. 10 is a graph of inter-stage gain simulation spectrum when the pipeline ADC is not calibrated for inter-stage gain error.

Reference numerals:

10-to-be-calibrated pipeline stage 11-sub ADC111- (n-1). 5-bit pipeline stage ADC

112-threshold of + (2)ⁿ-1)/2ⁿ*V_refComparator 113-threshold of- (2)ⁿ-1)/2ⁿ*V_refComparator (D)

12-sub DAC 20-post stage pipeline stage 30-pseudo random noise injection module

40-gain factor calibration module 50-digital output code calibration module

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

To facilitate understanding of the inter-stage gain error calibration method of the pipeline ADC according to the embodiment of the present invention, an application scenario of the inter-stage gain error calibration method according to the embodiment of the present invention is first described below, where the inter-stage gain error calibration method is applied to a pipeline ADC, the pipeline ADC includes a multi-stage pipeline stage, and referring to fig. 3, the multi-stage pipeline stage includes a pipeline stage 10 to be calibrated for completing n-bit digital code conversion and a subsequent pipeline stage 20 located at a subsequent stage of the pipeline stage to be calibrated, where the pipeline stage 10 to be calibrated includes a sub-ADC 11 and a sub-DAC 12, and the inter-stage gain error calibration method is used for calibrating an inter-stage gain coefficient of the pipeline stage 10 to be calibrated. The inter-stage gain error calibration method of the pipeline ADC is described in detail below with reference to the accompanying drawings.

Referring to fig. 2 and fig. 3, the method for calibrating inter-stage gain errors of a pipeline ADC according to an embodiment of the present invention includes:

step 10: inputting a sampling signal into the pipeline stage 10 to be calibrated;

step 20: injection of m pairs of sub-ADC pseudo-random noise into sub-ADC 11 with a magnitude of +1/a_i*V_refAt the same time as the pseudo random noise of (1), m pairs of sub-DAC pseudo random noise of-1/b size are injected into the sub-DAC 12_i*V_refThe pseudo random noise of (2); alternatively, the sub-ADC 11 is injected with m pairs of sub-ADC pseudo-random noise of size-1/a_i*V_refIs injected into the sub-DAC 12 with m pairs of sub-DAC pseudo random noise of +1/b_i*V_refThe pseudo random noise of (2); wherein m is a positive integer, the ith sub-ADC pseudo-random noise and the ith sub-DAC pseudo-random noise correspond to the same ith group of pseudo-random noise sequences, and a_i＝b_i*2^n-1；

Step 30: according to m, n, ± 1/a_i*V_refDetermining a signal range available for calibration;

step 40: when the sampling signal input into the pipeline stage 10 to be calibrated is in the signal range available for calibration, the actual gain coefficient of the pipeline stage 10 to be calibrated is determined according to the ideal digital code of the corresponding weight of the i-th group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage 20, and the ideal gain coefficient of the pipeline stage 10 to be calibrated.

In the above scheme, pseudo random noise jitter injection in opposite directions is performed simultaneously from the sub-ADC 11 and the sub-DAC 12, and an actual gain coefficient of the pipeline stage 10 to be calibrated is determined based on a sampling signal interval division mode input to the pipeline stage 10 to be calibrated, so as to extract an inter-stage gain error. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC 11 and the sub-DAC 12, the residual voltage is maintained to be +/-1/2V_refWithin the range, the requirement of linearity under the signal to be calibrated for the pipeline-level operational amplification can be greatly relieved, and the residual error caused by pseudo-random noise injection of the sub-DAC 12 can be avoidedA voltage overflow phenomenon. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also perform pseudo-random noise jitter injection in opposite directions through the sub-ADC 11 and the sub-DAC 12 on the basis of completing interstage gain calibration, so that a good spectrum scattering effect can be achieved, and the whole dynamic range of the pipeline stage ADC is improved. The above steps will be described in detail with reference to the accompanying drawings.

First, referring to fig. 2 and 3, a sampling signal is input into the pipeline stage 10 to be calibrated. The sampling signal may be from an output signal output by a previous stage of the pipeline stage 10 to be calibrated, or may be from an analog signal of a certain acquisition point directly acquired from the analog signal. V as shown in FIG. 3_inRepresenting an input sampled signal; v as shown in FIG. 3_resAnd the output signal of the pipeline stage 10 to be calibrated, which is output to the subsequent pipeline stage 20 of the subsequent stage after processing, is used as the input signal of the subsequent pipeline stage 20.

Next, referring to fig. 2 and 3, pseudo random noise dither injection in opposite directions is simultaneously performed from the sub-ADC 11 and the sub-DAC 12. Specifically, m pairs of sub-ADC pseudo-random noise can be injected into each of the sub-ADC 11 and the sub-DAC 12, where m is a positive integer of 1, 2, 4, 5, or the like. Each pair of sub-ADC pseudo-random noise comprises two pseudo-random noises with mutually opposite numbers, for example, the i-th sub-ADC pseudo-random noise of m pairs of sub-ADC pseudo-random noises can comprise +1/a_i*V_refAnd-1/a_i*V_refI is in particular any positive integer less than or equal to m. Each pair of sub-DAC pseudo-random noise comprises two pseudo-random noises with mutually opposite numbers, for example, the i-th sub-DAC pseudo-random noise of m pairs of sub-DAC pseudo-random noises can comprise +1/b_i*V_refAnd-1/b_i*V_refI is in particular any positive integer less than or equal to m. The ith sub-ADC pseudo-random noise and the ith sub-DAC pseudo-random noise correspond to the same ith group of pseudo-random noise sequences, i.e. the ith group of pseudo-random noise sequences are controlled simultaneouslyThe ith sub-ADC pseudo-random noise and the ith sub-DAC pseudo-random noise are injected into the sub-ADC 11 and the sub-DAC 12, respectively. And a is_iAnd b_iThe following relationship is also satisfied: a is_i＝b_i*2^n-1。

When the i-th sub-ADC pseudo random noise and the i-th sub-DAC pseudo random noise are injected into the sub-ADC 11 and the sub-DAC 12, respectively, the positive and negative directions of the pseudo random noise injected into the sub-ADC 11 and the sub-DAC 12 are different according to the different binary values jumped out by the i-th group of pseudo random noise sequences. The main direction injection may be defined such that the magnitude of the pseudo random noise injected into the sub ADC11 is positive and the magnitude of the pseudo random noise injected into the sub ADC11 is negative, and the main direction injection may be defined as a positive direction. It is of course also possible to define the positive and negative directions separately by the magnitude of the pseudo random noise injected into the sub-DAC 12. Specifically, when the binary number jumped out by the ith group of pseudo random noise sequences is the first value, the ith pair of pseudo random noise is injected into the sub ADC11, wherein the size of the i pair of pseudo random noise is +1/a_i*V_refAnd has a magnitude of +1/a in injecting the i-th pair of pseudo random noise into the sub-ADC 11_i*V_refAt the same time as the pseudo random noise of (1) is injected into the sub-DAC 12, the i < th > sub-DAC is given a pseudo random noise of-1/b_i*V_refOf the pseudo random noise. When the binary number of the ith group of pseudo random noise sequences is the second value, m pairs of sub ADC pseudo random noise with the size of-1/a are injected into the sub ADC11_i*V_refAnd a size of-1/a in the i-th pair injecting m pairs of sub-ADC pseudo random noise into the sub-ADC 11_i*V_refIs injected into the sub-DAC 12 with m pairs of sub-DAC pseudo random noise of +1/b_i*V_refOf the pseudo random noise. Thereby enabling simultaneous opposite direction pseudo random noise dither injection from sub-ADC 11 and sub-DAC 12.

It should be additionally noted that each pair of m pairs of sub-ADC pseudo random noise and m pairs of sub-DAC pseudo random noise are simultaneously injected into the sub-ADC 11 and the sub-DAC 12, respectively, according to the injection manner described above.

In the following, n is 3, m is 1, 1/a_i＝1/16、1/b _i1/4, an example of an injection method is described. At this time, the transmission curve when the direction of injecting pseudo random noise to the sub-DAC 12 is opposite to the direction of injecting pseudo random noise to the sub-ADC 11 is shown in fig. 6, and it can be seen that the injection mode can fold both ends of the transmission curve of the pipeline stage 10 to be calibrated, thereby avoiding the residual voltage overflow phenomenon caused by pseudo random noise injection of the sub-DAC 12.

FIG. 7 shows the injection of pseudo random noise at the sub-DAC only, with injection level of 2 and + -1/4V_refThe transmission profile of time. It can be seen that the middle part of the transmission curve has an up-and-down shift due to the injection of pseudo random noise, so that the original middle compression is within + -1/2V_refThe transmission curve is expanded to +/-3/4V_ref. Meanwhile, when the range of the left end of the transmission curve is in the negative direction (downwards), the pseudo-random noise exceeds-V_refThe risk of (c). In the same way, when the pseudo random noise is in the forward direction (upward direction), the range of the right end of the transmission curve exceeds V_refThe risk of (c). This may cause the residual voltage output by the stage to exceed the quantization range of the next pipeline stage, resulting in non-linearity of the conversion.

FIG. 8 shows the injection of pseudo random noise at the sub-ADC only, with injection level of 2 and magnitude of + -1/16V in the prior art_refThe transmission profile of time. It can be seen that, at this time, the transmission curve jump point is shifted to the left or right under the influence of the injection of pseudo random noise, which also makes the original intermediate compression within + -1/2V_refThe transmission curve is expanded to +/-3/4V_refThe requirement for linearity of the to-be-calibrated pipeline-level operational amplification signal is greatly increased.

In contrast, the injection method described above in the present application can maintain the residual voltage at ± 1/2 × V, as compared with the two injection methods shown in the prior art shown in fig. 7 and 8_refWithin the range, the requirement of linearity under the signal of the operational amplifier of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow is avoided. And the present application injects more logarithm of pseudo random noise to the sub-ADC 11 and the sub-DAC 12 than the injection shown in fig. 7 and 8Compared with the mode, the method can achieve a better frequency spectrum scattering effect and improve the whole dynamic range of the pipeline ADC.

Next, referring to FIG. 2 and FIG. 3, according to m, n, ± 1/a_i*V_refThe signal range available for calibration is determined. The calibration procedure is only initiated when the sampled signal received by pipeline stage 10 to be calibrated is within the signal range available for calibration. And when the sampling signal received by the pipeline stage 10 to be calibrated is not within the signal range available for calibration, the calibration procedure is not started. In terms of m, n, ± 1/a_i*V_refWhen determining the signal range available for calibration, the values may be in terms of m, n, ± 1/a_i*V_refAnd calculating the signal range of the sampling signal influenced by the pseudo random noise of the ith sub-DAC only and not influenced by the pseudo random noise of the ith sub-ADC, and taking the signal range as the signal range which can be used for calibration. Taking the transmission curve shown in fig. 6 as an example, it can be seen that the input sampling signal can be correspondingly screened, and when the size of the sampling signal is limited within the range of the arrow in fig. 6, the input sampling signal is only affected by the sub-DAC pseudo random noise injection, but not affected by the sub-ADC pseudo random noise injection. When the sampling signal is located in the range, calibration can be carried out, and interstage gain calibration is achieved. In this way, the sampling signal input to the pipeline stage 10 to be calibrated is only affected by the injection of the sub-DAC pseudo-random noise sequence. Calibration may be initiated when the sampled signal is within a signal range that is available for calibration. That is, only the sampling signal within the calibration range is subjected to corresponding correlation operation, which is equivalent to the case where only the sub-DAC 12 injects the pseudo-random noise sequence, so that the inter-stage gain coefficient can be extracted. During calibration, the equivalent injection is a pseudo-random noise sequence that is uncorrelated with the sampling signal so as not to interfere with the operation of the sub-ADC 11 and the entire pipeline ADC. Since the pseudo-random noise sequence will encounter the same non-ideal situation through the same path as the sub-DAC 12 signal, the actual gain coefficient of the pipeline stage 10 to be calibrated can be detected and the inter-stage gain error can be extracted.

Specifically, when m is 1, the terms m, n, ± 1/a_i*V_refIs determined to be available forThe calibrated signal range may specifically be:

wherein k is 0, ± 1, ± 2^n-1-1). By injecting only one pair of pseudo random noise to the sub-ADC 11 and the sub-DAC 12, the circuit structure for running the algorithm is simplified.

In combination with n-3, m-1, 1/a as shown above_i＝1/16、1/b_iFor example 1/4, the range of the input signal injected by the sub-DAC pseudo random noise only is statistically calculated as follows:

TABLE 1-statistics of signal ranges that can be used for calibration

When m is more than 1, m can be any positive integer not less than 2, 3, 4, 5, 6, 7, 8, etc., in this case, m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration may specifically be:

wherein k is 0, ± 1, ± 2^n-1-1). I.e. the additive effect of the multiple pairs of sub-ADC pseudo random noise and sub-DAC pseudo random noise is taken into account, resulting in the above mentioned signal range that can be used for calibration. In addition, at least two pairs of pseudo random noise are injected into the sub-ADC 11 and the sub-DAC 12 simultaneously, so that the logarithm of the pseudo random noise injected into the sub-ADC 11 and the sub-DAC 12 is increased, the spectrum dispersion effect can be improved, and the overall dynamic range of the pipeline ADC is further improved.

Next, referring to fig. 2, 3 and 4, after each sampling signal is received, it is determined whether the sampling signal is within the obtained signal range available for calibration. If not, the calibration procedure is not initiated. If the sampling signal input into the pipeline stage 10 to be calibrated is within the signal range available for calibration, a calibration procedure is started, and the actual gain coefficient of the pipeline stage 10 to be calibrated is determined according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage 20 and the ideal gain coefficient of the pipeline stage 10 to be calibrated.

Specifically, when determining the actual gain coefficient of the pipeline stage 10 to be calibrated according to the ideal digital code of the corresponding weight of the i-th group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage 20, and the ideal gain coefficient of the pipeline stage 10 to be calibrated, an LMS iterative algorithm may be used. By adopting an LMS convergence iteration mode and combining a pseudo-random noise jitter injection technology and related operation, the inter-stage gain error is extracted, and the accuracy of the obtained actual gain coefficient of the pipeline stage 10 to be calibrated is improved.

Specifically, when the LMS algorithm is used to determine the actual gain coefficient of the pipeline stage 10 to be calibrated, referring to fig. 4, iterative operation may be performed according to the following formula:

ra_es[j+1]＝ra_es[j]+μ*D_PN*(D_R-D_PN*ra_es[j]/ra)

wherein j represents the number of iterations counted from 0; ra represents an ideal interstage gain coefficient; ra (ra)_esRepresenting estimated inter-stage gain coefficient, ra_es[j]And ra_es[j+1]Respectively representing an estimated interstage gain coefficient generated by the jth iteration and an estimated interstage gain coefficient generated by the j +1 th iteration; d_PNAn ideal digital code representing the corresponding weight of the ith group of pseudo-random noise sequences; d_RA post-stage digital output code output by the post-stage pipeline stage 20; mu represents a convergence stepping factor, and controls the accuracy and the convergence time of the algorithm. As shown at D in FIG. 4_o ^B＝D_R-D_PN*ra_es[j]/ra, as ra' in fig. 4, represents the actual gain coefficient of the pipeline stage 10 to be calibrated, D in fig. 4_{PN_es}＝D_PN*ra_es[j]And/ra. Namely, an initial ra is first set_es[0]Substituting the obtained value into the iterative formula, and calculating to obtain ra_es[1]And then performing iterative computation.

And at each timeAfter iterative computation, ra can also be judged_es[j+1]And ra_es[j]Whether the difference value between the two is less than a set threshold value; if not, continuing to perform the next iteration; otherwise, will ra_es[j+1]As the actual gain factor of the pipeline stage 10 to be calibrated. By judging ra once after each iteration_es[j+1]And ra_es[j]Whether the difference between the values is smaller than the set threshold value or not is judged, and the iterative computation is stopped only when the difference is smaller than the set threshold value, so that the accuracy of the obtained actual gain coefficient of the pipeline stage 10 to be calibrated is improved.

In addition, as shown in fig. 4, the inter-stage gain error calibration method may further include: according to the ideal digital code of the corresponding weight of the i-th group of pseudo-random noise sequences, the ideal gain coefficient and the actual gain coefficient of the pipeline stage 10 to be calibrated, the post-stage digital output code output by the post-stage pipeline stage 20 is calibrated to obtain the calibrated post-stage digital output code, and the post-stage digital output code output by the post-stage pipeline stage 20 is calibrated by using the actual gain coefficient of the pipeline stage 10 to be calibrated, so that the analog-to-digital conversion accuracy of the pipeline stage ADC is improved. Specifically, referring to fig. 4, the following calculation formula may be used for calibration to obtain the calibrated post-stage digital output code D_o ^B_cal：

D_o ^B_cal＝D_R-D_PN*ra′/ra

Next, modeling simulation can be performed on the inter-stage gain error calibration method by using matlab, spectrograms before and after inter-stage gain calibration obtained by simulation are respectively shown in fig. 9 and fig. 10, and performance pairs before and after calibration are shown in table 2.

TABLE 2 comparison of simulation Performance before and after interstage gain calibration

Performance index	Before interstage gain calibration	After the interstage gain calibration
			SNR(dBc)	53.75	78.03
SNDR(dBc)	53.97	77.84
			SFDR(dBc)	64.26	88.61
THD(dBc)	-66.92	-91.47
			ENOB(Bit)	8.64	12.64

Pseudo-random noise jitter injection in opposite directions is carried out simultaneously from the sub-ADC 11 and the sub-DAC 12, and an actual gain coefficient of the pipeline stage 10 to be calibrated is determined based on a sampling signal interval division mode input into the pipeline stage 10 to be calibrated, so that interstage gain errors are extracted. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC 11 and the sub-DAC 12, the residual voltage is maintained to be +/-1/2V_refTherefore, the requirement of linearity of the operational amplification signal of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow caused by pseudo-random noise injection of the sub-DAC 12 is avoided. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also finish interstage gainOn the basis of calibration, pseudo-random noise jitter injection in opposite directions is simultaneously carried out through the sub-ADC 11 and the sub-DAC 12, a good spectrum scattering effect can be achieved, and the whole dynamic range of the pipeline ADC is improved.

Furthermore, the embodiment of the invention also provides an interstage gain error calibration circuit of the pipeline ADC. Referring to fig. 2, fig. 3 and fig. 4, the pipeline ADC includes a multi-stage pipeline stage, the multi-stage pipeline stage includes a pipeline stage 10 to be calibrated for completing n-bit digital code conversion and a pipeline stage 20 located at a stage subsequent to the pipeline stage to be calibrated, and the pipeline stage 10 to be calibrated includes a sub-ADC 11 and a sub-DAC 12. The interstage gain error calibration circuit comprises: a sample-and-hold module, a pseudo random noise injection module 30, a calibration signal determination module, and a gain factor calibration module 40. The sample-and-hold module is configured to obtain a sampling signal, and input the sampling signal into the pipeline stage 10 to be calibrated. The pseudo random noise injection module 30 is used for injecting m pairs of sub ADC pseudo random noise with the size of +1/a into the sub ADC11_i*V_refAt the same time as the pseudo random noise of (1), m pairs of sub-DAC pseudo random noise of-1/b size are injected into the sub-DAC 12_i*V_refThe pseudo random noise of (2); alternatively, the pseudo random noise injection module 30 is used to inject m pairs of sub-ADC pseudo random noise with a size of-1/a into the sub-ADC 11_i*V_refIs injected into the sub-DAC 12 with m pairs of sub-DAC pseudo random noise of +1/b_i*V_refThe pseudo random noise of (2); wherein m is a positive integer, the ith sub-ADC pseudo-random noise and the ith sub-DAC pseudo-random noise correspond to the same ith group of pseudo-random noise sequences, and a_i＝b_i*2^n-1. The calibration signal determining module is used for determining the calibration signal according to m, n, +/-1/a_i*V_refThe signal range available for calibration is determined. The gain coefficient calibration module 40 is configured to determine an actual gain coefficient of the pipeline stage 10 to be calibrated according to an ideal digital code of a corresponding weight of the i-th group of pseudo-random noise sequences, a post-stage digital output code output by the post-stage pipeline stage 20, and an ideal gain coefficient of the pipeline stage 10 to be calibrated when a sampling signal input to the pipeline stage 10 to be calibrated is within a signal range available for calibration.

In the above scheme, pseudo random noise jitter injection in opposite directions is performed simultaneously from the sub-ADC 11 and the sub-DAC 12, and an actual gain coefficient of the pipeline stage 10 to be calibrated is determined based on a sampling signal interval division mode input to the pipeline stage 10 to be calibrated, so as to extract an inter-stage gain error. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC 11 and the sub-DAC 12, the residual voltage is maintained to be +/-1/2V_refTherefore, the requirement of linearity of the operational amplification signal of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow caused by pseudo-random noise injection of the sub-DAC 12 is avoided. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also perform pseudo-random noise jitter injection in opposite directions through the sub-ADC 11 and the sub-DAC 12 on the basis of completing interstage gain calibration, so that a good spectrum scattering effect can be achieved, and the whole dynamic range of the pipeline stage ADC is improved. The above functional modules are described in detail with reference to the accompanying drawings.

In setting the sub ADC11 described above, referring to fig. 5, the sub ADC11 may include a sub ADC 2ⁿ(n-1) 5bit pipeline stage ADC111 consisting of-2 comparators and two additional thresholds respectively +/-2ⁿ-1)/2ⁿ*V_refThe comparator(s) of (2) is (are) a comparator (112) having a threshold value of + (2n-1)/2n × Vref and a comparator (113) having a threshold value of- (2n-1)/2n × Vref are added. The pseudo random noise injection module 30 injects m pairs of sub-ADC pseudo random noise with the sizes of +/-1/a respectively into the i-th pair of the sub-ADC 11 by changing the threshold of the comparator of the sub-ADC 11_i*V_refOf the pseudo random noise. In fig. 5, n of the sub-ADC 11 is 3, and the threshold is respectively increased to ± 7/8 × V on the basis of the original 2.5-bit pipeline stage ADC composed of 6 comparators_refThe comparator facilitates pseudo-random noise jitter injection from the sub-ADC 11, and simultaneously folds both ends of a transmission curve, thereby avoiding residual voltage overflow caused by pseudo-random noise injection of the sub-DAC 12.

When sub-DAC 12 is provided, sub-DAC 12 may include sub-DAC 2ⁿ-2 capacitors (n-1).5bThe current limiting circuit comprises an it-pipeline DAC and two additionally-arranged capacitors with the same capacitance value, namely two additionally-arranged capacitors with the same capacitance value as other capacitors. A pseudo random noise capacitor can be arranged in the pseudo random noise injection module 30, and the pseudo random noise injection module 30 injects the ith pair of m sub-DAC pseudo random noise to the sub-DAC 12 with the sizes of +/-1/b respectively through the pseudo random noise capacitor_i*V_refOf the pseudo random noise. The simultaneous opposite direction pseudo random noise dither injection from sub-ADC 11 and sub-DAC 12 is facilitated.

When the calibration signal determination module is provided, referring to fig. 2, 3 and 4, the calibration signal determination module may be based on m, n, ± 1/a_i*V_refAnd calculating the signal range of the sampling signal influenced by the pseudo random noise of the ith sub-DAC only and not influenced by the pseudo random noise of the ith sub-ADC, and taking the signal range as the signal range which can be used for calibration. The sampling signal input to the pipeline stage 10 to be calibrated is only affected by the injection of the sub-DAC pseudo-random noise sequence. Calibration may be initiated when the sampled signal is within a signal range that is available for calibration. That is, only the sampling signal within the calibration range is subjected to corresponding correlation operation, which is equivalent to the case where only the sub-DAC 12 injects the pseudo-random noise sequence, so that the inter-stage gain coefficient can be extracted. During calibration, the equivalent injection is a pseudo-random noise sequence that is uncorrelated with the sampling signal so as not to interfere with the operation of the sub-ADC 11 and the entire pipeline ADC. Since the pseudo-random noise sequence will encounter the same non-ideal situation through the same path as the sub-DAC 12 signal, the actual gain coefficient of the pipeline stage 10 to be calibrated can be detected and the inter-stage gain error can be extracted. The workflow of the calibration signal determination module may refer to the description of the foregoing method portion, and is not described herein again.

M may be equal to 1, and the calibration signal determination module determines the calibration signal according to m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration may specifically be:

wherein k is 0, ± 1, ± 2, ·, and ± (2)^n-1-1). By injecting only one pair of pseudo random noise to the sub-ADC 11 and the sub-DAC 12, the circuit structure for running the algorithm is simplified. For specific introduction, reference may be made to the description of relevant portions of the foregoing methods, which are not described herein again.

M may be a positive integer greater than 1, and the calibration signal determination module determines the calibration signal according to m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration may specifically be:

wherein k is 0, ± 1, ± 2, ·, and ± (2)^n-1-1). At least two pairs of pseudo-random noise are injected into the sub-ADC 11 and the sub-DAC 12, so that the spectrum scattering effect can be improved, and the whole dynamic range of the pipeline ADC is further improved. For specific introduction, reference may be made to the description of relevant portions of the foregoing methods, which are not described herein again.

When the gain calibration module is specifically configured, referring to fig. 2, fig. 3 and fig. 4, the gain coefficient calibration module 40 may determine the actual gain coefficient of the pipeline stage 10 to be calibrated by using an LMS algorithm according to the ideal digital code of the i-th group of pseudo-random noise sequences corresponding to the weights, the post-stage digital output code output by the post-stage pipeline stage 20, and the ideal gain coefficient of the pipeline stage 10 to be calibrated. By adopting an LMS convergence iteration mode and combining a pseudo-random noise jitter injection technology and related operation, interstage gain errors are extracted, and the accuracy of the obtained actual gain coefficient of the pipeline stage 10 to be calibrated is improved.

When the gain coefficient calibration module 40 specifically performs calibration by using LMS convergence iteration, referring to fig. 2, fig. 3, and fig. 4, the gain coefficient calibration module 40 may include an LMS algorithm iteration module and a threshold judgment module. The LMS algorithm iteration module is used for performing iteration operation according to the following formula:

ra_es[j+1]＝ra_es[j]+μ*D_PN*(D_R-D_PN*ra_es[j]/ra)

wherein j represents the number of iterations counted from 0; ra represents an ideal interstage gain coefficient; ra (ra)_esRepresenting estimated inter-stage gain coefficient, ra_es[j]And ra_es[j+1]Respectively representing an estimated interstage gain coefficient generated by the jth iteration and an estimated interstage gain coefficient generated by the j +1 th iteration; d_PNAn ideal digital code representing the corresponding weight of the ith group of pseudo-random noise sequences; d_RA post-stage digital output code output by the post-stage pipeline stage 20; μ denotes the convergence step factor.

The threshold judging module is used for judging ra after each iterative computation_es[j+1]And ra_es[j]Whether the difference value between the two is less than a set threshold value; if not, the next iteration is continued by the LMS algorithm iteration module; otherwise, the threshold judging module will ra_es[j+1]As the actual gain factor of the pipeline stage 10 to be calibrated. By judging ra once after each iteration_es[j+1]And ra_es[j]Whether the difference between the values is smaller than the set threshold value or not is judged, and the iterative computation is stopped only when the difference is smaller than the set threshold value, so that the accuracy of the obtained actual gain coefficient of the pipeline stage 10 to be calibrated is improved. For a specific calculation manner, reference may be made to the description of the foregoing method portion, which is not described herein again.

In addition, referring to fig. 2, fig. 3 and fig. 4, the interstage gain error calibration circuit may further include a digital output code calibration module 50, where the digital output code calibration module 50 is configured to calibrate a post-stage digital output code output by the post-stage pipeline stage 20 according to an ideal digital code weighted correspondingly by the ith group of pseudo-random noise sequences, an ideal gain coefficient and an actual gain coefficient of the pipeline stage 10 to be calibrated, to obtain the calibrated post-stage digital output code, and calibrate the post-stage digital output code output by the post-stage pipeline stage 20 by using the actual gain coefficient of the pipeline stage 10 to be calibrated, so as to improve analog-to-digital conversion accuracy of the pipeline stage ADC. For the digital output code calibration module 50 to implement the calibration process of the post-stage digital output code of the post-stage pipeline stage 20, reference may be made to the description of the foregoing method, and details are not repeated here.

By using pseudo random noise dither with simultaneous opposite direction from sub-ADC 11 and sub-DAC 12And determining an actual gain coefficient of the pipeline stage 10 to be calibrated based on a sampling signal interval division mode input into the pipeline stage 10 to be calibrated, and extracting an interstage gain error. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC 11 and the sub-DAC 12, the residual voltage is maintained to be +/-1/2V_refTherefore, the requirement of linearity of the operational amplification signal of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow caused by pseudo-random noise injection of the sub-DAC 12 is avoided. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also perform pseudo-random noise jitter injection in opposite directions through the sub-ADC 11 and the sub-DAC 12 on the basis of completing interstage gain calibration, so that a good spectrum scattering effect can be achieved, and the whole dynamic range of the pipeline stage ADC is improved.

In addition, an embodiment of the present invention further provides a pipeline ADC, where the pipeline ADC includes a multi-stage pipeline stage, and referring to fig. 2, fig. 3 and fig. 4, the multi-stage pipeline stage includes a pipeline stage 10 to be calibrated for completing n-bit digital code conversion, and a pipeline stage 20 located at a subsequent stage of the pipeline stage to be calibrated, where the pipeline stage 10 to be calibrated includes a sub-ADC 11 and a sub-DAC 12. The pipelined ADC further comprises an interstage gain error calibration circuit of any one of the pipelined ADCs. Pseudo-random noise jitter injection in opposite directions is carried out simultaneously from the sub-ADC 11 and the sub-DAC 12, and an actual gain coefficient of the pipeline stage 10 to be calibrated is determined based on a sampling signal interval division mode input into the pipeline stage 10 to be calibrated, so that interstage gain errors are extracted. And when pseudo random noise jitter injection in opposite directions is simultaneously carried out from the sub-ADC 11 and the sub-DAC 12, the residual voltage is maintained to be +/-1/2V_refTherefore, the requirement of linearity of the operational amplification signal of the pipeline stage to be calibrated can be greatly relieved, and the phenomenon of residual voltage overflow caused by pseudo-random noise injection of the sub-DAC 12 is avoided. The interstage gain error calibration method achieves a good interstage gain calibration effect for the high-precision ADC. Meanwhile, the interstage gain error calibration method can also be used for calibrating interstage gain through the sub-ADC 11 and the sub-DAC on the basis of completing interstage gain calibrationAnd 12, pseudo-random noise jitter injection in opposite directions is carried out at the same time, so that a better spectrum scattering effect can be realized, and the whole dynamic range of the pipeline ADC is improved.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An inter-stage gain error calibration method of a pipeline ADC (analog to digital converter) comprises a multi-stage pipeline stage, wherein the multi-stage pipeline stage is provided with a pipeline stage to be calibrated for completing n-bit digital code conversion and a post-stage pipeline stage positioned at the post-stage of the pipeline stage to be calibrated, and the pipeline stage to be calibrated comprises a sub-ADC and a sub-DAC; the interstage gain error calibration method is characterized by comprising the following steps:

inputting a sampling signal into the pipeline stage to be calibrated;

injecting m pairs of sub-ADCs with a pseudo-random noise of +1/a in the ith pair_i*V_refAt the same time of injecting m pairs of sub-DAC pseudo random noise with the size of-1/b into the sub-DAC_i*V_refThe pseudo random noise of (2); or, injecting m pairs of sub-ADC pseudo-random noise into the sub-ADC with the size of-1/a_i*V_refWhile injecting m sub-DAC pseudo-random noise with the i-th pair size of +1/b_i*V_refThe pseudo random noise of (2); wherein m is a positive integer, the ith sub-ADC pseudo-random noise corresponds to the same ith group of pseudo-random noise sequences as the ith sub-DAC pseudo-random noise, and a_i＝b_i*2^n-1；

According to said m, n, ± 1/a_i*V_refDetermining a signal range available for calibration;

and when the sampling signal input into the pipeline stage to be calibrated is in the signal range available for calibration, determining the actual gain coefficient of the pipeline stage to be calibrated according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage and the ideal gain coefficient of the pipeline stage to be calibrated.

2. The inter-stage gain error calibration method of claim 1, wherein said scaling is based on said m, n, ± 1/a_i*V_refDetermining a range of signals available for calibration includes:

according to said m, n, ± 1/a_i*V_refAnd calculating a signal range of the sampling signal, which is only influenced by the ith sub-DAC pseudo random noise and not influenced by the ith sub-ADC pseudo random noise, and taking the signal range as the signal range available for calibration.

3. The inter-stage gain error calibration method of claim 2, wherein m-1;

according to said m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration is specifically:

wherein k is 0, ± 1, ± 2^n-1-1)。

4. The inter-stage gain error calibration method of claim 2, wherein m > 1;

wherein k is 0, ± 1, ± 2, ·, and ± (2)^n-1-1)。

5. The inter-stage gain error calibration method according to claim 1, wherein said determining the actual gain coefficient of said pipeline stage to be calibrated according to the ideal digital code corresponding to the weight of said i-th set of pseudo-random noise sequences, the post-stage digital output code output by said post-stage pipeline stage, and the ideal gain coefficient of said pipeline stage to be calibrated, uses LMS algorithm.

6. The inter-stage gain error calibration method of claim 5, wherein said determining the actual gain coefficients of said pipeline stage to be calibrated using an LMS algorithm comprises:

performing iterative operation according to the following formula:

ra_es[j+1]＝ra_es[j]+μ*D_PN*(D_R-D_PN*ra_es[j]/ra)

wherein j represents the number of iterations counted from 0;

ra represents the ideal inter-stage gain coefficient;

ra_esrepresenting estimated inter-stage gain coefficient, ra_es[j]And ra_es[j+1]Respectively representing an estimated interstage gain coefficient generated by the jth iteration and an estimated interstage gain coefficient generated by the j +1 th iteration;

D_PNan ideal digital code representing the corresponding weight of said ith set of pseudorandom noise sequences;

D_Ra post-stage digital output code output by the post-stage pipeline stage;

μ denotes a convergence step factor;

and ra is judged after each iterative calculation_es[j+1]And ra_es[j]Whether the difference value between the two values is smaller than a set threshold value;

if not, continuing to perform the next iteration;

otherwise, will ra_es[j+1]As the actual gain coefficient of the pipeline stage to be calibrated.

7. The inter-stage gain error calibration method of claim 1, further comprising:

and calibrating the post-stage digital output code output by the post-stage pipeline stage according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the ideal gain coefficient and the actual gain coefficient of the pipeline stage to be calibrated, and obtaining the calibrated post-stage digital output code.

8. An inter-stage gain error calibration circuit of a pipeline ADC (analog to digital converter) comprises a multi-stage pipeline stage, wherein the multi-stage pipeline stage is provided with a pipeline stage to be calibrated for completing n-bit digital code conversion and a post-stage pipeline stage positioned at the post stage of the pipeline stage to be calibrated, and the pipeline stage to be calibrated comprises a sub-ADC and a sub-DAC; wherein the interstage gain error calibration circuit comprises:

the sampling and holding module is used for acquiring a sampling signal and inputting the sampling signal into the pipeline stage to be calibrated;

a pseudo random noise injection module for injecting m pairs of sub ADC pseudo random noise with the i-th pair size of +1/a into the sub ADC_i*V_refAt the same time of injecting m pairs of sub-DAC pseudo random noise with the size of-1/b into the sub-DAC_i*V_refThe pseudo random noise of (2); or the pseudo random noise injection module is used for injecting m pairs of sub ADC pseudo random noise into the sub ADC, wherein the i pair size of the m pairs of sub ADC pseudo random noise is-1/a_i*V_refWhile injecting m sub-DAC pseudo random noise into the sub-DAC, wherein the i-th pair of the pseudo random noise is +1/b_i*V_refThe pseudo random noise of (2); wherein m is a positive integer, the ith sub-ADC pseudo-random noise corresponds to the same ith group of pseudo-random noise sequences as the ith sub-DAC pseudo-random noise, and a_i＝b_i*2^n-1；

A calibration signal determination module for determining the calibration signal according to the m, n, ± 1/a_i*V_refDetermining a signal range available for calibration;

and the gain coefficient calibration module is used for determining the actual gain coefficient of the pipeline stage to be calibrated according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage and the ideal gain coefficient of the pipeline stage to be calibrated when the sampling signal input to the pipeline stage to be calibrated is in the signal range available for calibration.

9. The interstage gain error calibration circuit of claim 8, wherein the sub-ADC comprises: is composed of 2ⁿ(n-1) 5bit pipeline stage ADC composed of-2 comparators and two additional thresholds respectively of +/-2ⁿ-1)/2ⁿ*V_refThe comparator of (1);

the sub-DAC includes: is composed of 2ⁿ-2 capacitors constituting an (n-1).5bit pipeline DAC, and additionally two capacitors equal in size to the capacitance;

the pseudo random noise injection module injects the ith pair of pseudo random noise of the m pairs of sub ADCs into the sub ADCs by changing the threshold of the sub ADC comparator, wherein the sizes of the ith pair of pseudo random noise of the m pairs of sub ADCs are respectively +/-1/a_i*V_refThe pseudo random noise of (2);

a pseudo-random noise capacitor is also arranged in the pseudo-random noise injection module; the pseudo-random noise injection module injects m pairs of sub-DAC pseudo-random noise into the sub-DAC through the pseudo-random noise capacitor, wherein the sizes of the i pairs of the m pairs of the sub-DAC pseudo-random noise are +/-1/b_i*V_refOf the pseudo random noise.

10. The interstage gain error calibration circuit of claim 8, wherein the calibration signal determination module is dependent on the m, n, ± 1/a_i*V_refAnd calculating a signal range of the sampling signal, which is only influenced by the ith sub-DAC pseudo random noise and not influenced by the ith sub-ADC pseudo random noise, and taking the signal range as the signal range available for calibration.

11. The interstage gain error calibration circuit of claim 10, wherein m-1;

the calibration signal determination module determines the calibration signal according to the m, n, ± 1/a_i*V_refThe determined signal range that can be used for calibration is specifically:

wherein k is 0, ± 1, ± 2, ·, and ± (2)^n-1-1)。

12. The interstage gain error calibration circuit of claim 10, wherein m > 1;

wherein k is 0, ± 1, ± 2, ·, and ± (2)^n-1-1)。

13. The interstage gain error calibration circuit of claim 8, wherein the gain coefficient calibration module determines the actual gain coefficient of the pipeline stage to be calibrated by using an LMS algorithm according to an ideal digital code corresponding to the weight of the ith group of pseudo-random noise sequences, a post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated.

14. The inter-stage gain error calibration circuit of claim 13, wherein said gain factor calibration module comprises: an LMS algorithm iteration module and a threshold judgment module;

the LMS algorithm iteration module is used for performing iteration operation according to the following formula:

ra_es[j+1]＝ra_es[j]+μ*D_PN*(D_R-D_PN*ra_es[j]/ra)

wherein j represents the number of iterations counted from 0;

ra represents the ideal inter-stage gain coefficient;

D_Ra post-stage digital output code output by the post-stage pipeline stage;

μ denotes a convergence step factor;

the threshold judging module is used for judging ra after each iterative computation_es[j+1]And ra_es[j]Whether the difference value between the two values is smaller than a set threshold value; if not, the LMS algorithm iteration module continues to carry out the next iteration; otherwise, the threshold judging module is used for judging ra_es[j+1]As the actual gain coefficient of the pipeline stage to be calibrated.

15. The interstage gain error calibration circuit of claim 8, further comprising:

and the digital output code calibration module is used for calibrating the rear-stage digital output code output by the rear-stage pipeline stage according to the ideal digital code of the corresponding weight of the ith group of pseudo-random noise sequences, the ideal gain coefficient and the actual gain coefficient of the pipeline stage to be calibrated, so as to obtain the calibrated rear-stage digital output code.

16. A pipelined ADC, comprising:

a plurality of pipeline stages; the multi-stage pipeline stage is provided with a pipeline stage to be calibrated for completing n-bit digital code conversion and a post-stage pipeline stage positioned at the post-stage of the pipeline stage to be calibrated, wherein the pipeline stage to be calibrated comprises a sub-ADC and a sub-DAC;

an inter-stage gain error calibration circuit for a pipelined ADC as claimed in any one of claims 8 to 15.