CN114446877A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114446877A
CN114446877A CN202011210099.XA CN202011210099A CN114446877A CN 114446877 A CN114446877 A CN 114446877A CN 202011210099 A CN202011210099 A CN 202011210099A CN 114446877 A CN114446877 A CN 114446877A
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Prior art keywords
wafer
layer
hole
forming
trench
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CN202011210099.XA
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Chinese (zh)
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马慧琳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011210099.XA priority Critical patent/CN114446877A/en
Publication of CN114446877A publication Critical patent/CN114446877A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Abstract

The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: the substrate comprises a first wafer, a second wafer and a through silicon via, wherein the first wafer and the second wafer are stacked, the through silicon via penetrates through the second wafer and is electrically connected with a first rewiring layer in the first wafer, and a second metal wiring layer is formed in the second wafer; the dielectric layer is positioned on the surface of the second wafer; the second rewiring layer is positioned in the dielectric layer, a first part of the second rewiring layer is electrically connected with the silicon through hole, and a second part of the second rewiring layer is positioned above the second metal connecting line layer; a second via located below and electrically connected to the second portion of the second redistribution layer, the second via not being directly connected to the second metal interconnect layer; and the third through hole is positioned below the second through hole and is electrically connected with the second metal connecting line layer and the second through hole.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Through Silicon Vias (TSVs) may be used to connect wafers in a 3D integrated package. In some 3D integrated packaging processes, the TSVs are not directly connected to the device layers on the stacked wafer, but rather re-routing layers (RDLs) and vias are required to connect the through-silicon vias and the devices on the stacked wafer for electrical connection.
However, the current through silicon via process still has the problem that the dimension of the rewiring layer and the through hole is too large, which results in the oversize of the whole wafer. Therefore, there is a need to provide more efficient and reliable solutions.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can reduce the sizes of a rewiring layer and a through hole so as to reduce the overall size of a wafer.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first wafer, a second wafer and a through silicon via penetrating through the second wafer and electrically connected with a first rewiring layer in the first wafer, and a second metal wiring layer is formed in the second wafer; forming a dielectric layer on the surface of the through silicon via and the surface of the second wafer; forming a first groove in the dielectric layer, wherein a first part of the first groove exposes the silicon through hole, and a second part of the first groove is positioned above the second metal connecting line layer; forming a second trench at the bottom of a second portion of the first trench over the second metal wiring layer, the second trench not exposing the second metal wiring layer; forming a third groove exposing the second metal connecting line layer at the bottom of the second groove; and forming a second rewiring layer in the first groove, forming a second through hole in the second groove and forming a third through hole in the third groove.
In some embodiments of the present application, the method of forming the first trench, the second trench, and the third trench includes wet etching or dry etching.
In some embodiments of the present application, the method of forming the second re-wiring layer, the second via, and the third via includes: filling a conductive material in the first trench, the second trench and the third trench; and grinding to remove the conductive material higher than the surface of the first groove.
In some embodiments of the present application, a size of the third via is smaller than a size of the second via.
In some embodiments of the present application, the first wafer further includes a first metal wiring layer electrically connected to the first redistribution layer through a first via.
In some embodiments of the present application, the semiconductor structure further comprises an intermediate dielectric layer between the first wafer and the second wafer.
Another aspect of the present application provides a semiconductor structure comprising: the substrate comprises a first wafer, a second wafer and a through silicon via, wherein the first wafer and the second wafer are stacked, the through silicon via penetrates through the second wafer and is electrically connected with a first rewiring layer in the first wafer, and a second metal wiring layer is formed in the second wafer; the dielectric layer is positioned on the surface of the second wafer; the second rewiring layer is positioned in the dielectric layer, a first part of the second rewiring layer is electrically connected with the silicon through hole, and a second part of the second rewiring layer is positioned above the second metal connecting line layer; a second via located below the second portion of the second redistribution layer and electrically connected to the second portion of the second redistribution layer, the second via not being directly connected to the second metal interconnect layer; and the third through hole is positioned below the second through hole and is electrically connected with the second metal connecting line layer and the second through hole.
In some embodiments of the present application, a size of the third via is smaller than a size of the second via.
In some embodiments of the present application, the first wafer further includes a first metal wiring layer electrically connected to the first redistribution layer through a first via.
In some embodiments of the present application, the semiconductor structure further comprises an intermediate dielectric layer between the first wafer and the second wafer.
According to the semiconductor structure and the forming method thereof, the second through hole and the third through hole are formed through twice etching, so that the sizes of the second through hole and the third through hole can be reduced, and the overall size of a wafer is further reduced; in addition, the size of the third through hole is smaller than that of the second through hole, so that the metal material in the second through hole can be prevented from being diffused, and the reliability of the device is improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 7 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
In some methods of forming semiconductor structures, RDLs may be fabricated using common copper top metal processes since TSV sizes are on the order of a few microns. The vias under the RDL may also use a common copper top via process. However, in practice, since the film thickness between the RDL and the top metal on the stacked wafer is much thicker, the normal copper top via process cannot be used because the TSV process requires such a thick film.
FIG. 1 is a schematic diagram of a semiconductor structure. As shown in fig. 1, the semiconductor structure includes a substrate 100, where the substrate 100 includes a first wafer 110 and a second wafer 120 stacked on top of each other, an intermediate dielectric layer 130 between the first wafer 110 and the second wafer 120, and a through-silicon via 140 penetrating through the second wafer 120 and the intermediate dielectric layer 130.
The first wafer 110 includes a first substrate 111 and a first interlayer dielectric layer 112, a first metal wiring layer 113 connected to an active device (not shown) in the first substrate 111 is formed in the first interlayer dielectric layer 112, and the first metal wiring layer 113 is electrically connected to a first redistribution layer 115 through a first via 114.
Similarly, the second wafer 120 includes a second substrate 121 and a second interlayer dielectric layer 122, a second metal wiring layer 123 connected to an active device (not shown) in the second substrate 121 is formed in the second interlayer dielectric layer 122, and the second metal wiring layer 123 is electrically connected to a second redistribution layer 125 through a second via 124.
In the semiconductor structure shown in fig. 1, the sizes of the first via hole 114 and the second via hole 124 are large, and the sizes of the first re-wiring layer 115 and the second re-wiring layer 125 are also large, which has a great influence on the chip size.
Therefore, in order to solve the above problems, the present application provides a semiconductor structure and a method for forming the same, in which the second through hole and the third through hole are formed by two times of etching, so that the sizes of the second through hole and the third through hole can be reduced, and the overall size of a wafer is further reduced; in addition, the size of the third through hole is smaller than that of the second through hole, so that the metal material in the second through hole can be prevented from being diffused, and the reliability of the device is improved.
An embodiment of the present application provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first wafer, a second wafer and a through silicon via which penetrates through the second wafer and is electrically connected with a first rewiring layer in the first wafer, and a second metal connecting layer is formed in the second wafer; forming a dielectric layer on the surface of the through silicon via and the surface of the second wafer; forming a first groove in the dielectric layer, wherein a first part of the first groove exposes the silicon through hole, and a second part of the first groove is positioned above the second metal connecting line layer; forming a second trench at the bottom of a second portion of the first trench over the second metal wiring layer, the second trench not exposing the second metal wiring layer; forming a third groove exposing the second metal connecting line layer at the bottom of the second groove; and forming a second rewiring layer in the first groove, forming a second through hole in the second groove and forming a third through hole in the third groove.
Fig. 2 to 7 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. A method for forming a semiconductor structure according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 includes a first wafer 210 and a second wafer 220 stacked, and a through silicon via 240 penetrating the second wafer 220 and electrically connecting a first redistribution layer 215 in the first wafer 210, wherein a second metal interconnection layer 223 is formed in the second wafer 220.
With continued reference to fig. 2, the first wafer 210 includes a first substrate 211 and a first interlayer dielectric layer 212. Wherein the material of the first substrate 211 comprises (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. The material of the first interlayer dielectric layer 212 includes silicon oxide or silicon nitride.
In some embodiments of the present application, the first wafer 210 further includes a first metal wiring layer 213 disposed in the first interlayer dielectric layer 212 and electrically connected to active devices (not shown) in the first substrate 211, and the first metal wiring layer 213 is further electrically connected to the first redistribution layer 215 through a first via 214. The material of the first metal connecting layer 213 includes copper or aluminum. The material of the first via 214 includes tungsten or copper. The material of the first redistribution layer 215 includes copper, aluminum, or the like.
The second wafer 220 includes a second substrate 221 and a second interlayer dielectric layer 222. Wherein the material of the second substrate 221 comprises (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. The material of the second interlayer dielectric layer 222 includes silicon oxide or silicon nitride. The second metal wiring layer 223 is located in the second interlayer dielectric layer 222 and electrically connected to active devices (not shown) in the second substrate 221. The material of the second metal wiring layer 223 includes copper or aluminum.
In some embodiments of the present application, the material of the through silicon via 240 includes copper or tungsten, etc.
In some embodiments of the present application, the semiconductor structure further comprises an intermediate dielectric layer 230 located between the first wafer 210 and the second wafer 220. The through-silicon via 240 also penetrates the middle dielectric layer 230.
In the 3D packaging process of the semiconductor structure, the stacked first wafer 210 and second wafer 220 are electrically connected, and therefore, the second metal wire layer 223 and the through silicon via 240 are also electrically connected. It should be noted that the present application only uses two wafers as an example, and the process of the present application can also be applied to a stacking process of more than two wafers.
Referring to fig. 3, a dielectric layer 250 is formed on the surface of the through silicon via 240 and the surface of the second wafer 220.
In some embodiments of the present application, the method of forming the dielectric layer 250 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the material of the dielectric layer 250 includes silicon oxide or silicon nitride.
Referring to fig. 4, a first trench 260 is formed in the dielectric layer 250, a first portion of the first trench 260 exposes the through-silicon via 240, and a second portion of the first trench 260 is located above the second metal wire layer 223. The first trench 260 is used to form a second re-wiring layer, so the size of the first trench 260 matches the size of the second re-wiring layer.
In some embodiments of the present application, the method of forming the first trench 260 includes a photolithography process and a wet etching or a dry etching.
Referring to fig. 5, a second trench 270 is formed at the bottom of the second portion of the first trench 260 above the second metal wiring layer 223, the second trench 270 not exposing the second metal wiring layer 223.
In some embodiments of the present application, a method for forming the second trench 270 includes a photolithography process, or a dry etching or a wet etching.
Referring to fig. 6, a third trench 280 exposing the second metal wiring layer 223 is formed at the bottom of the second trench 270.
In some embodiments of the present application, the method for forming the third trench 280 includes a photolithography process and a dry etching or wet etching.
Compared with the semiconductor structure shown in fig. 1, the second through hole 124 in fig. 1 is formed at one time, a trench is formed by one etching, and then the trench is filled to form the second through hole 124, in such a process, the size of the formed second through hole 124 is larger, and the overall size of the chip is increased. In the method for forming the semiconductor structure according to the embodiment of the present application, the second trench 270 and the third trench 280 are formed by two times of etching, the amount of etching at each time is small, and the sizes of the formed second trench 270 and the formed third trench 280 are small, so that the size of the whole wafer can be reduced, and the device performance can be improved. The dimension includes a diameter (a dimension in a horizontal direction in the drawing).
In some embodiments of the present application, the method for forming a semiconductor structure described herein can reduce the size of a chip by 20% to 40% compared to the size of a conventional chip.
It should be noted that, in the embodiment of the present application, two through holes are formed by two times of etching, and actually, more times of etching may be performed, for example, three times or four times of etching, to form four through holes to electrically connect the second redistribution layer and the second metal interconnection layer.
Referring to fig. 7, a second re-wiring layer 226 is formed in the first trench 260, a second via hole 225 is formed in the second trench 270, and a third via hole 224 is formed in the third trench 280.
In some embodiments of the present application, the method of forming the second redistribution layer 226, the second via 225, and the third via 224 includes: filling the first trench 260, the second trench 270, and the third trench 280 with a conductive material; the conductive material above the surface of the first trench 260 is removed by grinding.
In some embodiments of the present application, the conductive material comprises a metal material, such as copper or tungsten or aluminum.
In some embodiments of the present application, the third through-hole 224 is smaller in size than the second through-hole 225. Therefore, the metal material in the second via 225 can be prevented from diffusing into the second interlayer dielectric layer 222, and the device performance can be reduced.
According to the forming method of the semiconductor structure, the second through hole and the third through hole are formed through twice etching, so that the sizes of the second through hole and the third through hole can be reduced, and the overall size of a wafer is further reduced; in addition, the size of the third through hole is smaller than that of the second through hole, so that the metal material in the second through hole can be prevented from being diffused, and the reliability of the device is improved.
Embodiments of the present application also provide a semiconductor structure, referring to fig. 7, comprising: the substrate comprises a first wafer, a second wafer and a through silicon via, wherein the first wafer and the second wafer are stacked, the through silicon via penetrates through the second wafer and is electrically connected with a first rewiring layer in the first wafer, and a second metal wiring layer is formed in the second wafer; the dielectric layer is positioned on the surface of the second wafer; the second rewiring layer is positioned in the dielectric layer, a first part of the second rewiring layer is electrically connected with the silicon through hole, and a second part of the second rewiring layer is positioned above the second metal connecting line layer; a second via located below and electrically connected to the second portion of the second redistribution layer, the second via not being directly connected to the second metal interconnect layer; and the third through hole is positioned below the second through hole and is electrically connected with the second metal connecting line layer and the second through hole.
Referring to fig. 7, the semiconductor structure includes a substrate 200, the substrate 200 includes a first wafer 210 and a second wafer 220 stacked, and a through silicon via 240 penetrating the second wafer 220 and electrically connecting a first redistribution layer 215 in the first wafer 210, and a second metal wiring layer 223 is formed in the second wafer 220.
With continued reference to fig. 7, the first wafer 210 includes a first substrate 211 and a first interlayer dielectric layer 212. Wherein the material of the first substrate 211 comprises (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. The material of the first interlayer dielectric layer 212 includes silicon oxide or silicon nitride.
In some embodiments of the present application, the first wafer 210 further includes a first metal wiring layer 213 disposed in the first interlayer dielectric layer 212 and electrically connected to active devices (not shown) in the first substrate 211, and the first metal wiring layer 213 is further electrically connected to the first redistribution layer 215 through a first via 214. The material of the first metal wiring layer 213 includes copper or aluminum. The material of the first via 214 includes tungsten or copper. The material of the first redistribution layer 215 includes copper, aluminum, or the like.
The second wafer 220 includes a second substrate 221 and a second interlayer dielectric layer 222. Wherein the material of the second substrate 221 comprises (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. The material of the second interlayer dielectric layer 222 includes silicon oxide or silicon nitride. The second metal wiring layer 223 is located in the second interlayer dielectric layer 222 and electrically connected to active devices (not shown) in the second substrate 221, and the second metal wiring layer 223 is further electrically connected to the second redistribution layer 226 through a second via 225 and a third via 224. The material of the second metal wiring layer 223 includes copper or aluminum, etc. The material of the second via 225 includes tungsten or copper. The material of the third via 224 includes tungsten or copper. The material of the first redistribution layer 215 includes copper, aluminum, or the like.
In some embodiments of the present application, the material of the through silicon via 240 includes copper or tungsten, etc.
In some embodiments of the present application, the semiconductor structure further comprises an intermediate dielectric layer 230 located between the first wafer 210 and the second wafer 220. The through-silicon via 240 also penetrates through the intermediate dielectric layer 230.
With continued reference to fig. 7, the dielectric layer 250 is disposed on the surface of the second wafer 220, and the second redistribution layer 226 is disposed in the dielectric layer 250.
In some embodiments of the present application, the material of the dielectric layer 250 includes silicon oxide or silicon nitride.
In some embodiments of the present application, the third through-hole 224 is smaller in size than the second through-hole 225. Therefore, the metal material in the second via 225 can be prevented from diffusing into the second interlayer dielectric layer 222, and the device performance can be reduced.
Compared with the semiconductor structure shown in fig. 1, the second through hole 124 in fig. 1 is formed at one time, a trench is formed by one etching, and then the trench is filled to form the second through hole 124, in such a process, the size of the formed second through hole 124 is larger, and the overall size of the chip is increased. In the semiconductor structure according to the embodiment of the present application, the second trench and the third trench are formed by two times of etching, the amount of each time of etching is small, the size of the formed second trench and the size of the formed third trench are small, and the size of the formed second through hole 225 and the size of the formed third through hole 224 are also small, so that the size of the whole wafer can be reduced, and the device performance can be improved. The dimension includes a diameter (a dimension in a horizontal direction in the drawing).
In some embodiments of the present application, the dimensions of the semiconductor structures described herein can be reduced by 20% to 40% over the dimensions of conventional semiconductor structures.
It should be noted that, in the embodiment of the present application, two through holes are formed by two times of etching, and actually, more times of etching may be performed, for example, three times or four times of etching, to form four through holes to electrically connect the second redistribution layer and the second metal interconnection layer.
In the semiconductor structure, the second through hole and the third through hole are formed through twice etching, so that the sizes of the second through hole and the third through hole can be reduced, and the overall thickness of a wafer is further reduced; in addition, the size of the third through hole is smaller than that of the second through hole, so that the metal material in the second through hole can be prevented from being diffused, and the reliability of the device is improved.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It should be understood that the term "and/or" as used in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first wafer, a second wafer and a through silicon via penetrating through the second wafer and electrically connected with a first rewiring layer in the first wafer, and a second metal wiring layer is formed in the second wafer;
forming a dielectric layer on the surface of the through silicon via and the surface of the second wafer;
forming a first groove in the dielectric layer, wherein a first part of the first groove exposes the silicon through hole, and a second part of the first groove is positioned above the second metal connecting line layer;
forming a second trench at the bottom of a second portion of the first trench over the second metal wiring layer, the second trench not exposing the second metal wiring layer;
forming a third groove exposing the second metal connecting line layer at the bottom of the second groove;
and forming a second rewiring layer in the first groove, forming a second through hole in the second groove and forming a third through hole in the third groove.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first trench, the second trench, and the third trench comprises wet etching or dry etching.
3. The method of forming a semiconductor structure according to claim 1, wherein the method of forming the second re-wiring layer, the second via, and the third via includes:
filling a conductive material in the first trench, the second trench and the third trench;
and grinding to remove the conductive material higher than the surface of the first groove.
4. The method of forming a semiconductor structure of claim 1, wherein a size of the third via is smaller than a size of the second via.
5. The method of claim 1, wherein the first wafer further comprises a first metal link layer electrically connected to the first redistribution layer through a first via.
6. The method of forming a semiconductor structure of claim 1, further comprising an intermediate dielectric layer between the first wafer and the second wafer.
7. A semiconductor structure, comprising:
the substrate comprises a first wafer, a second wafer and a through silicon via, wherein the first wafer and the second wafer are stacked, the through silicon via penetrates through the second wafer and is electrically connected with a first rewiring layer in the first wafer, and a second metal wiring layer is formed in the second wafer;
the dielectric layer is positioned on the surface of the second wafer;
the second rewiring layer is positioned in the dielectric layer, a first part of the second rewiring layer is electrically connected with the silicon through hole, and a second part of the second rewiring layer is positioned above the second metal connecting line layer;
a second via located below and electrically connected to the second portion of the second redistribution layer, the second via not being directly connected to the second metal interconnect layer;
and the third through hole is positioned below the second through hole and is electrically connected with the second metal connecting line layer and the second through hole.
8. The semiconductor structure of claim 7, wherein a size of the third via is smaller than a size of the second via.
9. The semiconductor structure of claim 7, wherein the first wafer further comprises a first metal link layer electrically connected to the first redistribution layer through a first via.
10. The semiconductor structure of claim 7, further comprising an intermediate dielectric layer between the first wafer and the second wafer.
CN202011210099.XA 2020-11-03 2020-11-03 Semiconductor structure and forming method thereof Pending CN114446877A (en)

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