CN114441924B - Narrow pulse conduction voltage drop test method and circuit suitable for power semiconductor device - Google Patents
Narrow pulse conduction voltage drop test method and circuit suitable for power semiconductor device Download PDFInfo
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- CN114441924B CN114441924B CN202210370884.4A CN202210370884A CN114441924B CN 114441924 B CN114441924 B CN 114441924B CN 202210370884 A CN202210370884 A CN 202210370884A CN 114441924 B CN114441924 B CN 114441924B
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Abstract
The invention relates to a narrow pulse conduction voltage drop test method and a circuit suitable for a power semiconductor device. It comprises a current source including an energy storage capacitor C1 and an adjustable voltage source VadjThe energy storage capacitor C1 is connected with the first test connection end of the power semiconductor device to be tested through a test discharge part, and the test discharge part comprises a semiconductor switch T1 and a limiting resistor RlimitThe semiconductor switch T1 is controlled to be conducted by utilizing a turn-on driving signal PWM-Drive, and after the semiconductor switch T1 is conducted, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the test discharge part so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; measuring the voltage of the power semiconductor to be measured by using a voltage measuring device within the effective time range of turning on the driving signal PWM-Drive; the invention can improve the voltage drop test precision and reliability of the power semiconductor device.
Description
Technical Field
The invention relates to a conduction voltage drop test method and a circuit, in particular to a narrow pulse conduction voltage drop test method and a circuit suitable for a power semiconductor device.
Background
When testing the on-state voltage of the power semiconductor device, a pulse current source is used to generate a constant current pulse (the pulse width of the current pulse is usually less than 2ms, but not absolute) to deactivate the power semiconductor device to be tested, then a voltage meter is used to measure the voltage response of the power semiconductor device, and the voltage value when the power semiconductor device enters a steady state is taken as the final test result, so that the measured on-state voltage can be obtained.
Since the conduction voltage drop of the power semiconductor (voltage drop generated when the power semiconductor device is in a conduction state) is related to the temperature of the power semiconductor device, the conduction loss on the power semiconductor device can cause the temperature rise of the power semiconductor device during the test process, thereby affecting the test result. Therefore, the test procedure requires that the power semiconductor device be de-energized with a constant current pulse, and the shorter the duration of the current pulse (hereinafter referred to as pulse width), the less the temperature change of the power semiconductor device caused by the test procedure, the more accurate the temperature condition at the time of measurement. However, the shorter the pulse width is, the more difficult the design of the current source is, and the higher the implementation cost of the current source is. Generally, a reasonable pulse width is obtained by considering the test accuracy and the cost comprehensively. For example, the pulse width is usually 50 μ s to 500 μ s for an IGBT (insulated Gate Bipolar Transistor)/MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)/Diode device, and 100 μ s to 2000 μ s for an SCR (silicon Controlled rectifier) device.
As shown in fig. 1, the principle of the diode conduction voltage drop (VF) test is described. The method comprises the steps of placing a diode to be detected under a specific temperature condition, injecting specific current into the diode by using a current source, and collecting voltage at two ends of the diode to be detected by using a voltmeter, namely conducting voltage drop.
As shown in fig. 2 and 3, the principle of testing the turn-on voltage drop of the MOSFET and the IGBT, respectively. Unlike diode conduction voltage drop testing, MOSFET and IGBT conduction voltage drop testing also requires a gate bias voltage source to turn on the DUT (power semiconductor device under test, here MOSFET or IGBT). In addition, MOSFETs generally express turn-on characteristics in terms of RDSon parameters (on-resistance), which are essentially the same as on-voltage drops.
The core technology of the conduction voltage drop test of the power semiconductor device is a pulse constant current power supply, and an instantaneous constant current needs to be generated. As shown in fig. 4, the pulse constant current power supply is a typical voltage-controlled constant current source. Inputting a reference voltage waveform V to a pulse constant current power supplyref(t), the pulse constant current power supply will follow and output a current waveform Iforce(t)=Vref(t)/Rshunt. As shown in fig. 5, for a typical conduction voltage drop test waveform, the specific test process is as follows:
time period t 0-t 1: untested state, at which time VrefIs zero, IforceIs zero. time period t 1-t 2: vrefIncrease from zero to a target value, IforceAnd the current rises from zero to the test current, the distribution of carriers in the power semiconductor device to be tested is continuously increased in the process, and the voltage at two ends of the power semiconductor device is unstable. time period t 2-t 3: vrefHas reached the target value, IforceThe test current is reached, but the carrier distribution in the power semiconductor device does not enter a steady state yet, and the voltage is still changing. time period t 3-t 4: under the condition of testing current, the distribution of carriers in the power semiconductor device enters a stable state, and the voltage is basically stable. time period t 4-t 5: vrefFrom the target value down to zero, IforceFrom the test current to zero, the voltage across the device also gradually decreases to zero. time period t 5-t 6: the test is finished; at this time, VrefIs zero, IforceIs zero.
The conduction voltage drop is specifically tested within a time period of t 3-t 4, and under a common condition, a stable voltage waveform is taken to be averaged. In the whole test process, when current is poured into the power semiconductor device, heat accumulation T is generated inside the power semiconductor devicevjAnd also gradually rises. Taking into account TvjThe influence of the rise on the test precision is better as the time t 1-t 5 is shorter. two periods of time t 1-t 2 and t 4-t 5 are reserved for current change, and the current change rate di/dt is limited to a lower level, so that waveform stability is facilitated (otherwise, waveform oscillation may occur to affect the test result). In fact, the response speed of the traditional pulse constant current source is slow, and the two periods of time t 1-t 2 and t 4-t 5 are usually 50 mu s. During the test of the SiC/GaN device, the time length of t 1-t 5 needs to be controlled within 10 mu s, and the time lengths of t 1-t 2 and t 4-t 5 need to be controlled within 3 mu s, wherein the shorter the time length is, the better the time length is.
In summary, with the continuous progress of the technology, the power density of the power semiconductor chip is continuously improved, and the conduction voltage drop test requires further compression of the current pulse width. Particularly, after a third-generation power semiconductor (SiC/GaN and the like) device appears, the power density of a power semiconductor chip is far greater than that of a traditional silicon-based device, and the conduction voltage drop test of the power semiconductor chip requires that the current pulse width is compressed to be within 50 microseconds, even 10 microseconds. Such narrow pulse width pulsed current sources have been difficult to implement in a conventional manner.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a narrow-pulse conduction voltage drop test method and a circuit suitable for a power semiconductor device, which can effectively provide a narrow-pulse constant current for power semiconductor test and improve the voltage drop test precision and reliability of the power semiconductor device.
According to the technical scheme provided by the invention, the narrow pulse conduction voltage drop test method applicable to the power semiconductor device provides a current source for conducting voltage drop test of the power semiconductor device to be tested, the current source is in adaptive connection with a first test connection end of the power semiconductor device to be tested, and a second test connection end of the power semiconductor device to be tested and a grounding end of the current source are both directly grounded;
The current source comprises an energy storage capacitor C1 and an adjustable voltage source V for charging the energy storage capacitor C1adjThe energy storage capacitor C1 is connected with a first test connection end of the power semiconductor device to be tested in an adaptive manner through a test discharge part, and the test discharge part comprises a semiconductor switch T1 for controlling a test state and a limiting resistor R connected with the semiconductor switch T1 in serieslimitWherein, the semiconductor switch T1 is controlled by the turn-on driving signal PWM-Drive;
with the semiconductor switch T1 in the OFF state, an adjustable voltage source V is usedadjThe energy storage capacitor C1 is charged to a required voltage state, after the energy storage capacitor C1 is charged to the required voltage state, a turn-on driving signal PWM-Drive is used for controlling the semiconductor switch T1 to be conducted, and after the semiconductor switch T1 is conducted, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the test discharge part so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; in the effective time range of the on driving signal PWM-Drive,and measuring the voltage of the power semiconductor to be measured by using a voltage measuring device to obtain the required conduction voltage drop.
The semiconductor switch T1 is a fully-controlled semiconductor device, and the semiconductor switch T1 comprises an IGBT, an IGCT, a MOSFET, a JFET, a GTO or a HEMT.
The width of the current pulse loaded to the power semiconductor device to be tested is consistent with the effective time range of the PWM-Drive signal, and the width of the current pulse loaded to the power semiconductor device to be tested is 2-2000 mu s.
When the power semiconductor device to be tested is a power diode, the anode end of the power diode forms a first test connecting end, and the cathode end of the power diode forms a second test connecting end.
When the power semiconductor device to be tested is a controllable semiconductor device, the power semiconductor device to be tested also comprises a bias power supply for driving the power semiconductor device to be tested; when the power semiconductor device to be tested is tested, the bias power supply is used for driving the power semiconductor device to be tested to be in a conducting state.
The voltage measuring device comprises a voltmeter.
RT1+RDUT<<RlimitWherein R isT1Is the on-resistance, R, of the semiconductor switch T1DUTThe on-resistance of the power semiconductor device to be tested.
A narrow pulse conduction voltage drop test circuit suitable for a power semiconductor device comprises a current source for conducting voltage drop test of the power semiconductor device to be tested, wherein the current source is in adaptive connection with a first test connecting end of the power semiconductor device to be tested, and a second test connecting end of the power semiconductor device to be tested and a grounding end of the current source are both directly grounded;
The current source comprises an energy storage capacitor C1 and an adjustable voltage source V for charging the energy storage capacitor C1adjThe energy storage capacitor C1 is connected with the first test connection end of the power semiconductor device to be tested in an adaptive manner through a test discharge part, and the test discharge part comprises a semiconductor switch T1 for controlling a test state and a limiting resistor R connected with the semiconductor switch T1 in serieslimitWherein the semiconductor switchT1 is controlled by the turn-on driving signal PWM-Drive;
with the semiconductor switch T1 in the OFF state, an adjustable voltage source V is usedadjThe energy storage capacitor C1 is charged to a required voltage state, after the energy storage capacitor C1 is charged to the required voltage state, a turn-on driving signal PWM-Drive is used for controlling the semiconductor switch T1 to be conducted, and after the semiconductor switch T1 is conducted, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the test discharge part so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; and measuring the voltage of the power semiconductor to be measured by using a voltage measuring device within the effective time range of turning on the driving signal PWM-Drive so as to obtain the required conduction voltage drop.
The width of the current pulse loaded to the power semiconductor device to be tested is consistent with the effective time range of the PWM-Drive signal, and the width of the current pulse loaded to the power semiconductor device to be tested is 2-2000 mu s.
RT1+RDUT<<RlimitWherein R isT1Is the on-resistance, R, of the semiconductor switch T1DUTIs the on-resistance of the power semiconductor device to be tested.
The invention has the advantages that: the current source is used for providing pulse current required by the power semiconductor to be tested, and the adjustable voltage source V is used when the semiconductor switch T1 is in an off stateadjCharging the energy storage capacitor C1 to a required voltage state, controlling the semiconductor switch T1 to be conducted by using a turn-on driving signal PWM-Drive after the energy storage capacitor C1 is charged to the required voltage state, and discharging the power semiconductor device to be tested by the energy storage capacitor C1 through the test discharge part after the semiconductor switch T1 is conducted so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; within the effective time range of the on-Drive signal PWM-Drive, the voltage of the power semiconductor to be tested is measured by using a voltage measuring device to obtain the required on-voltage drop, and the effective time of the on-Drive signal PWM-Drive is adjusted to realize the current pulse with the required pulse width, so that the narrow pulse constant current for testing the power semiconductor can be effectively provided, and the voltage drop testing precision and reliability of the power semiconductor device are improved。
Drawings
Fig. 1 is a schematic diagram of a conventional conduction voltage drop test performed on a diode.
Fig. 2 is a schematic diagram of a conventional turn-on voltage drop test of a MOSFET device.
Fig. 3 is a schematic diagram of a conventional conduction voltage drop test of an IGBT device.
Fig. 4 is a schematic diagram of a conventional conduction voltage drop test using a pulsed constant current power supply.
Fig. 5 is a waveform diagram of the conduction voltage drop test of fig. 4.
Fig. 6 is a schematic diagram of the diode conduction voltage drop test according to the present invention.
Fig. 7 is a waveform diagram illustrating a conduction voltage drop test performed on a power semiconductor device according to the present invention.
Fig. 8 is a schematic diagram of the conduction voltage drop test of the IGBT device according to the present invention.
Fig. 9 is a schematic diagram of the conduction voltage drop test of the MOSFET device according to the present invention.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
In order to effectively provide a narrow pulse constant current for power semiconductor testing and improve the voltage drop testing precision and reliability of a power semiconductor device, the invention discloses a narrow pulse conduction voltage drop testing method suitable for the power semiconductor device, which specifically comprises the following steps: providing a current source for conducting voltage drop test of the power semiconductor device to be tested, wherein the current source is in adaptive connection with the first test connecting end of the power semiconductor device to be tested, and the second test connecting end of the power semiconductor device to be tested and the grounding end of the current source are both directly grounded;
The current source comprises an energy storage capacitor C1 and an adjustable voltage source V for charging the energy storage capacitor C1adjThe energy storage capacitor C1 is connected with the first test connection end of the power semiconductor device to be tested in an adaptive manner through a test discharge part, and the test discharge part comprises a semiconductor switch T1 for controlling a test state and a limiting resistor R connected with the semiconductor switch T1 in serieslimitWherein is semi-conductingThe body switch T1 is controlled by an on driving signal PWM-Drive;
with the semiconductor switch T1 in the OFF state, an adjustable voltage source V is usedadjThe energy storage capacitor C1 is charged to a required voltage state, after the energy storage capacitor C1 is charged to the required voltage state, a turn-on driving signal PWM-Drive is used for controlling the semiconductor switch T1 to be conducted, and after the semiconductor switch T1 is conducted, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the test discharge part so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; and measuring the voltage of the power semiconductor to be measured by using a voltage measuring device within the effective time range of turning on the driving signal PWM-Drive so as to obtain the required conduction voltage drop.
Specifically, the power semiconductor device to be tested may be a commonly used semiconductor device, such as a diode, an IGBT, a MOSFET, a HEMT (High Electron Mobility Transistor), an SCR (Thyristor), a GTO (turn-off Thyristor), an IGCT (Integrated Gate-shared Thyristor), and the like, and the specific form of the power semiconductor device to be tested may be selected as needed, and is not described herein again. In order to realize the conduction voltage drop test of the power semiconductor device to be tested, a current source is required to provide current pulses required by the test of the power semiconductor device, during the test, a first test connecting end of the power semiconductor device to be tested is electrically connected with a current output end of the current source, and a second test connecting end of the power semiconductor device to be tested and a grounding end of the current source are both grounded.
In the embodiment of the present invention, the current source includes the energy storage capacitor C1, and generally, the capacitance value of the energy storage capacitor C1 needs to be large enough to ensure that no significant voltage drop occurs during the discharging process, so the specific capacitance value of the energy storage capacitor C1 may be related to the type of the power semiconductor to be measured, and the like, so as to ensure that no significant voltage drop occurs during the discharging process of the energy storage capacitor C1, which is not described herein again. Using an adjustable voltage source VadjCan charge the energy storage capacitor C1 and has an adjustable voltage source VadjThe voltage to charge the energy storage capacitor C1 is based on the requirement of conducting pulse voltage drop test, and generally, the voltage source V is adjustableadjAnd storeEnergy capacitor C1 parallel connection, adjustable voltage source VadjSpecifically, the conventional common form can be adopted, so that the required voltage for the energy storage capacitor C1 can be satisfied, and details are not described herein.
During specific implementation, in order to control the process of conducting voltage drop, the energy storage capacitor C1 is connected with the first test connecting end of the power semiconductor device to be tested in an adaptive mode through the test discharge part, the energy storage capacitor C1 can discharge the power semiconductor device to be tested through the test discharge part, the discharge state of the energy storage capacitor C1 can be controlled through the test discharge part, and the discharge of the energy storage capacitor C1 to the power semiconductor device to be tested is controlled if the discharge state is opened or closed.
In the embodiment of the invention, the test discharge part comprises a semiconductor switch T1 for controlling the test state and a limiting resistor R connected with the semiconductor switch T1 in serieslimitWherein, the semiconductor switch T1 is controlled by the turn-on driving signal PWM-Drive; in a specific implementation, the semiconductor switch T1 is a fully-controlled semiconductor device, and the semiconductor switch T1 includes an IGBT, an IGCT, a MOSFET, a JFET, a GTO (gate turn-off thyristor), or a HEMT. The type of the semiconductor switch T1 may be specifically selected as required so as to meet the requirement of being turned on by the turn-on driving signal PWM-Drive, generally, the turn-on driving signal PWM-Drive is loaded to the controlled terminal of the semiconductor switch T1, if the semiconductor switch T1 is a MOSFET device or an IGBT device, the turn-on driving signal PWM-Drive is loaded to the gate terminal of the semiconductor switch T1, and after loading, the turn-on driving signal PWM-Drive can be controlled to be turned on, the level state of the turn-on driving signal PWM-Drive can be effectively satisfied to control the turn-on of the semiconductor switch T1, when the turn-on driving signal PWM-Drive is removed, the semiconductor switch T1 recovers the turn-off state, and when the semiconductor switch T1 is turned off, the electric energy of the energy storage capacitor C1 cannot discharge the power semiconductor device to be tested through the test discharge portion.
By means of a limiting resistor RlimitCan regulate and control the current pulse loaded to the power semiconductor device to be tested, and limit the resistance RlimitWhen different, the obtained current pulses have different sizes. In specific implementation, RT1+RDUT<<RlimitWherein R isT1Is the on-resistance, R, of the semiconductor switch T1DUTIs the on-resistance of the power semiconductor device to be tested.
In specific implementation, when the power semiconductor device to be tested is subjected to the current source, generally, the semiconductor switch T1 needs to be turned off first, and at this time, the adjustable voltage source V is usedadjCharging the energy storage capacitor C1 to the required voltage state, and adjusting the voltage source VadjThe charging process of the energy storage capacitor C1 is related to the size of the energy storage capacitor C1 and the voltage to be charged by the energy storage capacitor C1, and is specifically consistent with the prior art, and is well known in the art, and will not be described herein again.
After the energy storage capacitor C1 is charged to the required voltage state, the semiconductor switch T1 is turned on by an on-driving signal PWM-Drive. After the semiconductor switch T1 is in the on state, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the test discharge portion, that is, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the semiconductor switch T1 and the limiting resistor RlimitDischarging the power semiconductor device to be tested so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; and measuring the voltage of the power semiconductor to be measured by using a voltage measuring device within the effective time range of turning on the driving signal PWM-Drive so as to obtain the required conduction voltage drop. The valid time range for turning on the driving signal PWM-Drive specifically refers to the time range for driving the semiconductor switch T1 to be turned on, i.e. the tp range in fig. 6, 8 and 9.
In the embodiment of the invention, the width of the current pulse loaded to the power semiconductor device to be tested is consistent with the effective time range of the turn-on driving signal PWM-Drive, and the width of the current pulse loaded to the power semiconductor device to be tested is 2-2000 mus. The pulse width control of the constant current pulse loaded to the power semiconductor device to be tested can be realized through the on-state driving signal PWM-Drive, the on-state voltage drop test under the narrow pulse can be realized by selecting the corresponding effective time of the on-state driving signal PWM-Drive according to the required pulse width, and certainly, the on-state voltage drop test of other pulses with required widths can also be realized, and the on-state voltage drop test can be specifically selected according to the requirement.
In specific implementation, the voltage measuring device includes a voltmeter, the voltmeter is connected in parallel with the power semiconductor device to be measured, and the specific model of the voltmeter can be selected according to the type of the power semiconductor device to be measured and the specific situation of the conduction voltage drop so as to meet the actual measurement of the conduction voltage drop, which is not repeated herein.
In summary, during the turn-on period of the semiconductor switch T1, the current applied to the semiconductor device under test is Iforce=Vadj/(RT1+Rlimit+RDUT). Wherein R isT1Is the on-resistance, R, of the semiconductor switch T1DUTFor the on-resistance, V, of the power semiconductor device to be tested adjI.e. the voltage charged by the energy storage capacitor C1. Due to RT1+RDUT<<RlimitThus, current Iforce=Vadj/(RT1+Rlimit+RDUT)≈Vadj/Rlimit. Thus, only by adjusting the voltage VadjThe current I required by the test can be obtainedforce。
In particular by using a voltage V which is as high as possibleadjAnd a resistance R as large as possiblelimitIs favorable for increasing the current IforceAnd (4) precision. For example, assume that the on-resistance RT1And an on-resistance RDUTAre all 50m omega; to obtain a test current of 100A, V can be setadj=100V，Rlimit=1 Ω, the resulting current Iforce=100V/1.1 Ω =91A, error 9.1%. But if order Vadj=100V，Rlimit=10 Ω, the resulting test current Iforce=1000V/10.1 Ω =99A with an error of 1%.
On-resistance R to semiconductor switch T1T1The introduced error can be further improved, and R can be adjustedT1The on-state capacitance of the capacitor is reduced to a very low level, for example, by using FF2MR12KM1 from Infineon, which has an on-state capacitance of only 2m Ω. RT1Is a definite value, the voltage V can be increased appropriatelyadjTo compensate for the on-resistance R of the semiconductor switch T1 being conductiveT1The error introduced. For example: let R beT1=10mΩ，Rlimit=1 Ω, neglecting the on-resistance of the power semiconductor device to be testedRDUT. To obtain a test current of 100A, V can be setadj=101V，RDUTThe introduced error can be further improved, and the on-resistance R of the power semiconductor device to be measured can be estimated DUTValue, regulation voltage VadjTo compensate for the error.
Furthermore, the actual current value I can be determined by a plurality of pretestsforceTo adjust the voltage VadjUntil the actual pulse current is sufficiently close to the target pulse current. The specific method is that if the actual current is less than the target value, the voltage V is increasedadjIf the actual current is greater than the target value, the voltage V is decreasedadj。
As shown in fig. 6, when the power semiconductor device to be tested is a power diode, the anode end of the power diode forms a first test connection end, and the cathode end of the power diode forms a second test connection end. Specifically, one end of the energy storage capacitor C1 is connected to one end of the semiconductor switch T1, and the semiconductor switch T1 passes through the limiting resistor RlimitThe other end of the capacitor C1 and the cathode end of the power diode are both grounded.
As shown in fig. 7, a waveform diagram when conducting a conduction voltage drop test on a power semiconductor device is shown, where T1-T3 is a conduction time period of a semiconductor switch T1, T1-T2 is an unsteady state time period caused by a process of establishing a distribution of carriers inside a diode, and T2-T3 is a time period after the distribution of carriers inside the diode is stabilized. The conduction voltage drop is tested within the time period of t 2-t 3, and a section of measurement voltage V can be collected measAnd averaging after the waveform to obtain the conduction voltage drop. T1 to T3 are the conduction time periods of the semiconductor switch T1, i.e. the effective time for controlling the conduction of the semiconductor switch T1 by the turn-on driving signal PWM-Drive. In FIG. 7, current IforceI.e. the constant current pulse to the power semiconductor device (i.e. diode) to be tested, Tvj is the junction temperature of the diode during testing. the time periods T0-T1 and T3-T4 are that the semiconductor switch T1 is turned off, VT1GThe gate voltage waveform of the semiconductor switch T1 is a waveform diagram of the turn-on driving signal PWM-Drive. When the turn-on Drive signal PWM-Drive is higher than the threshold voltage of the semiconductor switch T1,the semiconductor switch T1 turns on. When the turn-on driving signal PWM-Drive voltage is lower than the threshold voltage of the semiconductor switch T1, the semiconductor switch T1 is turned off.
Further, when the power semiconductor device to be tested is a controllable semiconductor device, the power semiconductor device to be tested further comprises a bias power supply for driving the power semiconductor device to be tested; when the power semiconductor device to be tested is tested, the bias power supply is utilized to drive the power semiconductor device to be tested to be in a conducting state.
Fig. 8 is a schematic diagram of a conduction voltage drop test when the controllable semiconductor device is an IGBT, fig. 9 is a schematic diagram of a conduction voltage drop test when the controllable semiconductor device is an MOSFET, and the connection and matching form between the power semiconductor device to be tested and the current source in fig. 8 and fig. 9 can refer to the description of fig. 6, which is not described herein again. According to the type of the controllable semiconductor device, a bias power supply is provided, and the bias power supply is utilized to drive the power semiconductor device to be tested to be in a conducting state, so that the conducting voltage drop of the power semiconductor device to be tested can be measured, and the specific situation of the bias power supply is accurate to meet the conducting requirement when the power semiconductor device to be tested is the controllable semiconductor device, and is particularly known by people in the technical field, and is not repeated herein.
In summary, the narrow pulse conduction voltage drop test circuit suitable for the power semiconductor device can be obtained, and comprises a current source for conducting voltage drop test of the power semiconductor device to be tested, wherein the current source is in adaptive connection with a first test connecting end of the power semiconductor device to be tested, and a second test connecting end of the power semiconductor device to be tested and a grounding end of the current source are both directly grounded;
the current source comprises an energy storage capacitor C1 and an adjustable voltage source V for charging the energy storage capacitor C1adjThe energy storage capacitor C1 is connected with a first test connection end of the power semiconductor device to be tested in an adaptive manner through a test discharge part, and the test discharge part comprises a semiconductor switch T1 for controlling a test state and a limiting resistor R connected with the semiconductor switch T1 in serieslimitWherein, the semiconductor switch T1 is controlled by the turn-on driving signal PWM-Drive;
when the semiconductor switch T1 is in the OFF state, use is made ofAdjustable voltage source VadjThe energy storage capacitor C1 is charged to a required voltage state, after the energy storage capacitor C1 is charged to the required voltage state, a turn-on driving signal PWM-Drive is used for controlling the semiconductor switch T1 to be conducted, and after the semiconductor switch T1 is conducted, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the test discharge part so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; and measuring the voltage of the power semiconductor to be measured by using a voltage measuring device within the effective time range of turning on the driving signal PWM-Drive so as to obtain the required conduction voltage drop.
Specifically, the current source and the conduction voltage drop test process of the power semiconductor device to be tested using the current source can refer to the above description, and are not described herein again.
Claims (10)
1. A narrow pulse conduction voltage drop test method suitable for a power semiconductor device is characterized by comprising the following steps: providing a current source for conducting voltage drop test of the power semiconductor device to be tested, wherein the current source is in adaptive connection with the first test connecting end of the power semiconductor device to be tested, and the second test connecting end of the power semiconductor device to be tested and the grounding end of the current source are both directly grounded;
the current source comprises an energy storage capacitor C1 and an adjustable voltage source V for charging the energy storage capacitor C1adjThe energy storage capacitor C1 is connected with a first test connection end of the power semiconductor device to be tested in an adaptive manner through a test discharge part, and the test discharge part comprises a semiconductor switch T1 for controlling a test state and a limiting resistor R connected with the semiconductor switch T1 in serieslimitWherein, the semiconductor switch T1 is controlled by the turn-on driving signal PWM-Drive;
with the semiconductor switch T1 in the OFF state, an adjustable voltage source V is usedadjCharging the energy storage capacitor C1 to a required voltage state, controlling the semiconductor switch T1 to be conducted by utilizing a turn-on driving signal PWM-Drive after the energy storage capacitor C1 is charged to the required voltage state, and discharging the power semiconductor device to be tested by the energy storage capacitor C1 through the test discharge part after the semiconductor switch T1 is conducted so as to load a conduction to the power semiconductor device to be tested A current pulse for voltage drop test; and measuring the voltage of the power semiconductor to be measured by using a voltage measuring device within the effective time range of turning on the driving signal PWM-Drive so as to obtain the required conduction voltage drop.
2. The narrow pulse turn-on voltage drop test method for the power semiconductor device as claimed in claim 1, wherein: the semiconductor switch T1 is a fully-controlled semiconductor device, and the semiconductor switch T1 comprises an IGBT, an IGCT, a MOSFET, a JFET, a GTO or a HEMT.
3. The narrow pulse turn-on voltage drop test method for the power semiconductor device as claimed in claim 1, wherein: the width of the current pulse loaded to the power semiconductor device to be tested is consistent with the effective time range of the PWM-Drive signal, and the width of the current pulse loaded to the power semiconductor device to be tested is 2-2000 mu s.
4. The narrow pulse turn-on voltage drop test method suitable for the power semiconductor device according to any one of claims 1 to 3, wherein: when the power semiconductor device to be tested is a power diode, the anode end of the power diode forms a first test connecting end, and the cathode end of the power diode forms a second test connecting end.
5. The narrow pulse turn-on voltage drop test method suitable for the power semiconductor device according to any one of claims 1 to 3, wherein: when the power semiconductor device to be tested is a controllable semiconductor device, the power semiconductor device to be tested also comprises a bias power supply for driving the power semiconductor device to be tested; when the power semiconductor device to be tested is tested, the bias power supply is utilized to drive the power semiconductor device to be tested to be in a conducting state.
6. The narrow pulse turn-on voltage drop test method suitable for the power semiconductor device according to any one of claims 1 to 3, wherein: the voltage measuring device comprises a voltmeter.
7. The narrow pulse turn-on voltage drop test method suitable for the power semiconductor device according to any one of claims 1 to 3, wherein: rT1+RDUT<<RlimitWherein R isT1Is the on-resistance, R, of the semiconductor switch T1DUTThe on-resistance of the power semiconductor device to be tested.
8. A narrow pulse conduction voltage drop test circuit suitable for a power semiconductor device is characterized in that: the testing device comprises a current source for conducting voltage drop testing of a power semiconductor device to be tested, wherein the current source is in adaptive connection with a first testing connecting end of the power semiconductor device to be tested, and a second testing connecting end of the power semiconductor device to be tested and a grounding end of the current source are both directly grounded;
The current source comprises an energy storage capacitor C1 and an adjustable voltage source V for charging the energy storage capacitor C1adjThe energy storage capacitor C1 is connected with the first test connection end of the power semiconductor device to be tested in an adaptive manner through a test discharge part, and the test discharge part comprises a semiconductor switch T1 for controlling a test state and a limiting resistor R connected with the semiconductor switch T1 in serieslimitWherein, the semiconductor switch T1 is controlled by the turn-on driving signal PWM-Drive;
with the semiconductor switch T1 in the OFF state, an adjustable voltage source V is usedadjThe energy storage capacitor C1 is charged to a required voltage state, after the energy storage capacitor C1 is charged to the required voltage state, a turn-on driving signal PWM-Drive is used for controlling the semiconductor switch T1 to be conducted, and after the semiconductor switch T1 is conducted, the energy storage capacitor C1 discharges the power semiconductor device to be tested through the test discharge part so as to load a current pulse for conducting voltage drop test on the power semiconductor device to be tested; and measuring the voltage of the power semiconductor to be measured by using a voltage measuring device within the effective time range of turning on the driving signal PWM-Drive so as to obtain the required conduction voltage drop.
9. The narrow pulse turn-on voltage drop test circuit suitable for the power semiconductor device as claimed in claim 8, wherein: the width of the current pulse loaded to the power semiconductor device to be tested is consistent with the effective time range of the turn-on driving signal PWM-Drive, and the width of the current pulse loaded to the power semiconductor device to be tested is 2-2000 mus.
10. The narrow pulse turn-on voltage drop test circuit suitable for the power semiconductor device according to claim 8 or 9, wherein: r isT1+RDUT<<RlimitWherein R isT1Is the on-resistance, R, of the semiconductor switch T1DUTIs the on-resistance of the power semiconductor device to be tested.
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