CN114430270A - High-precision capacitor voltage converter based on hold error correction technology - Google Patents
High-precision capacitor voltage converter based on hold error correction technology Download PDFInfo
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- CN114430270A CN114430270A CN202111459416.6A CN202111459416A CN114430270A CN 114430270 A CN114430270 A CN 114430270A CN 202111459416 A CN202111459416 A CN 202111459416A CN 114430270 A CN114430270 A CN 114430270A
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
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- H—ELECTRICITY
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- H03F3/70—Charge amplifiers
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Abstract
The invention discloses a high-precision capacitance-voltage converter based on a hold error correction technology, which comprises: the device comprises a voltage excitation source, an external capacitance sensor, a common-mode charge controller, a differential charge amplifier, a gain error corrector and a holding error corrector; the voltage excitation source is used for generating an excitation signal to excite the external capacitance sensor to generate a charge signal; the common-mode charge controller is used for absorbing a common-mode component in the charge signal so as to inhibit common-mode charge interference; the differential charge amplifier is used for converting the differential component of the charge signal into a voltage signal; the gain error corrector is used for correcting the gain error generated by the differential charge amplifier; the hold error corrector corrects a hold error in the gain error corrector. The invention can restrain the loss of output voltage caused by holding error and improve the gain precision.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a high-precision capacitance-to-voltage converter based on a hold error correction technology.
Background
With the continuous progress of semiconductor technology, the device size is continuously reduced, and the requirement for the precision of the MEMS (Micro-Electro-Mechanical System) capacitive sensor interface circuit is higher and higher. Modern high-energy-efficiency amplifiers such as Inverter-based amplifiers (IBA) and Dynamic Amplifiers (DA) cannot be applied to high-precision MEMS capacitive sensor interface circuits due to low open-loop gain.
In particular, due to parasitic capacitances, the closed loop feedback coefficient of the interface circuit front-end amplifier is very low (e.g., -40dB), which requires the amplifier to have a high gain (e.g., 80dB) to achieve low gain error (e.g., < 1%) and low gain drift. While the gain of a high-energy amplifier such as IBA open loop is usually very low (e.g., around 30 dB), the gain error requirement cannot be met. Even though the conventional MEMS capacitive sensor capacitor-to-voltage conversion circuit uses the gain error corrector to boost the equivalent gain, since the gain error corrector has a hold error, the equivalent gain can be actually boosted by only 2 steps (i.e. 30dB to 60dB), which still cannot meet the requirement of gain error.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a high-precision capacitor-voltage converter based on a hold-error correction technique. The technical problem to be solved by the invention is realized by the following technical scheme:
a high accuracy capacitive voltage converter based on hold-error correction techniques, the converter comprising: the device comprises a voltage excitation source, an external capacitance sensor, a common-mode charge controller, a differential charge amplifier, a gain error corrector and a holding error corrector; the voltage excitation source is connected with the external capacitance sensor and used for generating an excitation signal to excite the external capacitance sensor to generate a charge signal; the common-mode charge controller is connected with the external capacitance sensor and used for absorbing common-mode components in the charge signals so as to inhibit common-mode charge interference; the differential charge amplifier is connected with the common-mode charge controller and is used for converting the differential component of the charge signal into a voltage signal; the gain error corrector is connected with the differential charge amplifier and is used for correcting the gain error generated by the differential charge amplifier; the holding error corrector is connected with the gain error corrector and the differential charge amplifier and is used for correcting the holding error in the gain error corrector.
In one embodiment of the invention, the external capacitive sensor comprises a first sensing capacitance and a second sensing capacitance; one polar plate of the first sensing capacitor is connected with one polar plate of the second sensing capacitor to form a common electrode of the sensing unit; the other electrode plate of the first sensing capacitor and the other electrode plate of the second sensing capacitor form a first differential electrode and a second differential electrode of the sensing unit respectively, wherein the first differential electrode and the second differential electrode are connected to the input end of the differential charge amplifier to form a fully differential capacitor voltage structure.
In one embodiment of the invention, the common mode charge controller comprises a common mode amplifier, a common mode feedback capacitor; the input end of the common mode amplifier is connected across the first differential electrode and the second differential electrode; two differential feedback capacitors are connected across the output end of the common mode amplifier, the first differential electrode and the second differential electrode.
The invention has the beneficial effects that:
the invention can restrain the loss of output voltage caused by holding error and improve the gain precision.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic structural diagram of a high-precision capacitive-to-voltage converter based on a hold-error correction technique according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a charge-to-voltage conversion network in a conventional capacitive-to-voltage converter;
FIG. 3 is a schematic circuit diagram of a charge-to-voltage conversion network in a capacitance-to-voltage conversion circuit based on a hold error correction technique according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram illustrating a technique for error correction according to an embodiment of the present invention;
fig. 5 is a circuit diagram illustrating an internal connection relationship of a capacitor voltage converter employing a two-stage hold-error corrector according to an embodiment of the present invention.
Description of reference numerals:
101-a capacitive sensor; 102-voltage excitation source; 103-common mode charge controller; 104-differential charge amplifier; 105-holding an error corrector; 106-gain error corrector; 201-hold error sampling network; 202-hold error correction network; 203-differential amplifier.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a charge-to-voltage conversion network in a conventional capacitive-to-voltage converter.
The circuit architecture includes: a differential charge amplifier 104 and a gain error corrector 106, wherein the differential charge amplifier 104 is formed by an integrating capacitor CIAnd a differential amplifier A0The gain error corrector 106 is composed of a holding capacitor CH0And calibrating the capacitance CC0And (4) forming. The interface circuit has two operating phases Φ 1 and Φ 2 in common. In the phi 1 stage of the first period, all the capacitors including the sensing capacitor are set, and the output voltage is in a holding state under the action of the holding capacitor; in the phi 2 phase of the first cycle, the sensing capacitor in the capacitive sensor 101 is subjected to step voltage signals V with opposite phases through the differential portRIs activated to generate a charge signal representative of the difference in capacitance, which is transferred to a differential charge amplifier, ideally by an integrating capacitor CIAll absorbed and converted into output voltage signals, and the expression of the output voltage is as follows:
wherein, Δ C is the capacitance value change generated by the sensing capacitance in the capacitance sensor under the excitation of the physical signal, and V isRThe magnitude of the step voltage signal generated for the excitation source.
In practical cases, since the actual operational amplifier gain is not infinite, a gain error occurs, and as a result, the output voltage value expression becomes:
wherein σdThe expression of the deterioration factor is as follows:
in the phi 1 phase of the second cycle, the capacitor CH0And a capacitor CC0Connected to the amplifier and forming a feedback loop with the amplifier such that the capacitor C is in the first sampling periodH0The output voltage is stored as a gain error in a calibration capacitor CC0In (1). As the operation period gradually increases, the error term is gradually absorbed, and the output gradually climbs to an ideal value, which is expressed as:
however, the actual response of the conventional capacitance-voltage conversion circuit still has a holding error phenomenon, namely, the holding error phenomenon is caused by the holding capacitor C when the phase is switched from the phase phi 2 to the phase phi 1H0The voltage jump of the left plate causes the output voltage to have an unexpected level drop, so that the output voltage value expression becomes:
the percentage error of gain accuracy is calculated as:
as can be seen from the formula (6), the capacitance-voltage conversion circuit of the MEMS capacitive sensor has a limited capability of improving the gain accuracy, and due to the existence of the holding error, the equivalent gain of the amplifier can only be improved by 2 orders, which cannot meet the requirement of the gain error.
In order to solve the problem that the capacity of improving the gain precision of a capacitance-voltage conversion circuit of a traditional MEMS capacitive sensor is limited, the invention provides a hold error correction technology, and the gain precision is further improved by eliminating a hold error generated by a gain error corrector.
Examples
Referring to fig. 1, fig. 1 is a schematic structural diagram of a high-precision capacitance-to-voltage converter based on a hold error correction technique according to an embodiment of the present invention, where the converter includes:
a voltage excitation source 102, an external capacitance sensor 101, a common mode charge controller 103, a differential charge amplifier 104, a gain error corrector 106, and a hold error corrector 105.
The voltage excitation source 102 is connected to the external capacitive sensor 101 for generating an excitation signal to excite the external capacitive sensor to generate a charge signal.
It should be noted that the voltage excitation source generates a step voltage with a certain amplitude to excite the capacitive sensor, and the excitation is mainly rectangular.
The common mode charge controller 103 is connected to the external capacitive sensor 101 for absorbing a common mode component in the charge signal to suppress common mode charge interference.
The differential charge amplifier 104 is connected to the common mode charge controller 103 for converting the differential component of the charge signal into a voltage signal.
The differential signal read can be realized by converting the differential component of the charge signal into a voltage signal.
The gain error corrector 106 is connected to the differential charge amplifier 104 for correcting the gain error generated by the differential charge amplifier.
Specifically, gain errors of the differential charge amplifier are absorbed to improve gain accuracy.
The hold error corrector 105 is connected to the gain error corrector 106 and the differential charge amplifier 104, and corrects a hold error in the gain error corrector.
Specifically, the hold error generated by the gain error corrector is absorbed to further improve the gain accuracy.
Optionally, the external capacitive sensor comprises a first sensing capacitance and a second sensing capacitance.
One pole plate of the first sensing capacitor is connected with one pole plate of the second sensing capacitor to form a common electrode of the sensing unit.
The other electrode plate of the first sensing capacitor and the other electrode plate of the second sensing capacitor form a first differential electrode and a second differential electrode of the sensing unit, respectively, wherein the first differential electrode and the second differential electrode are connected to the input end of the differential charge amplifier to form a fully differential capacitor voltage structure, i.e., a fully differential-to-voltage converter (CVC) structure.
Optionally, the common mode charge controller includes a common mode amplifier and a common mode feedback capacitor.
The input end of the common mode amplifier is connected across the first differential electrode and the second differential electrode.
It should be noted that, the common mode charge controller is connected to two differential electrodes of the external capacitance sensor, and is used for reading out a common mode component in the charge signal and converting the common mode component into a common mode voltage, so as to suppress common mode charge interference.
Two differential feedback capacitors are connected across the output end of the common mode amplifier, the first differential electrode and the second differential electrode.
Optionally, the differential charge amplifier includes a charge-to-voltage conversion network and a differential amplifier.
The charge-voltage conversion network is composed of an integrating capacitor CIAnd (4) forming.
The differential amplifier is composed of a differential operational amplifier A0And (4) forming.
Optionally, the gain error corrector comprises a holding capacitor CH0And calibrating the capacitance CC0。
Optionally, the hold error corrector comprises two gain buffers of one unit and a sampling capacitor CH1。
Optionally, the input end and the output end of the holding error corrector are connected with the left plate of the holding capacitor of the differential charge amplifier.
Optionally, the connecting the common mode charge controller to the external capacitance sensor includes:
the common-mode charge controller is connected with the first differential electrode and the second differential electrode of the sensing unit of the external capacitance sensor.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a charge-voltage conversion network in a capacitance-voltage conversion circuit based on a hold error correction technique according to an embodiment of the present invention.
The improved charge-voltage conversion network provided by the invention mainly comprises a differential charge amplifier 104, a gain error corrector 106 and a holding error corrector 105. A first-stage holding error corrector 105 is added on the basis of the internal structure of the traditional charge-voltage conversion network and is used for eliminating the holding error in the gain error corrector so as to further improve the gain precision. The holding error corrector 105 is composed of a unity gain amplifier and a holding capacitor CH1A structure in which an input/output port is connected to the holding capacitor CH0The left polar plate of the device completes the correction of the holding error through a clock signal and a switch. In the conventional capacitance-voltage conversion circuit structure of the MEMS capacitive sensor shown in fig. 1, the holding capacitance C is maintained at the Φ 2 stageH0The left polar plate is grounded, so the voltage value of the left polar plate is zero, and the differential operational amplifier input end, namely the left polar plate C of the holding capacitor at the phi 1 stageH0The voltage value of the access position is not zero, so that voltage jump can occur on the left electrode plate of the holding capacitor at the moment of conversion between the phase phi 2 and the phase phi 1, voltage loss occurs on the input port of the differential amplifier, and further loss occurs on the output voltage value, namely, a holding error. The invention is realized by maintaining the capacitanceCH0A first-stage hold error corrector is added on the left polar plate, and in a phi 1 stage, the input voltage value of the differential amplifier A0 is sampled to a hold error sampling capacitor CH1And transfers the sampled voltage to the holding capacitor C in the phi 2 phaseH0Left side plate, thereby making the holding capacitance CH0The voltage value of the left polar plate is the same as the input voltage value of the differential operational amplifier, so that the voltage jump at the moment of conversion between the phi 2 stage and the phi 1 stage can be avoided, the loss of output voltage is reduced, and the gain precision is improved.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of a hold error correction technique according to an embodiment of the present invention. Fig. 4 shows an implementation of the hold error corrector 105 according to the present invention, but is not limited to this circuit implementation. The embodiment keeps the specific circuit of the error corrector 105 in the configuration of a differential charge amplifier as shown in fig. 4: comprising a holding error sampling network 201, a gain error correction network 202 and a differential amplifier 203, VGHolding capacitor C in port connection main differential charge amplifierH0At the phase phi 1, the switch phi 1 is closed, the switch phi 2 is opened, and the error sampling capacitor C is keptSH1Charged to realize error sampling; in the phase phi 2, the switch phi 2 is closed, the switch phi 1 is opened, the sampling voltage is output through the gain error corrector 202 and the differential amplifier 203, and the holding capacitor C is further raisedH0The voltage of the left pole plate is used for inhibiting the loss of the output voltage caused by the holding error.
Theoretically, the percentage error of gain accuracy after using a first-order hold error corrector becomes:
that is, theoretically, the equivalent gain of the amplifier can be raised by 4 steps by using a one-step holding error corrector.
Further, referring to fig. 5, fig. 5 is a circuit diagram of an internal connection relationship of a capacitor voltage converter employing a two-stage hold error corrector according to an embodiment of the present invention. The two-stage error corrector 105 has the same internal structure and the second stageInput port V ofG2A holding capacitor C connected to the first stageH1The left pole plate of (1). Because the holding error corrector 105 also has a holding error, when the gain accuracy still cannot meet the requirement after the holding error corrector 105 is adopted in one stage, in order to further eliminate the holding error of the holding error corrector, higher gain can be realized by increasing the stage number of the holding error corrector 105. The hold-in error can theoretically be reduced infinitely by nesting infinite stages of hold-in error correctors 105 such that the gain precision percentage error approaches zero infinitely. Similarly, the input port V of the Nth stageGNHolding capacitor C connected to the upper stageH(N-1)On the left side plate.
The capacitor voltage conversion circuit provided by the invention introduces a holding error corrector by using a holding capacitor CH0The voltage of the left pole plate is raised to VO/A1The loss of the output voltage caused by the holding error is restrained, and the gain precision is further improved. Specifically, the invention can improve the equivalent gain by 4 orders (namely, 30dB to 120dB), so that the application of the high-energy-efficiency amplifier to a high-precision MEMS capacitive sensor interface circuit becomes possible.
In summary, the present invention introduces a hold error corrector based on the hold error correction technique, and can further improve the gain accuracy by correcting the hold error. Further, higher gain accuracy is achieved by increasing the number of stages of the nested holding error correctors, theoretically, the nested infinite multi-stage holding error correctors can infinitely reduce the holding error, and the percentage error of the gain accuracy approaches zero infinitely.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "connected" and the like are to be construed broadly, e.g., as meaning fixedly attached, detachably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (8)
1. A high accuracy capacitive voltage converter based on hold-error correction techniques, said converter comprising:
the device comprises a voltage excitation source, an external capacitance sensor, a common-mode charge controller, a differential charge amplifier, a gain error corrector and a holding error corrector; wherein,
the voltage excitation source is connected with the external capacitance sensor and used for generating an excitation signal to excite the external capacitance sensor to generate a charge signal;
the common-mode charge controller is connected with the external capacitance sensor and used for absorbing common-mode components in the charge signals so as to inhibit common-mode charge interference;
the differential charge amplifier is connected with the common-mode charge controller and is used for converting the differential component of the charge signal into a voltage signal;
the gain error corrector is connected with the differential charge amplifier and is used for correcting the gain error generated by the differential charge amplifier;
the holding error corrector is connected with the gain error corrector and the differential charge amplifier and is used for correcting the holding error in the gain error corrector.
2. The transducer of claim 1, wherein the external capacitive sensor comprises a first sense capacitance and a second sense capacitance; wherein,
one polar plate of the first sensing capacitor is connected with one polar plate of the second sensing capacitor to form a common electrode of the sensing unit;
the other electrode plate of the first sensing capacitor and the other electrode plate of the second sensing capacitor form a first differential electrode and a second differential electrode of the sensing unit respectively, wherein the first differential electrode and the second differential electrode are connected to the input end of the differential charge amplifier to form a fully differential capacitor voltage structure.
3. The converter of claim 2, wherein the common mode charge controller comprises a common mode amplifier, a common mode feedback capacitance;
the input end of the common mode amplifier is connected across the first differential electrode and the second differential electrode;
two differential feedback capacitors are connected across the output end of the common mode amplifier, the first differential electrode and the second differential electrode.
4. The converter of claim 1, wherein the differential charge amplifier comprises a charge-to-voltage conversion network and a differential amplifier; wherein,
the charge-voltage conversion network is composed of an integrating capacitor CIForming;
the differential amplifier is composed of a differential operational amplifier A0And (4) forming.
5. Converter according to claim 1, characterized in that the gain error corrector comprises a holding capacitor CH0And calibrating the capacitance CC0。
6. The converter of claim 1, wherein the hold-error corrector comprises a two-unit gain buffer and a sampling capacitor CH1。
7. The converter according to claim 1, wherein the input and output of the hold-error corrector are connected to the left plate of the hold capacitor of the differential charge amplifier.
8. The converter of claim 1, wherein the common mode charge controller coupled to an external capacitive sensor comprises:
the common-mode charge controller is connected with the first differential electrode and the second differential electrode of the sensing unit of the external capacitance sensor.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116545428A (en) * | 2023-07-05 | 2023-08-04 | 成都市晶蓉微电子有限公司 | High-precision capacitance-to-voltage conversion error trimming circuit and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116545428A (en) * | 2023-07-05 | 2023-08-04 | 成都市晶蓉微电子有限公司 | High-precision capacitance-to-voltage conversion error trimming circuit and method |
| CN116545428B (en) * | 2023-07-05 | 2023-09-26 | 成都市晶蓉微电子有限公司 | High-precision capacitance-to-voltage conversion error trimming circuit and method |
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