CN114420690A - ESD protection structure and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 92
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 92
- 239000010703 silicon Substances 0.000 claims abstract description 92
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 81
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 81
- 238000002955 isolation Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000003068 static effect Effects 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Abstract
The present invention provides an ESD protection structure, comprising: the fully depleted silicon-on-insulator comprises a silicon substrate, a buried oxide layer and top silicon from bottom to top; the silicide layer is formed on the upper surface of the buried oxide layer and formed on two sides of the top silicon layer; the gate oxide layer is formed on the upper surface of the top layer silicon; the isolation layer is formed on the upper surface of part of the silicide layer and formed on two sides of the gate oxide layer; the control gate is formed on the upper surface of a part of the gate oxide layer; the programmable gate is formed on the upper surfaces of part of the gate oxide layer and part of the isolation layer adjacent to the gate oxide layer and formed on two sides of the control gate, and a space is reserved between the programmable gate and the control gate; the source electrode is formed on the upper surface of the silicide layer on one side of the top silicon layer and is formed on one side, far away from the programmable gate, of the isolation layer; and the drain electrode is formed on the upper surface of the silicide layer on the other side of the top layer silicon and is formed on one side, away from the programmable gate, of the isolation layer. The ESD protection structure provided by the invention solves the problem of high static electricity leakage of the existing structure.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an ESD protection structure and a preparation method thereof.
Background
Electrostatic discharge (ESD) protection of a chip is an important link, and a chip can resist ESD by using a conventional silicon controlled protection structure and other structures, however, static leakage of the devices is high (static leakage of ESD devices when the chip normally works), and requirements for ultra-low leakage, such as leakage requirements of high-precision instrument amplifiers such as ultra-low bias current amplifiers, are difficult to meet.
Therefore, designing an ESD protection structure with ultra-low leakage has become one of the technical problems that those skilled in the art are eagerly required to solve.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an ESD protection structure and a method for manufacturing the same, which are used to solve the problem of high static leakage of the conventional ESD protection structure.
To achieve the above and other related objects, the present invention provides an ESD protection structure, comprising:
the fully depleted silicon-on-insulator comprises a silicon substrate, a buried oxide layer and top silicon in sequence from bottom to top;
the silicide layer is formed on the upper surface of the buried oxide layer and formed on two sides of the top silicon layer;
the gate oxide layer is formed on the upper surface of the top layer silicon;
the isolation layer is formed on the upper surface of part of the silicide layer and formed on two sides of the gate oxide layer;
the control gate is formed on the upper surface of part of the gate oxide layer;
the programmable gate is formed on the upper surfaces of part of the gate oxide layer and part of the isolation layer adjacent to the gate oxide layer, and is formed on two sides of the control gate, wherein a space is reserved between the programmable gate and the control gate;
the source electrode is formed on the upper surface of the silicide layer on one side of the top silicon layer and is formed on one side, far away from the programmable gate, of the isolation layer;
and the drain electrode is formed on the upper surface of the silicide layer on the other side of the top layer silicon and is formed on one side, far away from the programmable gate, of the isolation layer.
Optionally, the control gate is formed in a central position of the gate oxide layer; the two programmable gates are symmetrically formed on two sides of the control gate and are symmetrical along the adjacent position of the gate oxide layer and the isolation layer.
Optionally, the silicide layer sequentially comprises silicide and metal silicide from bottom to top, and the work function of the metal silicide is located in the center of the silicon forbidden band; the control gate, the programmable gate, the source electrode and the drain electrode are made of the same material and are made of metal with work function positioned in the center of a silicon forbidden band.
Optionally, the ESD protection structure is an N-type device, and when ESD protection is performed, the source is grounded as a cathode, and the drain, the control gate, and the programmable gate are connected to each other and used as an anode to receive a positive ESD pulse.
Optionally, the ESD protection structure is a P-type device, and when performing ESD protection, the drain is connected to a negative ESD pulse as a cathode, and the source, the control gate, and the programmable gate are connected to each other and connected to a power supply voltage as an anode.
Optionally, when the ESD protection structure is an N-type device, the top layer silicon has P-type doping; and when the ESD protection structure is a P-type device, the top layer silicon is doped with N type.
The invention also provides a preparation method of the ESD protection structure, which comprises the following steps:
providing a fully depleted silicon-on-insulator, sequentially comprising a silicon substrate, a buried oxide layer and top silicon from bottom to top, and carrying out ion doping on the top silicon;
etching the top layer silicon to expose part of the buried oxide layer, and forming silicide layers on the upper surface of the exposed buried oxide layer, wherein the silicide layers are positioned on two sides of the reserved top layer silicon;
forming a gate oxide layer on the upper surface of the reserved top layer silicon;
forming an isolation layer on part of the upper surface of the silicide layer, wherein the isolation layer is positioned at two sides of the gate oxide layer;
forming a control gate on the upper surface of part of the gate oxide layer;
forming programmable gates on part of the gate oxide layer and the upper surface of the part of the isolation layer adjacent to the gate oxide layer, wherein the programmable gates are positioned on two sides of the control gate and have a distance with the control gate;
forming a source electrode on the upper surface of the silicide layer on one side of the top silicon layer, wherein the source electrode is positioned on one side, away from the programmable gate, of the isolation layer;
and forming a drain on the upper surface of the silicide layer on the other side of the top silicon, wherein the drain is positioned on one side of the isolation layer away from the programmable gate.
Optionally, the control gate is formed in a central position of the gate oxide layer; the two programmable gates are symmetrically formed on two sides of the control gate and are symmetrical along the adjacent position of the gate oxide layer and the isolation layer.
Optionally, the silicide layer sequentially comprises silicide and metal silicide from bottom to top, and the work function of the metal silicide is located in the center of the silicon forbidden band; the control gate, the programmable gate, the source electrode and the drain electrode are made of the same material and are made of metal with work function positioned in the center of a silicon forbidden band.
Optionally, when the ESD protection structure is an N-type device, the top layer silicon has P-type doping; and when the ESD protection structure is a P-type device, the top layer silicon is doped with N type.
As described above, according to the ESD protection structure and the manufacturing method thereof of the present invention, when an ESD pulse enters, an inversion channel is formed in the top silicon by changing the barrier heights of the silicide layer and the top silicon, so as to form a leakage channel, and realize ultra-low leakage while discharging the ESD pulse; moreover, the process of the invention is compatible with the CMOS process, and can be realized by only increasing the modulation of the work functions of the silicide layer and the grid, the source and the drain.
Drawings
Fig. 1 is a schematic structural diagram of a fully depleted soi according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram illustrating the formation of a silicide layer according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram illustrating the formation of a gate oxide layer and an isolation layer in accordance with a first embodiment of the present invention.
Fig. 4 is a schematic structural diagram illustrating the formation of a control gate, a programmable gate, a source and a drain in accordance with an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating connection of electrodes during ESD protection according to the structure of the first embodiment of the present invention.
Fig. 6 is an equivalent schematic diagram of the structure according to the first embodiment of the present invention during ESD protection.
Fig. 7 is a schematic diagram illustrating connection of electrodes during ESD protection according to the second embodiment of the present invention.
Fig. 8 is an equivalent schematic diagram of the structure according to the second embodiment of the present invention during ESD protection.
Element number description: 100 fully depleted silicon on insulator, 101 silicon substrate, 102 buried oxide layer, 103 top silicon, 200 silicide layer, 300 gate oxide layer, 400 isolation layer, 500 control gate, 600 programmable gate, 700 source, 800 drain.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 4, the present embodiment provides an N-type ESD protection structure, which includes: fully depleted silicon-on-insulator 100, silicide layer 200, gate oxide layer 300, isolation layer 400, control gate 500, programmable gate 600, source 700, and drain 800.
The fully depleted silicon-on-insulator 100 sequentially comprises a silicon substrate 101, a buried oxide layer 102 and a top silicon layer 103 from bottom to top, that is, the buried oxide layer 102 is formed on the upper surface of the silicon substrate 101, and the top silicon layer 103 is formed on the upper surface of the buried oxide layer 102; wherein the top layer silicon 103 has a P-type doping. In this embodiment, the thickness of the buried oxide layer 102 is 25nm, the thickness of the top silicon layer 103 is 10nm, and the P-type ion doping concentration is 10-15 cm-3。
The silicide layer 200 is formed on the upper surface of the buried oxide layer 102 and on both sides of the top silicon 103.
Specifically, the silicide layer 200 sequentially includes a silicide and a metal silicide (not shown in the figure) from bottom to top, that is, the silicide is formed on the upper surface of the buried oxide layer 102, and the metal silicide is formed on the upper surface of the silicide; wherein the thickness of the silicide is greater than that of the metal silicide, and the sum of the thickness of the silicide and the thickness of the metal silicide is equal to that of the top silicon 103. More specifically, the work function of the metal silicide is located at the center of the silicon forbidden band (4.61 eV).
The gate oxide layer 300 is formed on the top surface of the top silicon 103.
Specifically, the gate oxide layer 300 is a silicon oxide layer or a hafnium oxide layer. In this embodiment, the gate oxide layer 300 is a hafnium oxide layer with a thickness of 1.4 nm.
The isolation layer 400 is formed on a portion of the upper surface of the silicide layer 200 and on both sides of the gate oxide layer 300.
Specifically, the isolation layer 400 may be a silicon oxide layer having a uniform thickness, or may be a silicon oxide layer having different thicknesses; if it is a silicon oxide layer having a uniform thickness, the thickness thereof is the same as that of the gate oxide layer 300; if the gate oxide layer is a silicon oxide layer with different thicknesses, the thickness of the portion adjacent to the gate oxide layer 300 is the same as that of the gate oxide layer 300, and the thickness of the portion away from the gate oxide layer 300 is the same as that of the source electrode and the drain electrode which are formed later. In this embodiment, in order to better realize the isolation function, the isolation layer 400 is implemented by using silicon oxide layers with different thicknesses. It should be noted that, when the isolation layer 400 is implemented by using silicon oxide layers with different thicknesses, the width of the portion adjacent to the gate oxide layer 300 is designed according to the width of the programmable gate 600 formed thereon, and the portion is far from the gate oxide layer 300 except for the width.
The control gate 500 is formed on the upper surface of a portion of the gate oxide layer 300; the programmable gate 600 is formed on a portion of the gate oxide layer 300 and a portion of the isolation layer 400 adjacent thereto, and is formed on both sides of the control gate 500, wherein a space is formed between the programmable gate 600 and the control gate 500.
Specifically, the control gate 500 is formed in the center of the gate oxide layer 300, and the two programmable gates 600 are symmetrically formed on two sides of the control gate 500 and are symmetrically formed along the adjacent position of the gate oxide layer 300 and the isolation layer 400, so that one half of the programmable gates 600 are formed on the upper surface of the gate oxide layer 300, and the other half of the programmable gates 600 are formed on the upper surface of the isolation layer 400.
The source 700 is formed on the upper surface of the silicide layer 200 on one side of the top silicon 103 and on one side of the isolation layer 400 away from the programmable gate 600; the drain 800 is formed on the upper surface of the silicide layer 200 on the other side of the top silicon 103, and is formed on the side of the isolation layer 400 away from the programmable gate 600.
Specifically, the control gate 500, the programmable gate 600, the source 700, and the drain 800 are made of the same material and are made of metal having a work function located in the center of the silicon forbidden band (4.61 eV).
Specifically, the thickness of the control gate 500 is the same as that of the programmable gate 600, the thickness of the source 700 is the same as that of the drain 800, and the thickness of the source 700 is equal to the sum of the thickness of the control gate 500 and the thickness of the gate oxide layer 300.
As shown in fig. 1 to 4, this embodiment further provides a method for manufacturing an ESD protection structure, where the method includes the following steps:
s1 provides a fully depleted soi 100, which comprises a silicon substrate 101, a buried oxide layer 102 and a top silicon 103 from bottom to top, and P-type ion doping is performed on the top silicon 103 (as shown in fig. 1).
Specifically, the top silicon 103 is doped with P-type ions by an ion implantation process. In this embodiment, the thickness of the buried oxide layer 102 is 25nm, the thickness of the top silicon layer 103 is 10nm, and the P-type ion doping concentration is 10-15 cm-3。
S2, etching the top silicon 103 to expose a portion of the buried oxide layer 102, and forming a silicide layer 200 on the exposed top surface of the buried oxide layer 102, wherein the silicide layer 200 is located on both sides of the remaining top silicon 103 (as shown in fig. 2).
Specifically, the steps of forming the silicide layer 200 are as follows: s21 forming a photoresist layer on the top surface of the top silicon 103, and exposing and developing the photoresist layer based on a photomask to remove the photoresist layer in the region of the silicide layer 200; s22, etching the exposed top silicon 103 until the buried oxide layer 102 is exposed; s23 forming a silicide on the exposed top surface of the buried oxide layer, and performing a metal silicidation process on the top surface of the silicide to form a metal silicide, thereby completing the preparation of the silicide layer.
Specifically, the silicide layer 200 sequentially includes silicide and metal silicide from bottom to top; wherein the thickness of the silicide is greater than that of the metal silicide, and the sum of the thickness of the silicide and the thickness of the metal silicide is equal to that of the top silicon 103. More specifically, the work function of the metal silicide is located at the center of the silicon forbidden band (4.61 eV).
S3 forms a gate oxide layer 300 on the top surface of the top silicon 103.
Specifically, the gate oxide layer 300 is formed by a high-k process, wherein the gate oxide layer 300 is a silicon oxide layer or a hafnium oxide layer. In this embodiment, the gate oxide layer 300 is a hafnium oxide layer with a thickness of 1.4 nm.
S4, forming an isolation layer 400 on a portion of the upper surface of the silicide layer 200, wherein the isolation layer 400 is located on both sides of the gate oxide layer 300.
Specifically, the isolation layer 400 may be a silicon oxide layer having a uniform thickness, or may be a silicon oxide layer having different thicknesses; if it is a silicon oxide layer having a uniform thickness, the thickness thereof is the same as that of the gate oxide layer 300; if the gate oxide layer is a silicon oxide layer with different thicknesses, the thickness of the portion adjacent to the gate oxide layer 300 is the same as that of the gate oxide layer 300, and the thickness of the portion away from the gate oxide layer 300 is the same as that of the source electrode and the drain electrode which are formed later. In this embodiment, in order to better realize the isolation function, the isolation layer 400 is implemented by using silicon oxide layers with different thicknesses. It should be noted that, when the isolation layer 400 is implemented by using silicon oxide layers with different thicknesses, the width of the portion adjacent to the gate oxide layer 300 is designed according to the width of the programmable gate 600 formed thereon, and the portion is far from the gate oxide layer 300 except for the width.
S5 forming the control gate 500, the programmable gate 600, the source 700 and the drain 800.
Specifically, the control gate 500, the programmable gate 600, the source 700 and the drain 800 are formed by deposition and etching processes; wherein the control gate 500 is formed on the upper surface of a portion of the gate oxide layer 300; forming the programmable gate 600 on a portion of the gate oxide layer 300 and a portion of the isolation layer 400 adjacent thereto, wherein the programmable gate 600 is located on two sides of the control gate 500 and has a distance from the control gate 500; forming the source 700 on the upper surface of the silicide layer 200 on the side of the top silicon 103, wherein the source 700 is located on the side of the isolation layer 400 away from the programmable gate 600; the drain 800 is formed on the upper surface of the silicide layer 200 on the other side of the top silicon 103, wherein the drain 800 is located on one side of the isolation layer 400 away from the programmable gate 600.
Specifically, the control gate 500 is formed in the center of the gate oxide layer 300, and the two programmable gates 600 are symmetrically formed on two sides of the control gate 500 and are symmetrically formed along the adjacent position of the gate oxide layer 300 and the isolation layer 400, so that one half of the programmable gates 600 are formed on the upper surface of the gate oxide layer 300, and the other half of the programmable gates 600 are formed on the upper surface of the isolation layer 400.
Specifically, the control gate 500, the programmable gate 600, the source 700, and the drain 800 are made of the same material and are made of metal having a work function located in the center of the silicon forbidden band (4.61 eV).
Specifically, the thickness of the control gate 500 is the same as that of the programmable gate 600, the thickness of the source 700 is the same as that of the drain 800, and the thickness of the source 700 is equal to the sum of the thickness of the control gate 500 and the thickness of the gate oxide layer 300.
In the N-type ESD protection structure of this embodiment, during ESD protection, the source 700 serves as a cathode and is grounded, and the drain 800, the control gate 500 and the programmable gate 600 are connected to each other and serve as an anode to receive a positive ESD pulse (as shown in fig. 5 and fig. 6). Under the action of the forward ESD pulse, the control gate 500 and the programmable gate 600 change the barrier height of the silicide layer 200 and the top silicon 103, and at the same time, the control gate 500 controls the formation of an inversion channel in the top silicon 103, so as to form a leakage channel, and finally, the forward ESD pulse is discharged to the ground, and meanwhile, ultra-low leakage is realized.
Example two
This embodiment provides a P-type ESD protection structure, which is different from the first embodiment in that the top silicon 103 has N-type doping. Correspondingly, the embodiment further provides a method for manufacturing a P-type ESD protection structure, which is different from the first embodiment in that N-type ions are doped into the top silicon 103.
In the P-type ESD protection structure of this embodiment, when performing ESD protection, the drain 800 is connected to a negative ESD pulse as a cathode, and the source 700, the control gate 500 and the programmable gate 600 are connected to each other and connected to a power supply voltage as an anode (as shown in fig. 7 and 8). Under the action of the negative ESD pulse, the control gate 500 and the programmable gate 600 change the barrier heights of the silicide layer 200 and the top silicon 103, and at the same time, the control gate 500 controls the formation of an inversion channel in the top silicon 103, so that a leakage channel is formed, and finally the negative ESD pulse is discharged to a power supply, and meanwhile, ultra-low leakage is realized.
In practical applications, only the N-type ESD protection structure described in the first embodiment may be used for ESD protection, only the P-type ESD protection structure described in the second embodiment may be used for ESD protection, and further, the N-type ESD protection structure described in the first embodiment and the P-type ESD protection structure described in the second embodiment may be used for ESD protection at the same time. Moreover, the length and width of the ESD protection structure may be changed by layout design for better current drainage.
In summary, according to the ESD protection structure and the manufacturing method thereof of the present invention, when an ESD pulse enters, an inversion channel is formed in the top silicon by changing the barrier heights of the silicide layer and the top silicon, so as to form a leakage channel, and realize ultra-low leakage while discharging the ESD pulse; moreover, the process of the invention is compatible with the CMOS process, and can be realized by only increasing the modulation of the work functions of the silicide layer and the grid, the source and the drain. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. An ESD protection structure, comprising:
the fully depleted silicon-on-insulator comprises a silicon substrate, a buried oxide layer and top silicon in sequence from bottom to top;
the silicide layer is formed on the upper surface of the buried oxide layer and formed on two sides of the top silicon layer;
the gate oxide layer is formed on the upper surface of the top layer silicon;
the isolation layer is formed on the upper surface of part of the silicide layer and formed on two sides of the gate oxide layer;
the control gate is formed on the upper surface of part of the gate oxide layer;
the programmable gate is formed on the upper surfaces of part of the gate oxide layer and part of the isolation layer adjacent to the gate oxide layer, and is formed on two sides of the control gate, wherein a space is reserved between the programmable gate and the control gate;
the source electrode is formed on the upper surface of the silicide layer on one side of the top silicon layer and is formed on one side, far away from the programmable gate, of the isolation layer;
and the drain electrode is formed on the upper surface of the silicide layer on the other side of the top layer silicon and is formed on one side, far away from the programmable gate, of the isolation layer.
2. The ESD protection structure of claim 1, wherein the control gate is formed in a central position of the gate oxide layer; the two programmable gates are symmetrically formed on two sides of the control gate and are symmetrical along the adjacent position of the gate oxide layer and the isolation layer.
3. The ESD protection structure of claim 1, wherein the silicide layer sequentially comprises a silicide and a metal silicide from bottom to top, and a work function of the metal silicide is located at a center of a silicon forbidden band; the control gate, the programmable gate, the source electrode and the drain electrode are made of the same material and are made of metal with work function positioned in the center of a silicon forbidden band.
4. The ESD protection structure of claim 1, wherein the ESD protection structure is an N-type device, and wherein the source is grounded as a cathode and the drain, the control gate, and the programmable gate are connected to each other and to a positive ESD pulse as an anode during ESD protection.
5. The ESD protection structure of claim 1, wherein the ESD protection structure is a P-type device, and wherein the drain is configured to be a cathode for receiving a negative ESD pulse during ESD protection, and wherein the source, the control gate, and the programmable gate are connected to each other and to be an anode for receiving a supply voltage.
6. The ESD protection structure of claim 1, wherein the top layer silicon has a P-type doping when the ESD protection structure is an N-type device; and when the ESD protection structure is a P-type device, the top layer silicon is doped with N type.
7. A preparation method of an ESD protection structure is characterized by comprising the following steps:
providing a fully depleted silicon-on-insulator, sequentially comprising a silicon substrate, a buried oxide layer and top silicon from bottom to top, and carrying out ion doping on the top silicon;
etching the top layer silicon to expose part of the buried oxide layer, and forming silicide layers on the upper surface of the exposed buried oxide layer, wherein the silicide layers are positioned on two sides of the reserved top layer silicon;
forming a gate oxide layer on the upper surface of the reserved top layer silicon;
forming an isolation layer on part of the upper surface of the silicide layer, wherein the isolation layer is positioned at two sides of the gate oxide layer;
forming a control gate on the upper surface of part of the gate oxide layer;
forming programmable gates on part of the gate oxide layer and the upper surface of the part of the isolation layer adjacent to the gate oxide layer, wherein the programmable gates are positioned on two sides of the control gate and have a distance with the control gate;
forming a source electrode on the upper surface of the silicide layer on one side of the top silicon layer, wherein the source electrode is positioned on one side, away from the programmable gate, of the isolation layer;
and forming a drain on the upper surface of the silicide layer on the other side of the top silicon, wherein the drain is positioned on one side of the isolation layer away from the programmable gate.
8. The method for manufacturing an ESD protection structure according to claim 7, wherein the control gate is formed in a central position of the gate oxide layer; the two programmable gates are symmetrically formed on two sides of the control gate and are symmetrical along the adjacent position of the gate oxide layer and the isolation layer.
9. The method according to claim 7, wherein the silicide layer comprises a silicide and a metal silicide in sequence from bottom to top, and the work function of the metal silicide is located in the center of the silicon forbidden band; the control gate, the programmable gate, the source electrode and the drain electrode are made of the same material and are made of metal with work function positioned in the center of a silicon forbidden band.
10. The method of claim 7, wherein the top silicon has a P-type doping when the ESD protection structure is an N-type device; and when the ESD protection structure is a P-type device, the top layer silicon is doped with N type.
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