CN114420554B - Acid etching method for controlling morphology of silicon wafer - Google Patents

Acid etching method for controlling morphology of silicon wafer Download PDF

Info

Publication number
CN114420554B
CN114420554B CN202111677464.2A CN202111677464A CN114420554B CN 114420554 B CN114420554 B CN 114420554B CN 202111677464 A CN202111677464 A CN 202111677464A CN 114420554 B CN114420554 B CN 114420554B
Authority
CN
China
Prior art keywords
etching
silicon wafer
inert gas
cleaning
etching solution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111677464.2A
Other languages
Chinese (zh)
Other versions
CN114420554A (en
Inventor
吴泓明
钟佑生
黄郁璿
李少华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhengzhou Hejing Silicon Materials Co ltd
Original Assignee
Zhengzhou Hejing Silicon Materials Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhengzhou Hejing Silicon Materials Co ltd filed Critical Zhengzhou Hejing Silicon Materials Co ltd
Priority to CN202111677464.2A priority Critical patent/CN114420554B/en
Publication of CN114420554A publication Critical patent/CN114420554A/en
Application granted granted Critical
Publication of CN114420554B publication Critical patent/CN114420554B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67248Temperature monitoring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67253Process monitoring, e.g. flow or thickness monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

The invention discloses an acid etching method for controlling the appearance of a silicon wafer,the method comprises the following steps: placing the silicon wafer with the exposed surface after cleaning in an etching tank, and etching by adopting an etching solution overflow circulation method, wherein the overflow circulation flow of the etching solution is 140-195L/min; the etching solution is prepared from HF and HNO 3 The composition is that inert gas bubbles are uniformly distributed in the etching solution, and a silicon wafer with a specific geometric shape can be obtained by adjusting the parameters of the inert gas bubbles. The invention firstly controls the whole etching rate of the surface of the silicon wafer by adjusting the composition, flow and temperature of the etching solution, and then adjusts the etching rate of the edge and the center of the silicon wafer by adding inert gas bubbles into the etching solution, thereby effectively controlling the etching rate of the silicon wafer, obtaining the silicon wafer with ideal specific geometric morphology, and providing flatness and geometric shape which are beneficial to quality output for the subsequent polishing process.

Description

Acid etching method for controlling morphology of silicon wafer
Technical Field
The invention relates to the technical field of semiconductor silicon wafer manufacturing, in particular to an acid etching method for controlling the appearance of a silicon wafer.
Background
The current manufacturing process of silicon wafers is basically as follows: the method comprises the following steps of primary processing (cutting and barreling), slicing, grinding, chamfering, etching, back processing, polishing, cleaning and the like of the single crystal silicon rod. The chemical etching process of the silicon wafer is generally divided into an alkali etching process and an acid etching process, wherein the alkali etching process is an anisotropic etching process, the etching rate is relatively slow, the surface roughness of the silicon wafer is relatively large, the acid etching process is an isotropic etching process, the etching rate is high, particularly, the center etching rate of the silicon wafer is higher, the surface roughness is small, but the shape of the silicon wafer is not suitable to be controlled. Etching is an important process, the etching process can remove a damaged layer on the surface of the silicon wafer caused by the previous process, improve the surface glossiness and cleanliness of the silicon wafer, and the silicon wafers with different shapes can be obtained by adjusting the etching process parameters.
The existing common polishing method of the silicon wafer is Chemical Mechanical Polishing (CMP), and in the polishing process, due to the rotation of the polishing head, the removal rate of the edge of the silicon wafer is obviously higher than that of the center of the silicon wafer under the action of centrifugal force of polishing liquid. In order to balance the thickness difference between the edge and the center of a silicon wafer during polishing, etching wafers with different shapes are often needed. Etching is a last key process for changing the topography of the silicon wafer before polishing, and the etched topography of the silicon wafer has TTV (total thickness variation of the silicon wafer: difference between maximum thickness and minimum thickness among a plurality of thickness measurement values), TIR (total indication reading: a surface where the sum of the intercepts of all points in an acceptable quality area or a prescribed local area of the surface of the silicon wafer is smallest in a case where the silicon wafer is clamped tightly, as a reference plane, a deviation value of the maximum distance and the minimum distance of the surface of the wafer from the reference plane is measured), STIR (local total indication reading), roloff (edge Roll-Off Amount: roaa) which is an Amount of edge Roll Off of the wafer surface at a boundary position between an edge-removed area outside an applicable range of flatness specification and an area further inside than the reference area, specifically, an edge Roll Off Amount is defined as an Amount of Roll Off of the wafer surface from the outermost 3 mm to 6mm of the periphery of the wafer surface as a reference plane where Roll Off is a parameter of importance, such as Roll Off, and a Roll Off parameter which is a maximum value of the wafer surface displacement from the outermost edge Roll Off of the reference plane. How to control the etching process and provide flatness and geometry beneficial to quality output for the subsequent polishing process to meet the increasingly demanding requirements of integrated circuit manufacturing on the flatness performance of silicon wafers is a problem to be solved.
Disclosure of Invention
In view of the problem that the shape of the silicon wafer is not easy to control in the current acid etching process, the invention explores the method for etching the silicon wafer by acid, which can stably control the shape change of the silicon wafer through a plurality of process condition tests.
The technical scheme adopted by the invention is as follows:
an acid etching method for controlling the appearance of a silicon wafer comprises the following steps:
placing the silicon wafer with the surface exposed after cleaning in an etching tank, and etching at the temperature of 20-46 ℃ by adopting an etching solution overflow circulation method, wherein the etching time is 135-185 s, and the etching solution overflow circulation flow is 140-195L/min; the etching solution consists of HF and HNO 3 Composition of, among them, HF and HNO 3 The volume ratio of (25-35): (65-75), inert gas bubbles are uniformly distributed in the etching solution, and a silicon wafer with a specific geometric shape can be obtained by adjusting parameters of the inert gas bubbles.
Preferably, the silicon wafer adopts HF/O 3 Cleaning to expose the surface; the HF/O 3 Cleaning is carried out by adopting cleaning solution circulation, wherein the volume percentage concentration of HF acid in the cleaning solution is 3-10%, the ozone content is 1-2.6 ppm, the circulation flow is 20-26L/min, and the temperature is 55-60 ℃.
Preferably, in said HF/O 3 Before the cleaning treatment, the method also comprises a step of pre-cleaning the silicon wafer to be etched, and is used for removing impurities on the surface of the silicon wafer; the pre-cleaning is added with a cleaning agent, the cleaning temperature is 60-70 ℃, and the pre-cleaning is carried out under the ultrasonic condition.
Preferably, the inert gas bubbles are on the nanometer scale.
Preferably, the inert gas bubble parameters include a bubble number, an inert gas concentration, or an inert gas flow rate.
Preferably, the step of obtaining a silicon wafer with a specific geometry by adjusting the parameters of the inert gas bubbles further comprises:
obtaining a silicon wafer with a low Rolloff value after etching by increasing the number of bubbles, the concentration of inert gas or the flow rate of inert gas;
by reducing the number of bubbles, the concentration of the inert gas, or the flow rate of the inert gas, a silicon wafer having a high Rolloff value is obtained after etching.
Preferably, the inert gas bubbles in the etching solution are formed by continuously filling inert gas into the etching solution outside the etching tank; the inert gas charging flow is calculated according to the formula I:
Figure BDA0003452531360000041
wherein Rolloff is the Rolloff value to be obtained after etching the silicon wafer to be etched;
▲TTV=TTV 2 -TTV 1 ,TTV 2 is TTV value before etching of a silicon wafer to be etched 1 Is 1.5;
k is a constant coefficient, and is adjusted according to the overflow circulation flow rate of the etching solution, the circulation temperature and the composition of the etching solution;
N 2 the inert gas is filled with flow rate in L/min.
Preferably, when the circulation flow rate of the etching solution is 170L/min, the circulation temperature is 21 ℃, and the composition of the etching solution is HF and HNO 3 At a volume ratio of 25.
Preferably, the etching further comprises the use of HF/O 3 And (5) cleaning again.
Preferably, the HF/O 3 The cleaning process also comprises a step of cleaning by adopting ozone gas.
The invention firstly controls the integral etching rate of the surface of the silicon wafer by adjusting the composition, the flow and the temperature of the etching solution, and then adjusts the etching rate of the edge and the center of the silicon wafer by adding the inert gas bubbles into the etching solution, thereby effectively controlling the etching rate of the silicon wafer, obtaining the silicon wafer with ideal specific geometric morphology, and providing flatness and geometric shape which are beneficial to quality output for the subsequent polishing process.
Drawings
FIG. 1 is a graph of the geometry of sample 1 after etching;
FIG. 2 is a graph of the geometry of sample 2 after etching;
fig. 3 is a graph of the geometry of sample 3 after etching.
FIG. 4 is a graph of the geometry of the post-etch product obtained for the comparative example.
FIG. 5 is a graph of the geometry of the post-etch product obtained in example 2.
FIG. 6 is a graph of the geometry of the post-etch product obtained in example 3.
FIG. 7 is a graph of the geometry of the etched product obtained in example 4.
Detailed Description
In order to better understand the technical solutions, the technical solutions will be described in detail with reference to specific embodiments.
An acid etching method for controlling the morphology of a silicon wafer comprises the following steps:
placing the silicon wafer with the exposed surface after cleaning in an etching tank, and etching at the temperature of 20-46 ℃ by adopting an etching solution overflow circulation method, wherein the etching time is 135-185 s, and the overflow circulation flow of the etching solution is 140-195L/min; the etching solution is prepared from HF and HNO 3 Composition of, among others, HF and HNO 3 The volume ratio of (25-35): (65-75) the method is applicable to any monocrystalline silicon wafer; inert gas bubbles are uniformly distributed in the etching solution, and the silicon wafer with a specific geometric shape can be obtained by adjusting the parameters of the inert gas bubbles. Through the overflow circulation of the etching solution, the etching solution can be fully contacted with the surface of the silicon wafer to generate etching, and in the etching process, the following chemical reactions can occur between the silicon wafer and the etching solution: si +4HNO 3 +6HF=H 2 SiF 6 +4NO 2 ↑+6H 2 O, the chemical reaction is exothermic. The generated reaction heat can be rapidly taken away through the overflow circulation of the etching solution, so that the stability of the reaction temperature is maintained, and the stability of the concentration of the etching solution is realized.
The whole etching rate of the surface of the silicon wafer can be influenced by the circulating flow and the temperature of the etching liquid, the composition of the etching liquid also has important influence on the whole etching rate, and HF and HNO in a certain proportion are adopted in the method 3 In which HNO 3 Oxidizing the silicon surface to silicon dioxide, dissolving and removing the formed silicon dioxide by HF, and adjusting HF and HNO 3 The etching rate can be adjusted. The etching time can be adjusted to the total etching amount, and the total etching amount of the silicon wafer is increased along with the increase of the etching time.
In order to balance the etching rate of each part of the surface of the silicon wafer and obtain the specific geometrical morphology of the silicon wafer, inert gas bubbles are distributed in the etching solution, in the process of contacting the etching solution and the silicon wafer, the inert gas bubbles are easily enriched on the surface of the silicon wafer, the enrichment amount is more when the inert gas bubbles are closer to the center of the silicon wafer, the enrichment of the bubbles prevents the etching solution from contacting the silicon wafer, the center etching rate is reduced, and the number of the bubbles enriched on the surface of the silicon wafer is changed along with the enrichment of the bubbles in the etching solution by adjusting the number and the density degree of the bubbles in the etching solution, so that the etching rate of the center and the edge of the silicon wafer can be adjusted, and the specific geometrical morphology of the silicon wafer is obtained. The concentration and the flow rate of the inert gas are directly related to the quantity and the density of the inert gas, so that the specific geometrical morphology of the silicon wafer can be obtained by adjusting the concentration and the flow rate of the inert gas and also adjusting the etching rate of the center and the edge of the silicon wafer.
Therefore, the invention firstly controls the whole etching rate of the surface of the silicon wafer by adjusting the composition, the flow and the temperature of the etching solution, and then adjusts the etching rate of the edge and the center of the silicon wafer by adding the inert gas bubbles into the etching solution, thereby effectively controlling the etching rate of the silicon wafer, obtaining the silicon wafer with ideal specific geometric morphology, and providing flatness and geometric shape which are beneficial to quality output for the subsequent polishing process.
Preferably, HF/O is used in the present application 3 And cleaning to enable some metal impurities on the surface of the silicon wafer to fall off, and further exposing the surface of the silicon wafer for subsequent acid corrosion. Specifically, ozone can oxidize and decompose organic matters on the surface of the silicon wafer, and HF acid can perform acidolysis, differentiation and stripping of the organic matters to expose the silicon wafer; at the same time, via HF/O 3 And cleaning, namely forming hydrophobic property on the surface of the silicon wafer by hydrophilic property, so that the surface of the silicon wafer is not easily attached by moisture after the hydrophobic property is formed, and reducing the technical problem of etching pollution on the surface of the silicon wafer caused by concentration difference due to dilution of an etching solution after the silicon wafer enters an etching tank.
HF/O 3 The cleaning is preferably carried out by the following method: cleaning is carried out by adopting cleaning solution in a circulating way, the volume percentage concentration of HF acid in the cleaning solution is 3-10%, and the ozone content is1-2.6 ppm, circulation flow rate of 20-26L/min, and temperature of 55-60 ℃.
Preferably, in HF/O 3 Before the cleaning treatment, the method also comprises a step of pre-cleaning the silicon wafer to be etched, and is used for removing various impurities adhered to the surface of the silicon wafer. Specifically, the pre-cleaning is carried out by adopting 15DI ultrapure water and adding a conventional silicon wafer cleaning agent, the cleaning temperature is 60-70 ℃, and the cleaning is carried out under the ultrasonic condition, and the ultrasonic frequency is preferably 20-35 Hz.
Preferably, the inert gas is nitrogen, argon or helium, more preferably inexpensive nitrogen.
Preferably, the inert gas bubbles are nano-sized, the particle size is about 10-1000 nm, and compared with common bubbles, the nano-bubbles have the advantages of large dissolving capacity, stability and the like, can be in better uniform contact with the surface of a silicon wafer, and can adjust the etching rate. The excessive bubble grain size will seriously hinder the contact between the etching solution and the silicon wafer, and affect the normal etching.
Preferably, the inert gas bubble parameters include the number of bubbles, inert gas concentration, or inert gas flow rate. Obtaining a silicon wafer with a low Rolloff value after etching by increasing the number of bubbles, the concentration of inert gas or the flow rate of the inert gas; by reducing the number of bubbles, the concentration of the inert gas, or the flow rate of the inert gas, a silicon wafer having a high Rolloff value is obtained after etching.
Preferably, the inert gas bubbles in the etching solution are formed by continuously filling inert gas into the etching solution outside the etching tank; outside the etching tank, such as in an etching solution circulating pipeline, inert gas can be filled into the etching solution through a nano bubble generating device to form nano bubble etching solution, and then the nano bubble etching solution is introduced into the etching tank to prevent nano bubbles from being generated in the etching tank and influencing normal etching. The quantity of the inert gas filled into the etching liquid can directly influence the quantity and the degree of the nano bubbles in the etching liquid, and further adjust the etching rate of the silicon wafer.
Figure BDA0003452531360000081
Wherein Rolloff is the Rolloff value to be obtained after etching the silicon wafer to be etched;
▲TTV=TTV 2 -TTV 1 ,TTV 2 is TTV value before etching of a silicon wafer to be etched 1 Is 1.5;
k is a constant coefficient, and K is adjusted according to the overflow circulation flow rate of the etching solution, the circulation temperature and the composition of the etching solution;
N 2 the inert gas is filled with flow rate in L/min.
Both the Rolloff value and the TTV value are indexes reflecting the flatness of a silicon wafer, and particularly, the Rolloff value is an index of primary interest to customers.
Through further research, when the circulating flow rate of the etching solution is 170L/min, the circulating temperature is 21 ℃, and the composition of the etching solution is HF and HNO 3 And the K value is 50 when the volume ratio is 25.
Preferably, the etching further comprises using HF/O 3 The step of cleaning again, because the etching solution is a non-electronic grade chemical reagent and contains more impurities and metal ions, HF/O is adopted again after acid etching 3 And cleaning to remove surface impurities and metal ions.
Preferably, HF/O 3 Before cleaning again, firstly, circulating water is adopted to wash and remove residual etching solution on the surface, so as to prevent the etching solution from continuously corroding and influencing subsequent cleaning.
Preferably, HF/O 3 After cleaning, the method also comprises a step of cleaning by adopting ozone gas, can oxidize silicon atoms into silicon dioxide with stable property, and has better dust resistance.
The present application is further explained with reference to specific embodiments, and before describing the specific embodiments, it needs to be explained that:
a silicon wafer measurement tool and method: 1. and detecting the glossiness change condition of the back of the silicon wafer by using a 60-degree glossiness meter so as to judge the roughness of the silicon wafer. 2. And detecting the surface geometry of the front surface of the silicon wafer by using an ADE970 flatness measuring instrument so as to judge the flatness index of the silicon wafer.
Silicon wafer test type: 8 inch grinding silicon wafer, doping element boron, crystal orientation (100) and resistivity of the silicon wafer is 15-25 omega cm. The following are specifically mentioned: the invention does not limit the doping elements and resistivity of the silicon wafer.
The following description is given by way of example only, and the method for acid etching silicon wafers according to the present invention is mainly applied to an acid etching bath, and the specific process of this embodiment is as follows: 1. prewash tank (volume 80L), 2, water wash tank (80L), 3, HF/O 3 Tanks (80L), 4, acid etching tanks (120L), 5, rinsing tanks (80L), 6, HF/O 3 Tank (80L), 7 ozone tank (80L).
Example 1
S1, taking 10 grinded silicon wafers, and sequentially pre-cleaning the silicon wafers in a pre-cleaning tank, wherein a special cleaning agent for the silicon wafers is added into the cleaning agent, the cleaning temperature is 65 ℃, and the cleaning is carried out under an ultrasonic condition for 200s;
s2, taking out the silicon wafer from the pre-cleaning tank, and removing the residual cleaning agent on the surface through a rinsing tank;
s3, placing the washed silicon wafer in HF/O 3 Cleaning the inside of the tank; the volume percentage concentration of HF acid in the cleaning solution is 7%, the ozone content is 1.8ppm, the circulation flow is 23L/min, the temperature is 58 ℃, and the cleaning time is 230s;
s4, continuously filling nitrogen into an etching solution circulating pipeline outside the etching tank to obtain the etching solution with uniformly distributed nano bubbles, wherein the average particle size of the nano bubbles is less than 1000nm; taken out via HF/O 3 Carrying the silicon wafer by a mechanical arm, placing the silicon wafer into an acid etching tank, and carrying out surface chemical etching on the silicon wafer by adopting an etching liquid overflow circulation method at the temperature of 21 ℃; HNO as HF in the etching solution 3 75 (volume ratio), 170L/min of etching solution overflow circulation and 165s of acid etching time in total;
s5, after etching, carrying the bearing frame by a continuous armThe silicon wafer was passed through a rinsing bath (time 200 s) in sequence, HF/O 3 A tank (time 230 s) and an ozone tank (time 200s, ozone concentration, 15 ppm), thereby completing the whole etching process; and drying to obtain the finished product of the etched silicon wafer.
According to the method, three groups of silicon wafers in different batches are taken for etching, different nitrogen flows are filled for etching, after the etching is finished, 3 wafers in each group are taken, the surface geometry of the front surface of the silicon wafer is detected by using an ADE9700 flatness measuring instrument, and the Rolloff value obtained by calculation according to the formula I is compared with the Rolloff value, and the results are shown in the table 1 and the figures 1 to 3.
TABLE 1
Figure BDA0003452531360000101
As can be seen from fig. 1 to 3 and table 1, the error between the roloff value calculated according to the formula one and the actually detected roloff value is within 5%, and the accuracy is high. In actual production, the corresponding nitrogen amount can be calculated and filled according to the requirements of customers, and the silicon wafer with ideal geometric morphology can be obtained after etching.
Comparative example
The same procedure as in example 1 was repeated except that the acid etching solution was not filled with nitrogen, i.e., the acid etching solution contained no nitrogen bubbles (i.e., the circulating flow rate of the etching solution was 170L/min, the circulating temperature was 21 ℃, and the etching solution consisted of HF and HNO) 3 Volume ratio 25. This application charges to N 2 By the principle of N 2 The adhesion of bubbles on the wafer surface adjusts the etching rate at the edge and center of the silicon wafer, and as can be seen from table 2 and fig. 4, if no nitrogen is filled, the etching rate will be too high and uncontrollable, the concave shape of the product cannot be made, and roloff will be positive.
TABLE 2
Figure BDA0003452531360000111
Example 2
Step S4 acid etching is performed as follows, and the rest is the same as in example 1.
Continuously filling nitrogen in an etching solution circulating pipeline outside the etching tank, wherein the nitrogen flow is 30L/min, so as to obtain the etching solution uniformly distributed with nano bubbles, and the average particle size of the nano bubbles is less than 1000nm; taken out via HF/O 3 Carrying the silicon wafer by a mechanical arm, placing the silicon wafer into an acid etching tank, and carrying out surface chemical etching on the silicon wafer by adopting an etching solution overflow circulation method at the temperature of 21 ℃; HF: HNO in the etching solution 3 The volume ratio of the etching solution to the etching solution was set to 25 (75), the overflow circulation of the etching solution was set to 175L/min, and the acid etching time was 165s in total.
Conditions affecting the roloff product other than N 2 The flow rate, removal amount and temperature are also increased, and the roloff product is also increased when the circulation flow rate of the etching solution is 175L/min, the circulation temperature is 21 ℃, the composition of the etching solution is HF in the etching solution, namely HNO 3 K value was 46 and the results of examination of the etched silicon wafer were shown in table 3 and fig. 5, where =25 (volume ratio).
TABLE 3
Figure BDA0003452531360000121
Example 3
Step S4 acid etching is performed as follows, and the rest is the same as in example 1.
Continuously filling nitrogen in an etching solution circulating pipeline outside the etching tank, wherein the nitrogen flow is 30L/min to obtain the etching solution with uniformly distributed nano bubbles, and the average particle size of the nano bubbles is less than 1000nm; taken out via HF/O 3 Carrying the bearing frame by a mechanical arm to place the silicon wafer into an acid etching tank, and carrying out surface chemical etching on the silicon wafer at 21 ℃ by adopting an etching solution overflow circulation method; HNO as HF in the etching solution 3 The volume ratio of =25 (75), the etching solution overflow cycle was set at 160L/min, the total acid etching time was 165s, the K value was 58, and the results of examination of the etched silicon wafer were shown in table 4 and fig. 6.
TABLE 4
Figure BDA0003452531360000122
Example 4
Step S4 acid etching was performed as follows, and the rest was the same as in example 1.
Continuously filling nitrogen in an etching solution circulating pipeline outside the etching tank, wherein the nitrogen flow is 30L/min to obtain the etching solution with uniformly distributed nano bubbles, and the average particle size of the nano bubbles is less than 1000nm; taken out via HF/O 3 Carrying the bearing frame by a mechanical arm to place the silicon wafer into an acid etching tank, and carrying out surface chemical etching on the silicon wafer at 23 ℃ by adopting an etching solution overflow circulation method; HNO as HF in the etching solution 3 The volume ratio of =25 (75), the etching solution overflow cycle was set at 165L/min, the total acid etching time was 115s, the K value was 38, and the results of examination of the etched silicon wafers were shown in table 5 and fig. 7.
TABLE 5
Figure BDA0003452531360000131
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (7)

1. An acid etching method for controlling the appearance of a silicon wafer is characterized by comprising the following steps:
will clear awayPlacing the silicon wafer with the exposed surface after washing in an etching groove, and etching at the temperature of 20 to 46 ℃ by adopting an etching liquid overflow circulation method, wherein the etching time is 135 to 185s, and the etching liquid overflow circulation flow is 140 to 195L/min; the etching solution is prepared from HF and HNO 3 Composition of, among them, HF and HNO 3 The volume ratio of (25 to 35): (65 to 75), uniformly distributing inert gas bubbles in the etching solution, and adjusting parameters of the inert gas bubbles to obtain a silicon wafer with a specific geometric shape; the inert gas bubble parameters comprise the number of bubbles, the concentration of inert gas or the flow rate of inert gas;
the inert gas bubbles in the etching solution are formed by continuously filling inert gas into the etching solution outside an etching tank; the inert gas charging flow is calculated according to the formula I:
Figure 397595DEST_PATH_IMAGE001
wherein Rolloff is the Rolloff value to be obtained after etching the silicon wafer to be etched;
▲TTV=TTV 2 -TTV 1 ,TTV 2 is the TTV value before etching of the silicon wafer to be etched 1 Is 1.5;
k is a constant coefficient and is adjusted according to the overflow circulation flow rate of the etching solution, the circulation temperature and the composition of the etching solution;
N 2 the inert gas is filled with flow rate in L/min.
2. The method of claim 1, wherein the etching process includes a step of etching the wafer,
the silicon wafer adopts HF/O 3 Cleaning to expose the surface; the HF/O 3 Cleaning is carried out by adopting a cleaning solution in a circulating way, wherein the HF acid volume percentage concentration in the cleaning solution is 3-10%, the ozone content is 1-2.6 ppm, the circulating flow is 20-26L/min, and the temperature is 55-60 ℃.
3. The method of claim 2, wherein the acid etching is performed in a manner that controls the topography of the silicon wafer,
at the HF/O 3 Before the cleaning treatment, the method also comprises a step of pre-cleaning the silicon wafer, which is used for removing impurities on the surface of the silicon wafer; the precleaning is added with a cleaning agent, the cleaning temperature is 60-70 ℃, and the precleaning is carried out under an ultrasonic condition.
4. The method of claim 1, wherein the acid etching process is performed in a batch process,
the inert gas bubbles are in the nanometer level.
5. The method of claim 1, wherein the etching process includes a step of etching the wafer,
when the circulation flow rate of the etching solution is 170L/min, the circulation temperature is 21 ℃, and the composition of the etching solution is HF and HNO 3 And when the volume ratio is 25.
6. The method of claim 1, wherein the acid etching process is performed in a batch process,
the etching also comprises the use of HF/O 3 And (5) cleaning again.
7. The method of claim 6, wherein the acid etching is performed in a batch process,
the HF/O 3 The cleaning method also comprises a step of cleaning by adopting ozone gas.
CN202111677464.2A 2021-12-31 2021-12-31 Acid etching method for controlling morphology of silicon wafer Active CN114420554B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111677464.2A CN114420554B (en) 2021-12-31 2021-12-31 Acid etching method for controlling morphology of silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111677464.2A CN114420554B (en) 2021-12-31 2021-12-31 Acid etching method for controlling morphology of silicon wafer

Publications (2)

Publication Number Publication Date
CN114420554A CN114420554A (en) 2022-04-29
CN114420554B true CN114420554B (en) 2022-10-11

Family

ID=81272054

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111677464.2A Active CN114420554B (en) 2021-12-31 2021-12-31 Acid etching method for controlling morphology of silicon wafer

Country Status (1)

Country Link
CN (1) CN114420554B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011251907A (en) * 2011-09-09 2011-12-15 Osaka Univ Method and apparatus for processing surface

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3428615B2 (en) * 1996-08-29 2003-07-22 三菱住友シリコン株式会社 Etching apparatus and etching method
WO1998044541A1 (en) * 1997-04-03 1998-10-08 Memc Electronic Materials, Inc. Flattening process for semiconductor wafers
JP2002329691A (en) * 2001-04-27 2002-11-15 Shin Etsu Handotai Co Ltd Method of cleaning silicon wafer
CN101717938B (en) * 2009-11-10 2011-04-20 天津市环欧半导体材料技术有限公司 Technique for etching silicon slice with acid
JP2012238719A (en) * 2011-05-11 2012-12-06 Mitsubishi Electric Corp Silicon substrate etching method and etching device
CN113496887B (en) * 2020-04-03 2023-06-02 重庆超硅半导体有限公司 Uniform etching method of silicon wafer for integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011251907A (en) * 2011-09-09 2011-12-15 Osaka Univ Method and apparatus for processing surface

Also Published As

Publication number Publication date
CN114420554A (en) 2022-04-29

Similar Documents

Publication Publication Date Title
EP1295320A2 (en) Process for etching silicon wafers
JPH08298233A (en) Manufacture of wafer for calibration with flawless layer of depth determined correctly and wafer for calibration
KR102014926B1 (en) Method for predicting thickness of oxide layer of silicon wafer
JPH0822972A (en) Process and apparatus for manufacture of semiconductor device
CN101769848A (en) Method for detecting etching fluid filter
EP2039654A2 (en) Washing method, Washing apparatus for polycrystalline silicon and method of producing polycrystalline
CN114420554B (en) Acid etching method for controlling morphology of silicon wafer
US6630363B2 (en) Method for evaluating impurity concentrations in unpolished wafers grown by the Czochralski method
WO2005057645A1 (en) Silicon wafer processing method
JP7487655B2 (en) Silicon wafer resistivity measurement method
Gould et al. An in situ ellipsometric study of aqueous NH 4 OH treatment of silicon
JP3686910B2 (en) Etching method of silicon wafer
JP5216749B2 (en) Processing method of silicon wafer
US7888142B2 (en) Copper contamination detection method and system for monitoring copper contamination
JP2017219409A (en) Surface defect inspection method of semiconductor silicon wafer
JP2003209150A (en) Method for evaluating silicon wafer and etching agent therefor
JP7279753B2 (en) Silicon wafer cleaning method and manufacturing method
JP2894154B2 (en) Method for measuring the depth of the affected layer on the silicon wafer surface
JP4103304B2 (en) Silicon wafer manufacturing method
TWI814488B (en) Thickness measurement method and flatness measurement method of high resistance silicon wafer
JP3890981B2 (en) Alkaline etching solution, method for etching silicon wafer using this etching solution, and method for differentiating front and back surfaces of silicon wafer using this method
KR102368657B1 (en) Method for measuring defect of silicon wafer and wafer
US5573680A (en) Method for etching a semiconductor material without altering flow pattern defect distribution
WO2022190830A1 (en) Method for cleaning silicon wafer, method for producing silicon wafer, and silicon wafer
JPH031537A (en) Etching of silicon semiconductor wafer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant