CN114374781B

CN114374781B - Recorder and data processing method

Info

Publication number: CN114374781B
Application number: CN202111620327.5A
Authority: CN
Inventors: 尹志新
Original assignee: Hangzhou Haikang Auto Software Co ltd
Current assignee: Hangzhou Haikang Auto Software Co ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2023-12-29
Anticipated expiration: 2041-12-27
Also published as: CN114374781A

Abstract

The invention provides a recorder and a data processing method, which are applied to the technical fields of automobile data recorders and data storage and are used for meeting the service requirement of fully exporting data of the recorder in a short time. There is provided a recorder comprising: the system comprises a main control chip, a gating switch, an interface converter, a memory and a peripheral interface. The port controller is configured to transmit data to the gating switch; the gating switch is configured to turn on a first switching path between the first gating port and the second gating port, and the main control chip is capable of transmitting data to the memory at a first speed through the first switching path of the gating switch and the first port of the interface converter. The peripheral interface is configured to couple with a host computer for exporting data in the storage at a second speed through the peripheral interface and a second port of the interface converter. The second speed is greater than the first speed.

Description

Recorder and data processing method

Technical Field

The invention relates to the technical field of data storage, in particular to a recorder and a data processing method.

Background

The video recorder system is applied to a train carriage, can perform data recording equipment signal acquisition, analog-to-digital conversion, compression coding, file storage, high-speed export of storage files and the like on video images and sounds in a train, and is used for video monitoring in a train operation state.

In the process of temporary stop of the train arriving at the station, the code stream data stored in the video recorder system is required to be quickly exported to a PC (personal computer ) upper computer of the station. In order to meet the requirement that the data in the video recorder system is completely exported within a short time, the data export speed of the video recorder system is required to be more than 50 MB/s.

Disclosure of Invention

The invention provides a recorder and a data processing method and a computer readable storage medium, which are used for meeting the business requirements of high-efficiency data storage by the recorder and complete export of the data of the recorder in a short time.

In one aspect, the present invention provides a recorder comprising: the system comprises a main control chip, a gating switch, an interface converter, a memory and a peripheral interface. The main control chip comprises a port controller, the gating switch comprises a first gating port and a second gating port, and the interface converter comprises a first port, a second port and a third port. The port controller of the main control chip is coupled with a first gating port of the gating switch, a second gating port of the gating switch is coupled with a first port of the interface converter, a second port of the interface converter is coupled with the peripheral interface, and a third port of the interface converter is coupled with the storage. The port controller is configured to transmit data to the gating switch; the gating switch is configured to turn on a first switching path between the first gating port and the second gating port, and the main control chip is capable of transmitting data to the memory at a first speed through the first switching path of the gating switch and the first port of the interface converter. The peripheral interface is configured to couple with a host computer for exporting data in the storage at a second speed through the peripheral interface and a second port of the interface converter. Wherein the second speed is greater than the first speed.

In some embodiments, the gating switch further comprises a third gating port coupled with the peripheral interface. The gating switch is configured to turn on a second switching path between the second gating port and the third gating port; the upper computer is used for exporting data in the storage at a first speed through the peripheral interface, the second switch path of the gating switch and the first port of the interface converter.

In some embodiments, the port controller is an nth generation universal serial bus controller;

the first gating port, the second gating port, the third gating port and the first port are all Nth generation universal serial bus ports;

the second port is an Mth generation universal serial bus port, and the peripheral interface is an Mth generation universal serial bus interface; the data transmission speed supported by the N-th generation universal serial bus is smaller than the data transmission speed supported by the M-th generation universal serial bus;

for example, in some embodiments, the port controller is a second generation universal serial bus controller. The first gating port, the second gating port, the third gating port and the first port are all second-generation universal serial bus ports. The second port is the Mth generation universal serial bus port, and the peripheral interface is the Mth generation universal serial bus interface.

In some embodiments, the peripheral interface comprises: a first transmission pin and a second transmission pin. The first transmission pin is coupled with the second port, and a data transmission link between the first transmission pin and the second port is an Mth generation universal serial bus data transmission link; and the second transmission pin is coupled with the third gating port, and a data transmission link between the second transmission pin and the third gating port is an N generation universal serial bus data transmission link. For example, the data transmission link between the first transmission pin and the second port is a third generation universal serial bus data transmission link, and the data transmission link between the second transmission pin and the third strobe port is a second generation universal serial bus data transmission link.

In some embodiments, the master control chip further comprises: the record appearance still includes data recording equipment, and main control chip still includes: a data input port. The data recording device is coupled with the data input port and is configured to record video and audio data. The data input port is configured to receive data input by the data recording device. In some embodiments, the master control chip further comprises a gating switch control pin; the gating switch further includes a control signal receiving pin. The gating switch control pin is coupled with the control signal receiving pin, and the gating switch control pin is configured to output a control signal to the control signal receiving pin, wherein the control signal is used for controlling the first switch passage to be conducted and controlling the second gating switch to be conducted or controlling the second gating switch to be conducted. The gating switch is configured to either turn on the first switching path or turn on the second switching path under control of the control signal.

In some embodiments, the main control chip further comprises a power switch pin and an external detection pin; the peripheral interface further comprises: a power pin and a detection input pin. Wherein the power switch pin is coupled to the power pin, the power switch pin configured to provide power to the power pin. The external detection pin is coupled with the detection input pin, and the detection input pin is configured to output a first level of a first detection signal when the peripheral interface is connected with the upper computer, and output a second level of the first detection signal when the peripheral interface is not connected with the upper computer. The external detection pin is configured to output a first level of a second detection signal when the first level of the first detection signal is received, and to output a second level of the second detection signal when the second level of the first detection signal is received.

In some embodiments, the main control chip is configured to control the gating switch control pin to output a first level of the control signal when the peripheral interface is detected to be connected to the upper computer, the first level is used for controlling the first switch channel to be conducted, and the main control chip is configured to control the gating switch control pin to output a second level of the control signal when the peripheral interface is not detected to be connected to the upper computer, and the second level is used for controlling the second switch channel to be conducted.

In some embodiments, the storage is a memory card. The interface converter further comprises a storage control unit; the interface converter is configured to convert the format of the data received by the first port from the main control chip into a data format suitable for the storage, store the converted data into the storage control unit and then transmit the data to the storage through the third port; and the interface converter is configured to convert the format of the data received from the storage by the third port into a universal serial bus format, store the converted data into the storage control unit, and transmit the data to the first port or the second port.

On the other hand, the invention also provides a data processing method which is applied to the recorder of any one of the aspects. Wherein, the record appearance includes: the system comprises a main control chip, an interface converter, a memory and a peripheral interface.

The data processing method of the recorder comprises the following steps: the main control chip judges whether the peripheral interface is externally connected with the upper computer or not, and if the peripheral interface is connected with the upper computer, the main control chip controls the recorder to enter a data storage mode or a data export mode; or if the peripheral interface is not connected with the upper computer, the main control chip controls the recorder to enter a data storage mode.

In a data storage mode, the main control chip controls the first switch passage of the gating switch to be conducted and configures the interface converter into a working state, and the main control chip transmits data to the storage at a first speed through the first switch passage of the gating switch and the first port of the interface converter; in the data export mode, the upper computer is used for exporting the data in the storage at a second speed through the peripheral interface and a second port of the interface converter; wherein the second speed is greater than the first speed.

According to the data export method provided by the invention, under the data storage mode, the recorder can acquire data and store the data into the storage. In the data export mode, the recorder uploads the data to the upper computer through the interface converter at a second speed, and the purpose of exporting the data at a high speed is achieved.

In some embodiments, in the data export mode, the master control chip controls the second switch path of the gating switch to be turned on, and the upper computer is used for exporting the data in the storage at a first speed through the peripheral interface, the second switch path of the gating switch, and the first port of the interface converter.

In some embodiments, the data processing method of the recorder further includes: in the state that the peripheral interface is connected with the upper computer, the data processing method further comprises the step of setting a priority strategy, wherein the priority strategy comprises the following steps: storing the priority policy and deriving the priority policy. The storage priority strategy enables the working mode of the recorder to enter a data storage mode; the export priority policy causes the recorder's operating mode to enter a data export mode.

And judging that the peripheral interface is connected to the upper computer based on the main control chip, and controlling the recorder to enter a data storage mode or a data export mode according to the set result of the priority strategy.

In some embodiments, the main control chip further comprises a power switch pin and an external detection pin. The peripheral interface further comprises: a power pin and a detection input pin. The main control chip judges whether the peripheral interface is connected with the upper computer or not, and comprises: the peripheral interface controls the detection input pin to output a first level of the first detection signal under the condition of accessing the upper computer, and controls the detection input pin to output a second level of the first detection signal under the condition of not accessing the upper computer. The external detection pin switches the level of the output second detection signal to the first level when the first level of the first detection signal is received, and switches the level of the output second detection signal to the second level when the second level of the first detection signal is received. The main control chip judges whether the first level of the second detection signal is inquired, if so, the peripheral interface is indicated to be connected with the upper computer, and if not, the peripheral interface is indicated to be not connected with the upper computer. In the data export mode, the main control chip also controls the power switch pin to output a first level of the first power signal, and the power switch pin is used for receiving the first level of the first power signal and switching the level of the output second power signal into the first level.

In some embodiments, the master control chip further comprises a gating switch control pin; the gating switch further includes a control signal receiving pin. In the data storage mode, the main control chip controls the first switch path of the gating switch to be conducted, and the method comprises the following steps: the main control chip controls the gating switch to control the pin to output a first level of the control signal. The control signal receiving pin of the gating switch is used for receiving a first level of the control signal, and the gating switch is used for controlling the first switch passage to be conducted under the control of the first level of the control signal. In the data export mode, the main control chip controls the second switch path of the gating switch to be conducted, and the method comprises the following steps: the main control chip controls the gating switch to control the pin to output a second level of the control signal. The control signal receiving pin of the gating switch is used for receiving a second level of the control signal, and the gating switch is used for controlling the conduction of the second switch passage under the control of the second level of the control signal.

In some embodiments, the peripheral interface further comprises a first transfer pin and a second transfer pin. In the data export mode, the upper computer is used for carrying out self-adaptive detection of interface specifications and communication protocols on the interface converter. If the transmission port of the upper computer is an Mth generation (for example, third generation) universal serial bus port, an Mth generation (for example, third generation) universal serial bus data transmission link is established between the first transmission pin and the second port. The host computer drives the interface converter and derives the data in the storage at a second speed through an mth generation (e.g., third generation) universal serial bus data transmission link. If the transmission port of the upper computer is an nth generation (for example, a second generation) universal serial bus port, an nth generation (for example, a second generation) universal serial bus data transmission link is established between the second transmission pin and a third gating port of the gating switch. The host computer drives the interface converter and derives data in the storage at a first speed through an nth generation (e.g., second generation) universal serial bus data transmission link, a second switching path and a first port of the interface converter.

In some embodiments, the data processing method further comprises: the recorder is started, and the gating switch defaults to conduct a second switching path between the second gating port and the third gating port; the level of the second power signal output by the power pin of the peripheral interface defaults to the first level. The main control chip controls the power switch Guan Guanjiao to output the second level of the first power signal, and the power pin is used for receiving the second level of the first power signal and switching the first level of the output second power signal to the second level. The main control chip judges whether the peripheral interface is connected with the upper computer.

In yet another aspect, a computer program is provided. The computer program, when executed on a computer, causes the computer to perform the data processing method as described in any of the embodiments above.

In yet another aspect, the present invention also provides a computer-readable storage medium comprising computer-executable instructions which, when run on a computer, cause the computer to perform the data processing method as in any one of the above aspects.

In yet another aspect, a computer program product is provided that is stored on a non-transitory computer readable storage medium. The computer program product comprises computer program instructions which, when executed on a computer, cause the computer to perform a data processing method as described in any of the embodiments above.

A computer readable storage medium, a computer program product and a computer program for performing the data processing method provided above, and thus the advantages achieved by this are referred to as advantages in the data processing method provided above and will not be described in detail here.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a physical structure of a recorder according to some embodiments of the related art;

FIG. 2 is a physical architecture diagram of another recorder according to some embodiments of the present invention;

FIG. 3 is a physical architecture diagram of yet another recorder according to some embodiments of the present invention;

FIG. 4 is a diagram illustrating the connection of a peripheral interface to a second port and a third strobe port according to some embodiments of the present invention;

FIG. 5 is a physical architecture diagram of a recorder with a control gate switch function according to some embodiments of the present invention;

FIG. 6 is a physical architecture diagram of a recorder with a current path between a host chip and a peripheral interface according to some embodiments of the present invention;

FIG. 7 is a diagram of a logic architecture of a recorder according to some embodiments of the present invention;

FIG. 8 is a flowchart illustrating operation of a first scenario of a recorder according to some embodiments of the present invention;

fig. 9a to 9b are operation state diagrams of a recorder in a first scenario according to some embodiments of the present invention;

FIG. 10 is a flow chart illustrating operation of a second scenario and a third scenario of a recorder according to some embodiments of the present invention;

FIG. 11 is a diagram illustrating a second scenario of a recorder according to some embodiments of the present invention;

fig. 12 is a diagram illustrating an operation state of a recorder according to a third embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", "some examples", "and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled (communicatively coupled)" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As shown in fig. 1 and 2: some embodiments provide a recorder 100, for example, an audio-visual recorder, which can be installed on a train, a ship or a vehicle, etc. for capturing video images and sounds in the train, the ship or the vehicle, so as to facilitate later scene review for a specific occasion in a certain time period.

In some embodiments, taking the recorder 100 as a train recorder for example, when the recorder 100 is applied to a train, the video image and the sound data stored on the recorder 100 are required to be quickly exported to an upper computer of a stop station within a short stay time of each arrival of the train. The train is at a stop for a short time, for example, the high-speed rail train is at a partial stop for only two minutes. In a short time, it is required to export video and audio data stored inside the recorder 100 to a host computer, for example: the upper computer can be a computer or a mobile phone with OTG (On-The-Go) function. The data lead-out speed of the recorder 100' is above 50 MB/s.

In some embodiments, universal serial bus (Universal Serial Bus, USB) communication is employed between the recorder 100 and the host computer. In some related art, as shown in fig. 1: the main control chip 10 of the recorder 100 adopts a second generation universal serial bus transmission controller (USB 2.0 controller), the main control chip 10 stores signals (video streams) collected by the data recording device 20 (such as a camera lens) into the storage chip 11 after analog-digital conversion and compression coding, when data are required to be exported, the main control chip 10 exports the data in the storage chip 11, after the data transmission is controlled by the USB2.0 controller, the data are output to the peripheral interface 60, the peripheral interface 60 is connected through an upper computer, and the data are uploaded to the upper computer, wherein the peripheral interface 60 is a USB2.0 interface so as to correspond to the model of the USB2.0 controller. The main control chip 10 further includes a power module 18, the power module 18 being coupled to the power switch pin 16 and configured to provide a power signal. The main control chip 10 can meet the service requirement of the train, but cannot meet the requirement that the data export speed of the recorder 100 is more than 50 MB/s. The third generation universal serial bus transmission controller (USB 3.0 controller) can meet the requirement that the data export speed of the recorder 100 is more than 50MB/s, but the main control chip 10 adopting the USB3.0 controller can not meet the service requirement of a train. The data transmission speed supported by the second generation universal serial bus is smaller than that supported by the third generation universal serial bus.

Based on this, some embodiments of the present invention provide a recorder 100, as shown in fig. 2: the recorder 100 includes: the device comprises a main control chip 10, a gating switch 30, an interface converter 40, a storage 50 and a peripheral interface 60. The main control chip 10 includes a port controller 12, the gating switch 30 includes a first gating port 31 and a second gating port 32, and the interface converter 40 includes a first port 41, a second port 42 and a third port 43. The port controller 12 of the main control chip 10 is coupled to the first gate port 31 of the gate switch 30, the second gate port 32 of the gate switch 30 is coupled to the first port 41 of the interface converter 40, the second port 42 of the interface converter 40 is coupled to the peripheral interface 60, and the third port 43 of the interface converter 40 is coupled to the memory 50. The port controller 12 is configured to control data transfer to the gate switch 30. The gate switch 30 is configured to conduct a first switch path between the first gate port 31 and the second gate port 32. The main control chip 10 can transmit data to the memory 50 at a first speed by gating the first switching path of the switch 30 and the first port of the interface converter 40. The peripheral interface 60 is configured to couple with a host computer for exporting data in the storage 50 at a second speed through the peripheral interface 60 and the second port 42 of the interface converter 40. Wherein the second speed is greater than the first speed.

In the recorder 100 provided in the above embodiment of the present invention, when the gate switch 30 turns on the first switch path, the main control chip 10 can transmit data to the memory 50 at the first speed through the gate switch 30 and the interface converter 40, thereby realizing the data storage function. In the case that the peripheral interface 60 is externally connected with an upper computer, the upper computer is used for exporting the data in the storage 50 at a second speed through the peripheral interface and the second port 42 of the interface converter 40, thereby realizing the exporting function of the data. And since the first speed is greater than the second speed, i.e., the data is exported at a high speed during the export process, the recorder 100 can export a large amount of data quickly in a short time. In some examples, the first speed is the speed when the recorder 100 in the related art uses the USB2.0 controller and the USB2.0 interface for data storage and data export, and the second speed is the speed when the recorder 100 in the related art uses the USB3.0 interface for data export, for example, the first speed may be 20MB/s; the second speed may be 70MB/s.

In some embodiments, the gating switch 30 conducts a first switching path between the first gating port 31 and the second gating port 32, for example, the first gating port 31 and the second gating port are communicated through two ends of the conductive contact 3', where the communication is an electrical contact of a physical layer, i.e. a direct physical electrical contact, and whether the first switching path transmits data is controlled by the main control chip 10. In the data storage process, the main control chip 10 controls data to be transmitted through the first switch path. The first switch path of the gate switch 30 may be maintained, that is, the first gate port 31 and the second gate port are communicated, during the data outputting, and the main control chip 10 controls the first switch path not to perform data transmission, and in other embodiments, the gate switch 30 opens the first switch path between the first gate port 31 and the second gate port 32 during the data outputting.

It should be noted that, the first gate port 31, the second gate port 32, the first port 41, the second port 42, and the third port 43 are ports disposed inside the host computer of the recorder 100, and the different ports are coupled by data lines for transmitting data signals inside the host computer of the recorder 100, for example, the main control chip 10, the gate switch 30, the interface converter 40, and the memory 50 are modularized components disposed inside the recorder 100. The peripheral interface 60 is an interface provided outside the recorder 100 for connection with an external device (e.g., an upper computer), and the peripheral interface 60 is a plug-in type connector. Alternatively, the first gate port 31, the second gate port 32, the first port 41, the second port 42, and the third port 43 each include a plurality of pins, and the plurality of pins of the different ports are coupled by a lead/wire, and the first gate port 31, the second gate port 32, the first port 41, the second port 42, and the third port 43 are each used for transmitting data signals. The main control chip 10, the gate switch 30, the interface converter 40, and the memory 50 are electrical components integrated on a circuit board fixed inside the recorder 100.

The port controller 12 includes a control logic circuit and a data output port 13, the control logic circuit is a circuit disposed inside the port controller 12 and is used for completing control and processing of data transmission, parsing and packaging of data packets, encoding and decoding of transmitted signals, and the like, the data output port 13 is an exposed interface, and the data output port 13 is a USB2.0 port. The port controller 12 and the first strobe port 31 are coupled through the data output port 13.

For example: the first gate port 31, the second gate port 32, the first port 41, the second port 42 and the third port 43 are pins, the pins of the different ports are connected by wires, and the wires are welded with the pins. For example, the peripheral interface 60 is a USB female connector, and the host computer needs to be configured with a male connector adapted to the peripheral interface 60, and the connection portion of the host computer is electrically connected to the peripheral interface in a direct plug-in manner and is pluggable.

The port controller 12 in the recorder 100 provided in the above embodiment of the present invention may be an nth generation (e.g., second generation) usb controller in the related art shown in fig. 1, that is, the port controller 12 adopted by the main control chip 10 is still in the existing structure, and no new port controller 12 is needed to be provided, so that the type selection requirement of the recorder 100 on the main control chip 10 can be satisfied.

Illustratively, the port controller 12 is an nth generation (e.g., second generation) universal serial bus controller. The first strobe port 31, the second strobe port 32, and the first port 41 are all nth generation (e.g., second generation) universal serial bus ports (e.g., USB2.0 ports). The second port is an mth generation (e.g., third generation) USB port (e.g., USB3.0 port), and the peripheral interface 60 is an mth generation (e.g., third generation) USB port (e.g., USB3.0 port). Illustratively, the USB2.0 port may be: type-A USB2.0 female or type-A USB2.0 data line pin, micro-B USB2.0 female or Micro-B USB2.0 data line pin. The USB3.0 port may be: type-A USB3.0 female or type-A USB3.0 data line pin, micro-B USB3.0 female or Micro-B USB3.0 data line pin. The USB3.0 interface may be: type-A USB3.0 female, type-C USB3.0 female, or Micro-B USB3.0 female, etc.

Some of the benefits of the record 100 provided by some embodiments of the present invention are: on the basis of adopting the existing main control chip 10, the purposes of data storage and data high-speed export are achieved. The specific method is as follows: the present invention provides a new storage-export control logic, namely, data storage and export using two data transmission links. While realizing that the data export is not limited by the main control chip 10, different data export speeds and data export formats can be selected according to the needs, and effective storage of data and effective export of data can be ensured. The invention discloses that the peripheral interface 60 is an mth generation (e.g. third generation) universal serial bus interface, and cooperates with the interface converter 40 to realize data export at a second speed, or the peripheral interface 60 can adopt a TTL serial interface or an RS232 interface, etc. In the present invention, the port controller 12 of the main control chip 10 is not directly connected with the peripheral interface 60, and different data transmission paths are formed in the recorder 100, namely, the data transmission path from the main control chip 10 to the storage 50 through the gate switch 30 and the interface converter 40, and the data transmission path from the storage 50 to the peripheral interface 60 through the interface converter 40 are not affected by each other, and the data can be transmitted at different speeds under the effect of the gate switch 30, so that the model selection of the peripheral interface 60 can not depend on the model influence of the port controller 12 of the main control chip 10, and the peripheral interface 60 can be an interface with a high-speed transmission function, thereby achieving the purpose of deriving the data at a high speed in a short time.

In some embodiments, as shown in fig. 3: the gating switch 30 further comprises a third gating port 33, the third gating port 33 being coupled with the peripheral interface 60. The gating switch 30 is further configured to conduct a second switching path between the second gating port 32 and the third gating port 33, the host computer being configured to export data in the memory 50 at a first speed through the peripheral interface 60, the second gating switch of the gating switch 30 and the first port of the interface converter 40.

In some embodiments, the gating switch 30, when conducting the second switching path between the second gating port 32 and the third gating port 33, also disconnects the first switching path between the first gating port 31 and the second gating port 32, for example, one end of the conductive contact 3' in the gating switch 30 is coupled to the second gating port 32, and the other end is switched from the first gating port 31 to the third gating port 33, thereby realizing disconnection of the first switching path and conduction of the second switching path.

Illustratively, the third strobe port 33 is an nth generation universal serial bus port (e.g., a USB2.0 port).

In the following embodiments, for convenience of description of the present application, the nth generation universal serial bus is mainly taken as the second generation universal serial bus, and the mth generation universal serial bus is taken as the third generation universal serial bus as an example, which is described by way of example, but should not be construed as a specific limitation of the embodiments of the present application. The data transmission speed supported by the nth generation universal serial bus is smaller than that supported by the Mth generation universal serial bus, and the values of M and N can be determined according to the update development of the universal serial bus technology.

The recorder 100 provided in the above embodiment of the present invention establishes the second switch path, which can be used for being compatible with the USB2.0 interface of the host computer, so that when the host computer has the USB3.0 port, the host computer can read and write the storage 50 at the second speed; when the host computer adopts the original interface (USB 2.0 interface), a data transmission link can be formed with the storage 50 through the third gating port 33, the second gating port 32 and the first port 41 in sequence, and the host computer reads and writes the storage 50 at a first speed. In this way, the recorder 100 can be implemented to upload data at the second speed while still being compatible with existing connected devices and upload the data at the first speed.

In some embodiments, as shown in fig. 3, the peripheral interface 60 includes: a first transmission pin 61 (SSRX/TX) and a second transmission pin 62 (d+/D-). The first transmission pin 61 is coupled to the second port 42, and the data transmission link between the first transmission pin 61 and the second port 42 is an mth generation (e.g., third generation) universal serial bus data transmission link (e.g., USB3.0 transmission data link). The second transmission pin 62 is coupled to the third strobe port 33, and the data transmission link between the second transmission pin 62 and the third strobe port 33 is an nth generation (e.g., second generation) universal serial bus data transmission link (e.g., USB2.0 transmission data link).

Illustratively, as shown in fig. 4: the peripheral interface 60 is a type-C USB3.0 female, and the first transmission pin 61 of the peripheral interface 60 includes: tx+ pin, rx+ pin, TX-pin and RX-pin; the second transmission pin 62 includes: a D+ pin and a D-pin. Wherein the tx+ pin, the rx+ pin, the TX-pin, the RX-pin are coupled with corresponding pins of the second port 42, for example: the TX+ pin of the type-C USB3.0 female is coupled with the RX+ pin of the second port 42, the RX+ pin of the type-C USB3.0 female is coupled with the TX+ pin of the second port 42, the TX-pin of the type-C USB3.0 female is coupled with the RX-pin of the second port 42, and the RX-pin of the type-C USB3.0 female is coupled with the TX-pin of the second port 42. the d+ pin of the type-C USB3.0 female is coupled with the d+ pin of the third strobe port 33, and the D-pin of the type-C USB3.0 female is coupled with the D-pin of the third strobe port 33.

In some embodiments, as shown in fig. 5: the recorder 100 further includes a data recording device 20, and the main control chip 10 further includes: a data input port 14. The data recording device 20 is coupled to the data input port 14. The data recording device 20 is configured to record audio-visual data; the data input port 14 is configured to receive data input by the data recording device 20. For example: the data recording device 20 may be a microphone, and the microphone collects sound data and uploads the sound data to the main control chip 10; the data recording device 20 further comprises a camera, and the camera is used for recording video image data and uploading the video image data to the main control chip 10.

In some examples, port controller 12 is configured to complete control of data transfer, configuring interface converter 40 to an operational mode. Illustratively, after the first switch path is turned on, a data link is established between the main control chip 10 and the memory 50, and the port controller 12 performs logic driving to configure the interface converter 40 in an operation mode. The data recording device 20, such as a microphone and a camera, uploads data to the main control chip 10, the main control chip 10 receives the data, performs analog-to-digital conversion and compression encoding, and then transmits the data to the memory 50, the data transmitted by the main control chip 10 passes through the port controller 12, and the port controller 12 transmits the data to the memory 50 sequentially through the first strobe port 31, the second strobe port 32, the first port 41 and the third port 43.

In some embodiments, as shown in fig. 5: the main control chip 10 further comprises a gating switch control pin (channel_switch_gpio) 15; the gating switch 30 also includes a control signal receiving pin (GPIO) 34. The gate switch control pin 15 is coupled to the control signal receiving pin 34, and the gate switch control pin 15 is configured to output a control signal for controlling the on and off of the first switch path and the on and off of the second gate switch 32 to the control signal receiving pin 34. The gating switch 30 is configured to either turn on the first switching path or turn on the second switching path under control of a control signal.

Illustratively, the control signal receiving PIN 34 and the gating switch control PIN 15 are both general purpose input/output PINs, such as PIN PINs. The signals output from the control signal receiving pin 34 and the gate switch control pin 15 are signals having a high level and a low level, which are respectively indicated by 1 and 0. As shown in fig. 9 b: when the signal output from the gate switch control pin 15 is at a first level, for example, a high level, the second gate port 32 is coupled to the first gate port 31 to form a first switch path. As shown in fig. 12: when the signal output from the gate switch control pin 15 is a second voltage signal, for example, a low level, the second gate port 32 is coupled to the third gate port 33.

In some embodiments, as shown in fig. 6: the main control chip 10 further includes a power switch pin (typec_switch_gpio) 16 and an external detection pin (connect_detect_gpio) 17; the peripheral interface 60 further includes: a POWER Pin (POWER) 63 and a sense input pin (VBUS) 64. The power switch PIN 16 and the external detection PIN 17 are universal input/output PINs, such as PIN PINs. The signals output from the power switch pin 16 and the external detection pin 17 are signals having a high level and a low level, which are respectively indicated by 1 and 0. The power supply PIN 63 and the detection input PIN 64 are PIN PINs, and the signals output from the power supply PIN 63 and the detection input PIN 64 are signals having a high level and a low level, the high level being represented by 1, and the low level being represented by 0. The high level output by the main control chip 10 and the peripheral interface 60 is +3.3V or +5V, and the low level output by the main control chip and the peripheral interface 60 is 0. The first level of each pin output appearing below is a high level, and the second level is a low level.

The power switch pin 16 is coupled to the power pin 63, the power switch pin 16 being configured to provide power to the power pin 63. The external detection pin 17 is coupled with the detection input pin 64, and the detection input pin 64 is configured to output a first level of a first detection signal when the peripheral interface 60 is connected to the upper computer, and output a second level of the first detection signal when the peripheral interface 60 is not connected to the upper computer; the external detection pin 17 is configured to output a first level of the second detection signal when the first level of the first detection signal is received, and to output a second level of the second detection signal when the second level of the first detection signal is received.

The level of the first detection signal outputted from the detection input pin 64 has two states, and when the peripheral interface 60 is connected to the host computer and when the peripheral interface 60 is not connected to the host computer, different levels are outputted, and the level of the first detection signal outputted from the detection input pin 64 when the peripheral interface 60 is connected to the host computer is referred to as a first level, and the level of the first detection signal outputted from the detection input pin 64 when the peripheral interface 60 is not connected to the host computer is referred to as a second level. The level of the second detection signal output by the external detection pin 17 has two states, and when different levels of the first detection signal are received, the different levels are output, and the level of the second detection signal output when the external detection pin 17 receives the first level of the first detection signal is referred to as the first level, and the level of the second detection signal output when the external detection pin 17 receives the second level of the first detection signal is referred to as the second level. The first level and the second level of a certain signal are only one exemplary representation of the levels.

The main control chip 10 is configured to control a control signal output by the gating switch control pin 15 to be a first level when the external interface is detected to be connected with the upper computer, the first level controls the first switch channel to be turned on and the second switch channel to be turned off, and the main control chip 10 is configured to control a control signal output by the gating switch control pin 15 to be a second level when the external interface is not detected to be connected with the upper computer, and the second level controls the first switch channel to be turned off and the second switch channel to be turned on.

Illustratively, the peripheral interface 60 is a type-C USB3.0 female, and the power pin 63 of the type-C USB3.0 female is coupled to the power switch pin 16, so that the main control chip 10 supplies power to the peripheral interface 60 through the power switch pin 16.

As shown in fig. 4 and fig. 6, the VBUS pin of the type-C USB3.0 female header may be used as the detection input pin 64 and the external power supply pin, and in the case that the VBUS pin is used as the detection input pin 64, and in the case that the peripheral interface 60 is connected to the host computer, the VBUS pin receives the power provided by the host computer, so that the level of the VBUS pin changes, for example, from 0 to 1, so as to detect whether the peripheral interface is connected to the host computer. In addition, when the peripheral interface 60 is connected to the host computer, the VBUS pin is used as an external power pin, receives power provided by the host computer, and supplies power to the gate switch 30, the interface converter 40 and the storage 50, thereby realizing the power supply function in the data export mode.

The VBUS pin is coupled to the external detection pin 17, and when the host computer is connected to the peripheral interface 60, the host computer provides power to the VBUS pin, so that the VBUS pin outputs a first level of the first detection signal, when the external detection pin 17 receives the first level of the first detection signal, a first level of the second detection signal is output, and the external detection pin 17 feeds back the first level of the output second detection signal to the main control chip 10. When the main control chip 10 receives the first level of the second detection signal of the external detection pin 17, the external interface 60 can be judged to be connected with the upper computer; when the external detection pin 17 of the main control chip 10 outputs the second level of the second detection signal, it can be determined that the peripheral interface 60 is not connected to the host computer.

In some embodiments, the storage 50 is a memory card. The memory card may be, for example, a CF (Compact Flash) card, MMC (MultiMedia Card) card, SD (Secure Digital) card or the like. Illustratively, the recorder housing is provided with a memory card interface that is coupled with the third port 43 of the interface converter 40, the memory card being pluggable to facilitate data transfer and transmission.

In some embodiments, interface converter 40 further includes a memory control unit. As shown in fig. 6, the interface converter 40 is configured to convert the format of the data received by the first port 41 from the main control chip 10 into a data format suitable for the storage 50, store the converted data in the storage control unit, and transmit the converted data to the storage 50 through the third port 43; and converting the data received from the storage 50 by the third port 43 into a universal serial bus format, storing the converted data in the memory control unit, and transmitting the data to the first port 41 or the second port 42.

The third port 43 is configured as a port to which the interface converter 40 is connected with the memory card 50. For example, the memory card is an SD card, and the third port 43 is a SDIO (Secure Digital Input and Output) port. The interface converter 40 performs the mutual conversion of the USB data format and the SDIO data format on the data.

Illustratively, the interface converter 40 is a USB-SDIO HBA (USB to SDIO Host Bus Adapter, bus adapter) or a USB3.0 SD Card Reader (USB Reader), and when the interface converter 40 is a USB Reader, the storage control unit includes a Card Reader control chip and a USB3.0 control chip, wherein the USB3.0 control chip is coupled to the first port 41, the second port 42 and the Card Reader control chip, and the Card Reader control chip is coupled to the third port 43, and the Card Reader control chip may employ a Card Reader controller of a USB3.0 to SD4.0 memory Card.

In some embodiments, in the data storage mode, the power output pin of the port controller 12 supplies power to the interface converter 40 through the gating switch 30, and when the first gating port 31 and the second gating port 32 are interrupted, the current path between the power output pin of the port controller 12 and the interface converter 40 is interrupted.

In another aspect, some embodiments of the present invention provide a data processing method, which is applied to the recorder 100 described in any one of the above aspects. Wherein, the recorder 100 includes: the device comprises a main control chip 10, a gating switch 30, an interface converter 40, a storage 50 and a peripheral interface 60.

Wherein, as shown in fig. 6: a data processing method of the recorder 100, comprising: the main control chip 10 judges whether the peripheral interface 60 is connected with the upper computer, if yes, the main control chip 10 controls the recorder 100 to enter a data storage mode or a data export mode; if not, the main control chip 10 controls the recorder 100 to enter a data storage mode.

In the data storage mode, the main control chip 10 controls the first switching path of the gate switch 30 to be turned on and configures the interface converter 40 to be in an operating state, and the main control chip 10 transmits data to the memory 50 at a first speed through the first switching path of the gate switch 30 and the first port 41 of the interface converter 40.

In the data export mode, the host computer exports data in the storage 50 at a second speed through the peripheral interface 60 and the second port 42 of the interface converter 40.

Wherein the second speed is greater than the first speed.

Illustratively, the first and second gating ports 31, 32 are USB2.0 ports and the third port 43 is a USB3.0 port. In the data storage mode, the main control chip 10 controls the first switch path of the gate switch 30 to be turned on, data is sequentially transmitted to the interface converter 40 through the first gate port 31, the second gate port 32 and the first port 41, the interface converter 40 receives the data and configures an operating state, in the operating state, the interface converter 40 converts the format of the data from the main control chip 10 into a data format suitable for the memory 20, the converted data is stored in the memory control unit, and then the data is transmitted to the memory 50 through the third port 43. That is, the main control chip 10 establishes a first data transmission link composed of the first strobe port 31, the second strobe port 32, the first port 41, the memory main control chip and the third port 43, the first data transmission link is controlled by the port controller 12 of the main control chip 10, the data is transmitted at a first speed, and the first speed is the derived speed of the USB2.0 data link, that is, the transmission speed is less than 40MB/S.

In the data export mode, the main control chip 10 detects that the peripheral interface 60 is externally connected with an upper computer, and the recorder 100 enters the data export mode according to the setting. At this time, the main control chip 10 does not work, the upper computer controls the data export, the upper computer drives the interface converter 40, converts the format of the data received from the storage 50 by the third port 43 into a universal serial bus format, stores the converted data in the storage control unit, and then transmits the data to the second port 42. Under the condition that the interface of the upper computer is a 3.0USB interface, the data of the storage 50 are sequentially led out to the upper computer through the third port 43, the storage control unit, the second port 42 and the peripheral interface 60, the third port 43, the storage main control chip, the second port 42 and the peripheral interface 60 form a second data transmission link, the second data transmission link leads out the data at a second speed, and the second speed is the lead-out speed of the USB3.0 data link, namely, the transmission speed is more than 50MB/S, so that the high-speed lead-out of the data is realized.

In some embodiments, as shown in fig. 6, in the data export mode, the main control chip 10 controls the second switch path of the gate switch 30 to be turned on, and the host computer exports the data in the storage 50 at the first speed through the peripheral interface 60, the second switch path of the gate switch, and the first port 41 of the interface converter 40.

Illustratively, the main control chip 10 detects that the peripheral interface 60 is externally connected to the host computer, and the recorder 100 enters a data outputting mode according to the setting, and the main control chip controls the second switch path of the gate switch 30 to be turned on, and after the second switch path is turned on, the main control chip 10 stops working. The host computer controls the data export, drives the interface converter 40, converts the format of the data received from the storage 50 by the third port 43 into a universal serial bus format, stores the converted data in the storage control unit, and transmits the data to the first port 41. In the case that the interface of the host computer is a 2.0USB interface, the data of the storage 50 is sequentially led out to the host computer after passing through the third port 43, the storage control unit, the first port 41, the second switch path of the gate switch 30 and the peripheral interface 60, and the third port 43, the storage control unit, the first port 41, the second switch path of the gate switch 30 and the peripheral interface 60 form a third data transmission link, and the third data transmission link leads out the data at a first speed, so that the low-speed data export is realized.

In combination with the logic architecture diagram for data storage and export of the recorder shown in fig. 7, the specific process of the data processing method of the recorder is as follows:

In some embodiments, a data processing method includes: recorder 100 is on and gating switch 30 defaults to turn on the second switching path between second gating port 32 and third gating port 33. The peripheral interface 60 further comprises a power pin 63, and the level of the second power signal output by the power pin 63 of the peripheral interface 60 defaults to the first level, that is to say the peripheral interface 60 defaults to being powered. The main control chip 10 further includes a power switch pin 16, and the main control chip 10 controls the power switch pin 16 to output a second level of the first power signal, and the power pin 63 receives the second level of the first power signal and switches the first level of the output second power signal to the second level.

Illustratively, when the recorder 100 is powered on, the gating switch 30 defaults to turn on the second switching path, the power switch pin 16 of the main control chip 10 outputs a first level of the first power signal, the power pin 63 of the peripheral interface 60 receives the first level of the first power signal, and the level of the second power signal output by the power pin 63 of the peripheral interface 60 defaults to the first level. At this point a conductive data link is formed between the peripheral interface 60 and the memory 50. After the normal operation of the software, the software logic of the main control chip 10 pulls down the power switch pin 16, that is, the power switch pin 16 outputs the second level of the first power signal, and the power pin 63 receives the second level of the first power signal and switches the first level of the output second power signal to the second level. The peripheral interface 60 is powered down, at which point an interrupted data link is formed between the peripheral interface 60 and the memory 50.

In some embodiments, the main control chip 10 further comprises an external detection pin 17; the peripheral interface 60 further includes: the input pin 64 is detected. The data processing method further includes the main control chip 10 judging whether the peripheral interface 60 is connected to the host computer, and the steps include: the peripheral interface 60 controls the detection input pin 64 to output the first level of the first detection signal when the host is connected, and controls the detection input pin 64 to output the second level of the first detection signal when the host is not connected. The external detection pin 17 switches the level of the output second detection signal to the first level when the first level of the first detection signal is received, and switches the level of the output second detection signal to the second level when the second level of the first detection signal is received. The main control chip 10 determines whether the first level of the second detection signal is queried, if yes, it indicates that the peripheral interface 60 is connected to the upper computer, and if not, it indicates that the peripheral interface 60 is not connected to the upper computer. In the data deriving mode, the main control chip 10 also controls the power switch pin 16 to output a first level of the first power signal, and the power pin 63 receives the first level of the power signal and switches the level of the output second power signal to the first level.

Illustratively, as shown in fig. 6, the power switch pin 16 is pulled down under the control of the main control chip 10, the host computer is connected to the peripheral interface 60, and the host computer provides power to the peripheral interface 60, so that the detection input pin 64 outputs the first level of the first detection signal. After receiving the first level of the first detection signal, the external detection pin 17 switches the level of the output second detection signal to the first level. Similarly, the upper computer is not connected to the peripheral interface 60, and the peripheral interface 60 is not powered by external devices, so that the detection input pin 64 outputs the second level of the first detection signal. After receiving the second level of the first detection signal, the external detection pin 17 switches the level of the output second detection signal to the second level.

In some embodiments, the data processing method of the recorder 100 further includes: the data processing method further includes priority policy setting in a state where the peripheral interface 60 is connected to the host computer. In some embodiments, the priority policy settings include: storing the priority policy and deriving the priority policy. Wherein the storage priority policy causes the operation mode of the recorder 100 to enter a data storage mode; the export priority policy brings the operational mode of recorder 100 into a data export mode. In the process that the main control chip 10 judges whether the peripheral interface 60 is connected to the upper computer, and the main control chip 10 judges that the peripheral interface 60 is connected to the upper computer, the main control chip 10 controls the recorder to enter a data storage mode or a data export mode according to the set result of the priority strategy.

Illustratively, as shown in fig. 6, when the host computer is not connected to the peripheral interface 60, the recorder 100 enters a data storage mode when operating, i.e. the main control chip 10 stores the acquired data in the memory 50. When the host computer is connected into the peripheral interface 60, a user performs priority policy setting on the recorder 100 in advance, the priority policy setting structure is stored in the main control chip in advance, the recorder 100 can enter a data storage mode or a data export mode preferentially according to the priority policy setting structure, and if the priority data storage mode is set, the recorder 100 stores the data acquired by the main control chip 10 into the storage 50 preferentially. If the priority data export mode is set, the recorder will upload the data in the memory 50 to the host computer in priority.

In some embodiments, the master chip 10 further includes a gating switch control pin 15; gating switch 30 also includes a control signal receiving pin 34. In the data storage mode, the main control chip 10 controls the first switch path of the gating switch 30 to be turned on, including: the main control chip 10 controls the gate switch control pin 15 to output a first level of the control signal. The control signal receiving pin 34 of the gating switch 30 receives a first level of the control signal, and the gating switch 30 controls the first switch path to be turned on and the second switch path to be turned off under the control of the first level of the control signal.

In the data deriving mode, the main control chip 10 controls the second switch path of the gating switch 30 to be turned on, including: the main control chip 10 controls the gate switch control pin 15 to output the second level of the control signal. The control signal receiving pin 34 of the gating switch 30 receives the second level of the control signal, and the gating switch 30 keeps the first switch path closed and the second switch path conductive under the control of the second level of the control signal.

Illustratively, at a first level, i.e., in the powered state of the gating switch 30, a first switch path between the second gating port 32 and the first gating port 31 is autonomously open; in the power-off state of the gate switch 30, the second switch path between the second gate port 32 and the third gate port 33 is opened autonomously.

In some embodiments, a data processing method includes: recorder 100 is on and gating switch 30 defaults to turn on the second switching path between second gating port 32 and third gating port 33. The peripheral interface 60 further includes a power pin 63, and the level of the second power signal output from the power pin 63 of the peripheral interface 60 defaults to the first level. The main control chip 10 controls the power switch pin 16 to output the second level of the first power signal, and the power pin 63 receives the second level of the first power signal and switches the first level of the output second power signal to the second level.

In some embodiments, the peripheral interface 60 further includes a first transmission pin 61 and a second transmission pin 62. In the data export mode, the host computer performs adaptive probing of the interface specification and communication protocol for the interface converter 40.

If the transmission port of the upper computer is an mth generation (e.g., third generation) USB port (e.g., USB3.0 port), an mth generation (e.g., third generation) USB data transmission link (e.g., USB3.0 data transmission link) is established between the first transmission pin 61 and the second port 42. The host drives the interface converter 40 and derives data in the storage 50 at a second speed via an mth generation (e.g., third generation) usb data transmission link. If the transmission port of the upper computer is an nth generation (e.g., second generation) universal serial bus port (e.g., USB2.0 port), an nth generation (e.g., second generation) universal serial bus data transmission link (e.g., USB2.0 data transmission link) is established between the second transmission pin 62 and the third strobe port 33 of the strobe switch 3; the host drives the interface converter 40 and derives the data in the memory 50 at a first speed via the nth generation (e.g., second generation) usb data transmission link, the second switching path 32, and the first port 41 of the interface converter 40.

In some specific scenarios, taking the recorder 100 as a train recorder as an example, the invention has different running processes in different scenarios:

illustratively, in connection with fig. 7, 8 and 9a and 9 b: in a first application scenario, where the recorder 100 is mounted on a train mounting rack, the memory 50 stores a scenario whose workflow includes:

l1, the user starts up the recorder 100, and the initialized state of the recorder is shown in fig. 9 a: the default state is designed as follows:

a. the post-activation gating switch 30 defaults to the second gating port 32 and the third gating port 33 being in a coupled state.

b. The peripheral interface 60 is powered up by default and the transmission link between the peripheral interface 60 and the second gating port 32 and the transmission link between the peripheral interface 60 and the third gating port 33 are both provided with communication capabilities.

After the initialization state of the recorder is finished, the running state of the recorder is shown in fig. 9b, and the workflow in this scenario includes:

and L2, the main control chip 10 pulls down the power switch pin 16, and the external interface 60 is powered down, so that no communication capability exists between the external interface 60 and the second gating port 32 and between the external interface 60 and the third gating port 33. Wherein the second port 42, the third strobe port 33 and the peripheral interface 60 are in a physical isolation state.

L3, the main control chip 10 judges whether the peripheral interface 60 is connected with an upper computer, and the steps comprise: the peripheral interface 60 controls the detection input pin 64 to output the first level of the first detection signal when the host is connected, and controls the detection input pin 64 to output the second level of the first detection signal when the host is not connected. The external detection pin 17 switches the level of the output second detection signal to the first level when the first level of the first detection signal is received, and switches the level of the output second detection signal to the second level when the second level of the first detection signal is received. The main control chip 10 determines whether the first level of the second detection signal is queried, if yes, it indicates that the peripheral interface 60 is connected to the upper computer, and then L5 is entered, and if not, it indicates that the peripheral interface 60 is not connected to the upper computer, and then L4 is entered.

L4, normal start enters the working state of the recorder 100: the data recording device 20 encodes and stores the acquired data and the recorder 100 enters a data storage mode.

L5, according to the priority policy setting of the user, selecting to enter a data storage mode or a data export mode, including: whether the priority policy setting is the priority data storage mode S1 is determined, if yes, the process proceeds to L6, and if no, the process proceeds to L7.

L6, selecting a storage priority policy, the recorder 100 enters a data storage mode, and the main control chip 10 controls the gate switch control pin 15 to output a first level, such as a high level, of the control signal. The control signal receiving pin 34 of the gating switch 30 receives a first level of the control signal, and the gating switch 30 controls the first switch path to be turned on and the second switch path to be turned off under the control of the first level of the control signal.

For example, as shown in fig. 9b, the main control chip 10 pulls up the gate switch control pin 15, switches the gate switch 30 to the gate states of the first gate port 31 and the second gate port 32, the port controller 12 operates the driving logic, the interface converter 40 is configured to be in a data storage operation state, and the interface converter 40 converts the input USB data format into a data format corresponding to the storage 50, for example, converts the USB data format into the SDIO data format, and writes the data into the storage 50. The main control chip 10 transmits data to the memory 50 at a first speed through the gate switch 30 and the interface converter 40.

L7, selecting to derive a priority strategy, enabling the recorder to enter a data derivation mode, pulling up the power switch pin 16 by the main control chip 10, switching the peripheral interface 60 to a power-on state, enabling the peripheral interface 60 and the storage 50 to have communication capability, and entering G1-G3 or H1-H3. .

As shown in connection with fig. 10 and 11: in the second application scenario, after the recorder 100 is powered off from the mounting frame and then connected to the upper computer, the upper computer is connected to the USB2.0 for low-speed data export. The working process comprises the following steps:

g1, recorder 100 is powered off and connected with the host computer through peripheral interface 60.

G2, the host computer completes the self-adaptive detection, driving and read-write access of the interface specification and the communication protocol to the interface converter 40, thereby realizing the export operation of the USB port to the data of the recorder 100. In the adaptive detection stage, a suitable transmission link is selected according to whether the transmission port of the upper computer is an mth generation (for example, a third generation) universal serial bus port (USB 3.0 port). If yes, enter H3, if not, enter G3.

If the upper computer is provided with a USB2.0 port and is connected with the peripheral interface 60 through a data line, G3 is entered; if the host computer is provided with a USB3.0 port and is connected with the peripheral interface 60 through a data line, H3 is entered.

G3, the second transfer pin 62, and the third strobe port 33 establish an nth generation (e.g., second generation) universal serial bus data transfer link (USB 2.0 data transfer link). The host computer derives the data in the memory 50 at a first speed through the peripheral interface, the second switching path of the gating switch 30, and the first port 41 of the interface converter 40.

At this time, as shown in fig. 11, a data transmission channel is formed between the memory 50, the third port 43 and the first port of the interface converter 40, the second gate port 32 and the third gate port 33 of the gate switch, and the second transmission pin 62 of the peripheral interface 60, and a USB2.0 data transmission link is established between the second transmission pin 62 and the third gate port 33, so as to realize low-speed export of data.

Under the condition that the recorder 100 is not externally connected with electricity, the level of the control signal output by the gating switch control pin 15 is a second level, for example, a low level, the level of the gating switch control pin 15 is the same as the level of the common ground terminal, namely, a second switch path between the second gating port 32 and the third gating port 33 is conducted, and the upper computer performs read-write operation on the storage 50 through the second transmission pin 62 of the peripheral interface 60. At this time, the interface converter 40 is configured to be in a data export operating state, the interface converter 40 converts the format of the data input by the storage 50 into a USB data format, for example, converts the USB data format into an SDIO data format, and the host computer starts to execute the data export operation of the storage 50. At this time, the data export speed is the first speed, so that the compatibility of the recorder 100 provided by the invention to the USB2.0 port of the upper computer is realized.

As shown in connection with fig. 10 and 12: in the third application scenario, that is, after the recorder 100 is powered off from the mounting frame and then is connected to the upper computer, the upper computer is connected to the USB3.0 for performing a high-speed data export function. The working process comprises the following steps:

h1, recorder 100 is powered off and connected with the host computer through peripheral interface 60.

The H2, the host computer completes the adaptive detection, driving and read-write access of the interface specification and the communication protocol to the interface converter 40, thereby realizing the export operation of the USB port to the data of the recorder 100. In the adaptive detection stage, a suitable transmission link is selected according to whether the transmission port of the upper computer is an mth generation (for example, a third generation) universal serial bus port (USB 3.0 port). If yes, enter H3, if not, enter G3.

If the upper computer is provided with a USB2.0 port and is connected with the peripheral interface 60 through a data line, G3 is entered; if the upper computer has a USB3.0 port, the upper computer is connected with the peripheral interface 60 through a data line, and then H3 is entered.

mXth generation (e.g., third generation) universal serial bus data transfer link (USB 3.0 data transfer link) is established between H3, first transfer pin 61 and second port 42. The host computer exports the data in the storage 50 at a second speed through the peripheral interface 60 and the second port 42 of the interface converter 40.

At this time, as shown in fig. 12, a data transmission channel is formed between the memory 50, the third port 43 and the second port of the interface converter 40, and the second transmission pin 62 of the peripheral interface 60, and a USB3.0 data transmission link is established between the first transmission pin 61 and the second port 42, so that high-speed export of data is realized.

Under the condition that the recorder 100 is not externally connected with electricity, the upper computer performs read-write operation on the storage 50 through the first transmission pin 61 of the peripheral interface 60. At this time, the interface converter 40 is configured to be in a data export operating state, the interface converter 40 converts the format of the data input by the storage 50 into a USB data format, for example, converts the USB data format into an SDIO data format, and the host computer starts to execute the data export operation of the storage 50. At this time, the data transmission speed is the second speed, and the data high-speed export function is realized.

In yet another aspect, a computer program is provided. The computer program, when executed on a computer (e.g. a single-chip microcomputer), causes the computer to perform the data processing method as described in any of the embodiments above.

In yet another aspect, the present invention also provides a computer-readable storage medium comprising computer-executable instructions which, when executed on a computer, cause the computer to perform the data processing method according to any one of the above aspects.

In yet another aspect, a computer program product is provided that is stored on a non-transitory computer readable storage medium. The computer program product comprises computer program instructions which, when executed on a computer (e.g. a single-chip microcomputer), cause the computer to perform a data processing method as described in any of the embodiments above.

The beneficial effects of the computer readable storage medium, the computer program product and the computer program are the same as those of the data processing method described in some embodiments, and are not described here again.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A recorder, comprising: the system comprises a main control chip, a gating switch, an interface converter, a memory and a peripheral interface; wherein,

the main control chip comprises a port controller, the gating switch comprises a first gating port and a second gating port, and the interface converter comprises a first port, a second port and a third port;

The port controller of the main control chip is coupled with a first gating port of the gating switch, a second gating port of the gating switch is coupled with a first port of the interface converter, a second port of the interface converter is coupled with the peripheral interface, and a third port of the interface converter is coupled with the storage;

the port controller is configured to transmit data to the gating switch;

the gating switch is configured to conduct a first switching path between the first gating port and the second gating port;

the main control chip can transmit data to the storage at a first speed through a first switch path of the gating switch and a first port of the interface converter;

the peripheral interface is configured to be coupled to a host computer for exporting data in the storage at a second speed through the peripheral interface and a second port of the interface converter;

the second speed is greater than the first speed.

2. The recorder of claim 1, wherein the gating switch further comprises a third gating port, the third gating port coupled with the peripheral interface;

The gating switch is configured to turn on a second switching path between the second gating port and the third gating port;

the upper computer is used for exporting the data in the storage at the first speed through the peripheral interface, the second switch path of the gating switch and the first port of the interface converter.

3. The recorder according to claim 2, wherein,

the port controller is an Nth generation universal serial bus controller;

the second port is an Mth generation universal serial bus port, and the peripheral interface is an Mth generation universal serial bus interface; the data transmission speed supported by the Nth generation universal serial bus is smaller than that supported by the Mth generation universal serial bus.

4. A recorder according to claim 2 or 3, wherein the peripheral interface comprises:

the first transmission pin is coupled with the second port, and a data transmission link between the first transmission pin and the second port is an Mth generation universal serial bus data transmission link;

And the second transmission pin is coupled with the third gating port, and a data transmission link between the second transmission pin and the third gating port is an N generation universal serial bus data transmission link.

5. The recorder of claim 1, further comprising a data recording device, the master control chip further comprising: a data input port;

the data input port is configured to receive data input by a data recording device.

6. The recorder of claim 2, wherein the master control chip further comprises a gate switch control pin; the gating switch further comprises a control signal receiving pin;

the gating switch control pin is coupled with the control signal receiving pin, and is configured to output a control signal to the control signal receiving pin, wherein the control signal is used for controlling the first switch passage to be conducted or controlling the second gating switch to be conducted;

the gating switch is configured to conduct the first switching path or conduct the second switching path under control of the control signal.

7. The recorder of claim 6, wherein the main control chip further comprises a power switch pin and an external detection pin;

The peripheral interface further comprises: a power pin and a detection input pin;

the power switch pin is coupled with the power pin, the power switch pin configured to provide power to the power pin;

the external detection pin is coupled with the detection input pin; the detection input pin is configured to output a first level of a first detection signal when the peripheral interface is connected with the upper computer, and output a second level of the first detection signal when the peripheral interface is not connected with the upper computer; the external detection pin is configured to output a first level of a second detection signal when the first level of the first detection signal is received, and output a second level of the second detection signal when the second level of the first detection signal is received;

the main control chip is configured to control the gating switch control pin to output a first level of a control signal under the condition that the peripheral interface is detected to be connected to the upper computer, wherein the first level is used for controlling the first switch channel to be conducted; the main control chip is configured to control the gating switch control pin to output a second level of a control signal under the condition that the peripheral interface is not detected to be connected to the upper computer, and the second level is used for controlling the second switch channel to be conducted.

8. A recorder according to any one of claims 1 to 3, wherein the memory is a memory card; the interface converter further comprises a storage control unit; the interface converter is configured to convert the format of the data received by the first port from the main control chip into a data format suitable for the storage, store the converted data into the storage control unit, and transmit the converted data to the storage through the third port; and the interface converter is configured to convert the format of the data received from the storage by the third port into a universal serial bus format, store the converted data into the storage control unit, and transmit the converted data to the first port or the second port.

9. A data processing method, characterized in that the data processing method is applied to the recorder according to any one of the preceding claims 1 to 8, the recorder comprising: the system comprises a main control chip, a gating switch, an interface converter, a memory and a peripheral interface;

the data processing method comprises the following steps:

the main control chip judges whether the peripheral interface is connected with an upper computer or not;

If the peripheral interface is connected with the upper computer, the main control chip controls the recorder to enter a data storage mode or a data export mode; or if the peripheral interface is not connected with the upper computer, the main control chip controls the recorder to enter a data storage mode;

in the data storage mode, the main control chip controls the first switch passage of the gating switch to be conducted and configures the interface converter into a working state, and the main control chip transmits data to the storage at a first speed through the first switch passage of the gating switch and the first port of the interface converter;

in the data export mode, the upper computer is used for exporting the data in the storage at a second speed through the peripheral interface and a second port of the interface converter;

wherein the second speed is greater than the first speed.

10. The method for processing data according to claim 9, wherein,

in the data export mode, the main control chip controls the second switch path of the gating switch to be conducted, and the upper computer exports the data in the storage at the first speed through the peripheral interface, the second switch path of the gating switch and the first port of the interface converter.

11. The data processing method according to claim 10, characterized in that the data processing method further comprises: in a state that the peripheral interface is connected to the upper computer, the data processing method further comprises setting a priority strategy, wherein the priority strategy comprises the following steps:

storing a priority strategy to enable the working mode of the recorder to enter a data storage mode;

leading out a priority strategy to enable the working mode of the recorder to enter a data leading-out mode;

and judging that the peripheral interface is connected to an upper computer based on the main control chip, and controlling the recorder to enter a data storage mode or a data export mode according to a priority strategy setting result.

12. The data processing method according to claim 11, wherein the main control chip further comprises a power switch pin and an external detection pin; the peripheral interface comprises: a power pin and a detection input pin;

controlling the detection input pin to output a first level of a first detection signal under the condition that the peripheral interface is detected to be connected to the upper computer; controlling the detection input pin to output a second level of a first detection signal under the condition that the peripheral interface is not detected to be connected to the upper computer;

The external detection pin switches the level of the output second detection signal to a first level when receiving the first level of the first detection signal, and switches the level of the output second detection signal to a second level when receiving the second level of the first detection signal;

the main control chip judges whether the first level of the second detection signal is inquired, if yes, the peripheral interface is judged to be connected with the upper computer, and if not, the peripheral interface is judged to be not connected with the upper computer;

in the data export mode, the main control chip also controls the power switch pin to output a first level of a first power signal, and the power switch pin is used for receiving the first level of the first power signal and switching the level of an output second power signal into the first level.

13. The data processing method according to any one of claims 10 to 12, wherein the main control chip further comprises a gate switch control pin; the gating switch further comprises a control signal receiving pin;

in the data storage mode, the main control chip controls the first switch path of the gating switch to be conducted, and the method comprises the following steps: the main control chip controls the gating switch control pin to output a first level of a control signal; the control signal receiving pin of the gating switch is used for receiving a first level of the control signal, and the gating switch is used for controlling the first switch passage to be conducted under the control of the first level of the control signal;

In the data export mode, the main control chip controls the second switch path of the gating switch to be conducted, and the method comprises the following steps: the main control chip controls the gating switch control pin to output a second level of the control signal; the control signal receiving pin of the gating switch is used for receiving a second level of the control signal, and the gating switch is used for controlling the conduction of the second switch passage under the control of the second level of the control signal.

14. The data processing method of claim 13, wherein the peripheral interface further comprises a first transfer pin and a second transfer pin;

in the data export mode, the upper computer is used for carrying out self-adaptive detection on interface specifications and communication protocols of the interface converter;

if the transmission port of the upper computer is an Mth generation universal serial bus port, an Mth generation universal serial bus data transmission link is established between the first transmission pin and the second port; the upper computer is used for driving the interface converter and exporting the data in the storage at the second speed through the Mth generation universal serial bus data transmission link;

If the transmission port of the upper computer is an N-th generation universal serial bus port, an N-th generation universal serial bus data transmission link is established between the second transmission pin and a third gating port of the gating switch; the upper computer is used for driving the interface converter and exporting the data in the storage at the first speed through the Nth generation universal serial bus data transmission link, the second switch path and the first port of the interface converter.

15. The data processing method according to claim 10, 11, 12 or 14, characterized in that the data processing method further comprises:

after the recorder is started, the gating switch defaults to conduct a second switch path between the second gating port and a third gating port of the gating switch; the level of a second power signal output by a power pin of the peripheral interface defaults to a first level;

the main control chip controls the power switch pin to output a second level of the first power signal, and the power pin of the peripheral interface is used for receiving the second level of the first power signal and switching the first level of the output second power signal into the second level.