CN114374781A

CN114374781A - Recorder and data processing method

Info

Publication number: CN114374781A
Application number: CN202111620327.5A
Authority: CN
Inventors: 尹志新
Original assignee: Hangzhou Haikang Auto Software Co ltd
Current assignee: Hangzhou Haikang Auto Software Co ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-04-19
Anticipated expiration: 2041-12-27
Also published as: CN114374781B

Abstract

The invention provides a recorder and a data processing method, which are applied to the technical field of automobile data recorders and data storage and aim to meet the business requirement of completely exporting data of the recorder in a short time. There is provided a recorder comprising: the device comprises a main control chip, a gating switch, an interface converter, a storage and a peripheral interface. The port controller is configured to transmit data to the gate switch; the gating switch is configured to conduct a first switch path between the first gating port and the second gating port, and the main control chip can transmit data to the storage at a first speed through the first switch path of the gating switch and the first port of the interface converter. The peripheral interface is configured to couple with a host computer for exporting data in the storage at a second speed through the peripheral interface and a second port of the interface translator. The second speed is greater than the first speed.

Description

Recorder and data processing method

Technical Field

The invention relates to the technical field of data storage, in particular to a recorder and a data processing method.

Background

The video recorder system is applied to a video recorder system in a train carriage, can perform signal acquisition, analog-to-digital conversion, compression coding, file storage, high-speed export of stored files and the like of data recording equipment on video images and sound in a train, and is used for video monitoring in a train operation state.

In the temporary stop process of the train arriving at the station, the code stream data stored by the video recorder system is required to be rapidly exported to a PC (personal computer) upper computer of the stop station. In order to satisfy the requirement that the data in the video recorder system is completely exported in a short time, the data export speed of the video recorder system is required to be more than 50 MB/s.

Disclosure of Invention

The invention provides a recorder, a data processing method and a computer readable storage medium, which are used for meeting the business requirements of high-efficiency data storage by using the recorder and exporting all data of the recorder in a short time.

In one aspect, the present invention provides a recorder comprising: the device comprises a main control chip, a gating switch, an interface converter, a storage and a peripheral interface. The master control chip comprises a port controller, the gating switch comprises a first gating port and a second gating port, and the interface converter comprises a first port, a second port and a third port. The port controller of the main control chip is coupled with the first gating port of the gating switch, the second gating port of the gating switch is coupled with the first port of the interface converter, the second port of the interface converter is coupled with the peripheral interface, and the third port of the interface converter is coupled with the storage. The port controller is configured to transmit data to the gating switch; the gating switch is configured to conduct a first switch path between the first gating port and the second gating port, and the main control chip can transmit data to the storage at a first speed through the first switch path of the gating switch and the first port of the interface converter. The peripheral interface is configured to couple with a host computer for exporting data in the storage at a second speed through the peripheral interface and a second port of the interface translator. Wherein the second speed is greater than the first speed.

In some embodiments, the gating switch further comprises a third gating port, the third gating port coupled to the peripheral interface. The gating switch is configured to conduct a second switch path between the second gating port and the third gating port; the upper computer is used for exporting the data in the storage at a first speed through the peripheral interface, the second switch path of the gating switch and the first port of the interface converter.

In some embodiments, the port controller is an nth generation universal serial bus controller;

the first gating port, the second gating port, the third gating port and the first port are all Nth generation universal serial bus ports;

the second port is an Mth generation universal serial bus port, and the peripheral interface is an Mth generation universal serial bus interface; the data transmission speed supported by the Nth generation of universal serial bus is less than that supported by the Mth generation of universal serial bus;

for example, in some embodiments, the port controller is a second generation universal serial bus controller. The first gating port, the second gating port, the third gating port and the first port are all second generation universal serial bus ports. The second port is an Mth generation universal serial bus port, and the peripheral interface is an Mth generation universal serial bus interface.

In some embodiments, the peripheral interface comprises: a first transmission pin and a second transmission pin. The first transmission pin is coupled with the second port, and a data transmission link between the first transmission pin and the second port is an Mth generation universal serial bus data transmission link; and the second transmission pin is coupled with the third gated port, and a data transmission link between the second transmission pin and the third gated port is an Nth generation universal serial bus data transmission link. For example, the data transmission link between the first transmission pin and the second port is a third generation universal serial bus data transmission link, and the data transmission link between the second transmission pin and the third gating port is a second generation universal serial bus data transmission link.

In some embodiments, the main control chip further comprises: the record appearance still includes data logging equipment, and the master control chip still includes: and a data input port. The data recording device is coupled with the data input port and is configured to record audio and video data. The data input port is configured to receive data input by the data logging device. In some embodiments, the main control chip further comprises a gating switch control pin; the gating switch further comprises a control signal receiving pin. The gating switch control pin is coupled with the control signal receiving pin, and is configured to output a control signal to the control signal receiving pin, wherein the control signal is used for controlling the first switch path to be conducted and controlling the second gating switch to be conducted or controlling the second gating switch to be conducted. The gate switch is configured to conduct the first switching path or conduct the second switching path under control of the control signal.

In some embodiments, the main control chip further comprises a power switch pin and an external detection pin; the peripheral interface further includes: a power pin and a detection input pin. Wherein the power switch pin is coupled with the power pin, the power switch pin configured to provide power to the power pin. The external detection pin is coupled with the detection input pin, the detection input pin is configured to output a first level of a first detection signal when the external interface is connected to the upper computer, and output a second level of the first detection signal when the external interface is not connected to the upper computer. The external detection pin is configured to output a first level of the second detection signal when receiving a first level of the first detection signal, and to output a second level of the second detection signal when receiving a second level of the first detection signal.

In some embodiments, the main control chip is configured to control the gating switch control pin to output a first level of the control signal in case that the peripheral interface is detected to be connected to the upper computer, the first level being used for controlling the first switch path to be conducted, and the main control chip is configured to control the gating switch control pin to output a second level of the control signal in case that the peripheral interface is not detected to be connected to the upper computer, the second level being used for controlling the second switch path to be conducted.

In some embodiments, the storage is a memory card. The interface converter further comprises a storage control unit; the interface converter is configured to convert the format of the data received by the first port from the main control chip into a data format suitable for the storage, store the converted data into the storage control unit, and transmit the converted data to the storage through the third port; and the interface converter is configured to convert the format of the data received by the third port from the storage into a universal serial bus format, store the converted data in the storage control unit, and transmit the converted data to the first port or the second port.

In another aspect, the present invention further provides a data processing method applied to the recorder of any one of the above aspects. Wherein, the record appearance includes: the device comprises a main control chip, an interface converter, a storage and a peripheral interface.

The data processing method of the recorder comprises the following steps: the main control chip judges whether the peripheral interface is externally connected with the upper computer or not, and if the peripheral interface is connected with the upper computer, the main control chip controls the recorder to enter a data storage mode or a data export mode; or if the peripheral interface is not accessed to the upper computer, the main control chip controls the recorder to enter a data storage mode.

In a data storage mode, the main control chip controls the conduction of a first switch path of the gating switch and configures the interface converter to be in a working state, and the main control chip transmits data to the storage at a first speed through the first switch path of the gating switch and a first port of the interface converter; in the data export mode, the upper computer is used for exporting the data in the storage at a second speed through the peripheral interface and a second port of the interface converter; wherein the second speed is greater than the first speed.

According to the data export method provided by the invention, in the data storage mode, the recorder can acquire data and store the data into the storage. Under the data export mode, the recorder uploads the data to the upper computer at a second speed through the interface converter, and the purpose of exporting the data at a high speed is achieved.

In some embodiments, in the data export mode, the master control chip controls the second switch path of the gating switch to be conducted, and the upper computer is used for exporting the data in the storage at the first speed through the peripheral interface, the second switch path of the gating switch and the first port of the interface converter.

In some embodiments, the data processing method of the recorder further comprises: in the state that the peripheral interface is accessed to the upper computer, the data processing method further comprises the step of setting a priority strategy, wherein the priority strategy comprises the following steps: storing the precedence policy and deriving the precedence policy. The storage priority strategy enables the working mode of the recorder to enter a data storage mode; the export priority policy causes the recorder's mode of operation to enter a data export mode.

And judging whether the peripheral interface is accessed to the upper computer based on the main control chip, and controlling the recorder to enter a data storage mode or a data export mode according to a priority strategy setting result.

In some embodiments, the main control chip further comprises a power switch pin and an external detection pin. The peripheral interface further includes: a power pin and a detection input pin. Whether master control chip judges peripheral hardware interface inserts the host computer includes: the peripheral interface controls the detection input pin to output a first level of a first detection signal under the condition of being connected to the upper computer, and controls the detection input pin to output a second level of the first detection signal under the condition of not being connected to the upper computer. The external detection pin switches the level of the output second detection signal to the first level when receiving the first level of the first detection signal, and switches the level of the output second detection signal to the second level when receiving the second level of the first detection signal. The main control chip judges whether the first level of the second detection signal is inquired, if so, the peripheral interface is accessed to the upper computer, and if not, the peripheral interface is not accessed to the upper computer. In the data export mode, the main control chip also controls the power switch pin to output a first level of the first power supply signal, and the power switch pin is used for receiving the first level of the first power supply signal and switching the level of the output second power supply signal into the first level.

In some embodiments, the master control chip further comprises a gating switch control pin; the gating switch further comprises a control signal receiving pin. In the data storage mode, the main control chip controls the conduction of a first switch path of the gating switch, and the data storage mode includes: the main control chip controls the gating switch to control the pin to output a first level of the control signal. The control signal receiving pin of the gating switch is used for receiving a first level of the control signal, and the gating switch is used for controlling the first switch path to be conducted under the control of the first level of the control signal. In the data export mode, the main control chip controls the conduction of a second switch path of the gating switch, and the method includes: the main control chip controls the gating switch to control the pin to output a second level of the control signal. And the control signal receiving pin of the gating switch is used for receiving the second level of the control signal, and the gating switch is used for controlling the second switch to be conducted under the control of the second level of the control signal.

In some embodiments, the peripheral interface further comprises a first transmission pin and a second transmission pin. And in the data export mode, the upper computer is used for carrying out adaptive detection on the interface specification and the communication protocol of the interface converter. If the transmission port of the upper computer is an Mth generation (for example, a third generation) universal serial bus port, an Mth generation (for example, a third generation) universal serial bus data transmission link is established between the first transmission pin and the second port. The host computer drives the interface converter and exports the data in the storage at a second speed through an Mth generation (e.g., third generation) universal serial bus data transmission link. If the transmission port of the upper computer is an Nth generation (for example, a second generation) universal serial bus port, an Nth generation (for example, the second generation) universal serial bus data transmission link is established between the second transmission pin and the third gating port of the gating switch. The host computer drives the interface converter and exports the data in the storage at a first speed through an Nth generation (such as a second generation) universal serial bus data transmission link, a second switch path and a first port of the interface converter.

In some embodiments, the data processing method further comprises: the recorder is started, and the gating switch is used for conducting a second switch path between the second gating port and the third gating port by default; the level of a second power supply signal output by a power supply pin of the peripheral interface is defaulted to be the first level. The main control chip controls the power switch pin to output the second level of the first power supply signal, and the power supply pin is used for receiving the second level of the first power supply signal and switching the first level of the output second power supply signal into the second level. The main control chip judges whether the peripheral interface is connected to the upper computer.

In yet another aspect, a computer program is provided. When the computer program is executed on a computer, the computer program causes the computer to execute the data processing method according to any one of the above embodiments.

In yet another aspect, the present invention also provides a computer-readable storage medium comprising computer-executable instructions which, when executed on a computer, cause the computer to perform the data processing method according to any one of the above-mentioned another aspect.

In yet another aspect, a computer program product is provided that is stored on a non-transitory computer readable storage medium. The computer program product comprises computer program instructions which, when executed on a computer, cause the computer to perform the data processing method according to any of the embodiments described above.

A computer-readable storage medium, a computer program product, and a computer program are used for executing the data processing method provided above, and therefore, the beneficial effects achieved by the computer-readable storage medium can refer to the beneficial effects in the data processing method provided above, and are not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.

FIG. 1 is a diagram of the physical structure of a recorder provided in some embodiments of the related art;

FIG. 2 is a diagram of another physical configuration of a recorder provided in accordance with some embodiments of the invention;

FIG. 3 is a diagram of the physical architecture of yet another recorder provided in accordance with some embodiments of the present invention;

FIG. 4 is a diagram of a connection configuration of a peripheral interface with a second port and a third strobe port provided by some embodiments of the present invention;

FIG. 5 is a diagram of the physical architecture of a recorder with control gate switch functionality according to some embodiments of the present invention;

FIG. 6 is a diagram of the physical architecture of a recorder having current paths for the host chip and peripheral interface provided by some embodiments of the present invention;

FIG. 7 is a diagram of the logical architecture of a recorder provided in accordance with some embodiments of the present invention;

FIG. 8 is a flow chart illustrating operation of a first scenario of a recorder in accordance with some embodiments of the present invention;

FIGS. 9 a-9 b are diagrams of the operation of a recorder in a first scenario in accordance with some embodiments of the present invention;

FIG. 10 is a flow chart illustrating operation of a second scenario and a third scenario of a recorder in accordance with some embodiments of the present invention;

FIG. 11 is a diagram illustrating the operation of a recorder in a second scenario in accordance with some embodiments of the present invention;

fig. 12 is a diagram illustrating a third scenario of operation of a recorder according to some embodiments of the present invention.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As shown in fig. 1 and 2: some embodiments provide a recorder 100, for example, a video recorder 100, which can be installed on a train, a ship, or a vehicle, and is used to collect video images and sounds in the train, the ship, or the vehicle, so as to facilitate scene review in a specific occasion of a certain time period at a later time.

In some embodiments, taking the recorder 100 as a train recorder as an example, when the recorder 100 is applied to a train, it is required to rapidly export the video image and sound data stored on the recorder 100 to the upper computer of the stop within a short stop time of each arrival of the train. The train has a short time at the stop, for example, a high-speed train stops for only two minutes at a part of the stop. In a short time, it is required to export the video and audio data stored inside the recorder 100 to an upper computer, for example: the upper computer can be a computer or a mobile phone with OTG (On-The-Go) function. The data export speed of the recorder 100' is above 50 MB/s.

In some embodiments, Universal Serial Bus (USB) communication is used between the recorder 100 and the host computer. In some related art, as shown in fig. 1: the main control chip 10 of the recorder 100 adopts a second generation universal serial bus transmission controller (USB2.0 controller), the main control chip 10 stores a signal (video stream) collected by the data recording device 20 (such as a camera lens) into the storage chip 11 after analog-to-digital conversion and compression coding, when data needs to be exported, the main control chip 10 exports the data in the storage chip 11, after controlling the data transmission through the USB2.0 controller, the data is output to the peripheral interface 60, the peripheral interface 60 is connected through an upper computer, and the data is uploaded to the upper computer, wherein the peripheral interface 60 is a USB2.0 interface so as to correspond to the model of the USB2.0 controller. The main control chip 10 further includes a power module 18, and the power module 18 is coupled to the power switch pin 16 and configured to provide a power signal. The main control chip 10 can meet the service requirement of the train, but cannot meet the requirement that the data export speed of the recorder 100 is more than 50 MB/s. The third generation universal serial bus transmission controller (USB3.0 controller) can meet the requirement that the data export speed of the recorder 100 is above 50MB/s, but the main control chip 10 using the USB3.0 controller cannot meet the service requirement of the train. The data transmission speed supported by the second generation universal serial bus is less than the data transmission speed supported by the third generation universal serial bus.

In this regard, some embodiments of the present invention provide a recorder 100, as shown in fig. 2: the recorder 100 includes: a main control chip 10, a gating switch 30, an interface converter 40, a storage 50 and a peripheral interface 60. The main control chip 10 includes a port controller 12, the gate switch 30 includes a first gate port 31 and a second gate port 32, and the interface converter 40 includes a first port 41, a second port 42, and a third port 43. The port controller 12 of the main control chip 10 is coupled to the first gating port 31 of the gating switch 30, the second gating port 32 of the gating switch 30 is coupled to the first port 41 of the interface converter 40, the second port 42 of the interface converter 40 is coupled to the peripheral interface 60, and the third port 43 of the interface converter 40 is coupled to the storage 50. The port controller 12 is configured to control data transfer, transferring data to the gate switch 30. The gate switch 30 is configured to turn on a first switching path between the first gate port 31 and the second gate port 32. The main control chip 10 can transmit data to the storage 50 at a first speed through the first switching path of the gate switch 30 and the first port of the interface converter 40. The peripheral interface 60 is configured to couple with a host computer for exporting data in the storage 50 at a second speed through the peripheral interface 60 and the second port 42 of the interface converter 40. Wherein the second speed is greater than the first speed.

In the recorder 100 provided in the above embodiment of the present invention, when the gate switch 30 turns on the first switch path, the main control chip 10 can transmit data to the storage 50 at the first speed through the gate switch 30 and the interface converter 40, so as to implement a data storage function. In the case where the peripheral interface 60 is connected to the upper computer, the upper computer is configured to export the data in the storage 50 at the second speed through the peripheral interface and the second port 42 of the interface converter 40, thereby implementing the data export function. And since the first speed is greater than the second speed, i.e. the data is derived at a high speed during the derivation process, the recorder 100 is able to rapidly derive a large amount of data in a short time. In some examples, the first speed is a speed when the recorder 100 in the related art uses the USB2.0 controller and the USB2.0 interface for data storage and data export, and the second speed is a speed when the recorder 100 in the present invention uses the USB3.0 interface for data export, for example, the first speed may be 20 MB/s; the second speed may be 70 MB/s.

In some embodiments, the gate switch 30 conducts a first switch path between the first gate port 31 and the second gate port 32, for example, the first gate port 31 and the second gate port are connected through two ends of the conductive contact 3', where the connection is physical electrical contact, i.e., direct physical electrical contact, and whether the first switch path transmits data is controlled by the main control chip 10. In the data storage process, the main control chip 10 controls data to be transmitted through the first switch path. During the data export process, the first switch path of the gating switch 30 may be maintained, that is, the first gating port 31 and the second gating port are connected, the main control chip 10 controls the first switch path not to perform data transmission, and in other embodiments, during the data export process, the gating switch 30 disconnects the first switch path between the first gating port 31 and the second gating port 32.

It should be noted that the first strobe port 31, the second strobe port 32, the first port 41, the second port 42, and the third port 43 are ports disposed inside the host of the recorder 100, and the different ports are coupled by data lines for transmitting data signals inside the host of the recorder 100, for example, the main control chip 10, the strobe switch 30, the interface converter 40, and the storage 50 are modular components disposed inside the recorder 100. The peripheral interface 60 is an interface provided outside the recorder 100, and is used for connecting with an external device (for example, an upper computer), and the peripheral interface 60 is a plug-in type connector. Alternatively, the first strobe port 31, the second strobe port 32, the first port 41, the second port 42, and the third port 43 each include a plurality of pins, the plurality of pins of the different ports are coupled by wires, and the first strobe port 31, the second strobe port 32, the first port 41, the second port 42, and the third port 43 are all used for transmitting data signals. The main control chip 10, the gate switch 30, the interface converter 40, and the memory 50 are electrical components integrated on a circuit board that is fixed inside the recorder 100.

The port controller 12 includes a control logic circuit and a data output port 13, the control logic circuit is a circuit disposed inside the port controller 12 and is used for completing control and processing of data transmission, parsing and packaging of data packets, encoding and decoding of transmitted signals, and the like, the data output port 13 is an exposed interface, and the data output port 13 is a USB2.0 port. The port controller 12 and the first strobe port 31 are coupled through the data output port 13.

For example: the first gate port 31, the second gate port 32, the first port 41, the second port 42, and the third port 43 are pins, and the pins of the different ports are connected by a wire, and the wire is soldered to the pins. For example, the peripheral interface 60 is a USB type female connector, the upper computer and the like need to be configured with a male connector corresponding to the peripheral interface 60, and the connection portion of the upper computer is electrically connected with the peripheral interface in a direct-plug manner and can be plugged.

The port controller 12 in the recorder 100 provided in the above embodiment of the present invention may be an nth generation (for example, a second generation) usb controller in the related art shown in fig. 1, that is, the port controller 12 adopted by the main control chip 10 is still an existing structure, and does not need to be equipped with a new port controller 12, so that the requirement of the recorder 100 on the type selection of the main control chip 10 can be satisfied.

Illustratively, the port controller 12 is an Nth generation (e.g., second generation) universal serial bus controller. The first strobe port 31, the second strobe port 32 and the first port 41 are all nth generation (e.g., second generation) universal serial bus ports (e.g., USB2.0 ports). The second port is an mth (e.g., third generation) universal serial bus port (e.g., USB3.0 port), and the peripheral interface 60 is an mth (e.g., third generation) universal serial bus interface (e.g., USB3.0 interface). Illustratively, the USB2.0 port may be: the type-A type USB2.0 female head or type-A type USB2.0 data line pin, the Micro-B type USB2.0 female head or the Micro-B type USB2.0 data line pin. The USB3.0 port may be: type-A type USB3.0 female head or type-A type USB3.0 data line pin, Micro-B type USB3.0 female head or Micro-B type USB3.0 data line pin. The USB3.0 interface may be: a type-A type USB3.0 female head, a type-C type USB3.0 female head or a Micro-B type USB3.0 female head, etc.

Some of the benefits of the record 100 provided by some embodiments of the present invention are: on the basis of adopting the existing main control chip 10, the purposes of data storage and high-speed data export are fulfilled. Specifically, the method comprises the following steps: the present invention provides a new memory-export control logic, i.e. two data transmission links are used for data storage and export. While data export is not limited by the main control chip 10, different data export speeds and data export formats can be selected according to needs, and effective storage of data and effective export of data can be guaranteed. The peripheral interface 60 is an mth generation (for example, a third generation) universal serial bus interface, and is used in cooperation with the interface converter 40 to export data at the second speed, or the peripheral interface 60 may adopt a TTL serial port or an RS232 interface, etc. In the present invention, the port controller 12 of the main control chip 10 is not directly connected to the peripheral interface 60, and different data transmission paths are formed in the recorder 100, that is, a data transmission path from the main control chip 10 to the storage 50 through the strobe switch 30 and the interface converter 40, and another data transmission path from the storage 50 to the peripheral interface 60 through the interface converter 40, and these two data transmission paths do not affect each other under the action of the strobe switch 30, and can transmit data at different speeds, so that the type selection of the peripheral interface 60 can be independent of the type influence of the port controller 12 of the main control chip 10, and the peripheral interface 60 can be an interface with a high-speed transmission function, thereby achieving the purpose of high-speed export of data in a short time.

In some embodiments, as shown in fig. 3: the gate switch 30 further includes a third gate port 33, the third gate port 33 being coupled to the peripheral interface 60. The gate switch 30 is further configured to conduct a second switching path between the second gate port 32 and the third gate port 33, and the host computer is configured to derive the data in the storage 50 at the first speed through the peripheral interface 60, the second gate switch of the gate switch 30, and the first port of the interface converter 40.

In some embodiments, the gate switch 30 further opens the first switch path between the first gate port 31 and the second gate port 32 when the second switch path between the second gate port 32 and the third gate port 33 is opened, for example, one end of the conductive contact 3' in the gate switch 30 is coupled to the second gate port 32, and the other end is switched from the first gate port 31 to the third gate port 33, so as to open the first switch path and open the second switch path.

Illustratively, the third strobe port 33 is an Nth generation universal serial bus port (e.g., a USB2.0 port).

In the following embodiments, for convenience of describing the present solution, the nth generation usb is mainly used as the second generation usb, and the mth generation usb is mainly used as the third generation usb for exemplary description, but should not be construed as a specific limitation to the embodiments of the present application. The data transmission speed supported by the Nth generation of universal serial bus is lower than that supported by the Mth generation of universal serial bus, and the values of M and N can be determined according to the updating development of the universal serial bus technology.

The recorder 100 provided in the above embodiment of the present invention establishes the second switch path, which can be used for being compatible with the USB2.0 interface of the upper computer, so that when the upper computer has a USB3.0 port, the upper computer can read and write the storage 50 at the second speed; when the upper computer adopts an original interface (a USB2.0 interface), a data transmission link can be formed with the storage 50 through the third gating port 33, the second gating port 32 and the first port 41 in sequence, and the upper computer reads and writes the storage 50 at the first speed. In this way, the recorder 100 can upload data at the second speed, while still being compatible with existing connection devices to upload the data at the first speed.

In some embodiments, as shown in FIG. 3, peripheral interface 60 includes: a first transmission pin 61 (SSRX/TX) and a second transmission pin 62(D +/D-). The first transmission pin 61 is coupled to the second port 42, and the data transmission link between the first transmission pin 61 and the second port 42 is an mth (e.g., third) generation USB data transmission link (e.g., USB3.0 transmission data link). The second transmission pin 62 is coupled to the third strobe port 33, and the data transmission link between the second transmission pin 62 and the third strobe port 33 is an nth generation (e.g., second generation) universal serial bus data transmission link (e.g., USB2.0 transmission data link).

Illustratively, as shown in FIG. 4: peripheral interface 60 is female for type-C type USB3.0, and peripheral interface 60's first transmission pin 61 includes: a TX + pin, an RX + pin, a TX-pin and an RX-pin; the second transmission pin 62 includes: a D + pin and a D-pin. Wherein the TX + pin, RX + pin, TX-pin, RX-pin are coupled to corresponding pins of the second port 42, for example: the TX + pin of the type-C type USB3.0 female head is coupled with the RX + pin of the second port 42, the RX + pin of the type-C type USB3.0 female head is coupled with the TX + pin of the second port 42, the TX-pin of the type-C type USB3.0 female head is coupled with the RX-pin of the second port 42, and the RX-pin of the type-C type USB3.0 female head is coupled with the TX-pin of the second port 42. the D + pin of the type-C type USB3.0 female head is coupled with the D + pin of the third gating port 33, and the D-pin of the type-C type USB3.0 female head is coupled with the D-pin of the third gating port 33.

In some embodiments, as shown in fig. 5: recorder 100 further includes data recording device 20, and main control chip 10 further includes: data is input into port 14. A data logging device 20 is coupled to the data input port 14. The data recording device 20 is configured to record audio-visual data; the data input port 14 is configured to receive data input by the data recording device 20. For example: the data recording device 20 may be a microphone, and the microphone collects sound data and uploads the sound data to the main control chip 10; the data recording device 20 further includes a camera for recording video image data and uploading the video image data to the main control chip 10.

In some examples, the port controller 12 is configured to complete control of the data transfer, configuring the interface converter 40 in an operational mode. Illustratively, after the first switch path is turned on, a data link is established between the main control chip 10 and the storage 50, and the port controller 12 executes a logic drive to configure the interface converter 40 into an operating mode. The data recording device 20, such as a microphone and a camera, uploads data to the main control chip 10, the main control chip 10 receives the data, performs analog-to-digital conversion and compression coding, and then sends the data to the memory 50, the data sent by the main control chip 10 passes through the port controller 12, and the port controller 12 transmits the data to the memory 50 through the first strobe port 31, the second strobe port 32, the first port 41 and the third port 43 in sequence.

In some embodiments, as shown in fig. 5: the main control chip 10 further includes a gating switch control pin (Channel _ switch _ GPIO) 15; the gating switch 30 further includes a control signal receiving pin (GPIO) 34. The gate switch control pin 15 is coupled to the control signal receiving pin 34, and the gate switch control pin 15 is configured to output a control signal to the control signal receiving pin 34, the control signal being used to control the first switch path to be turned on and off and to control the second gate switch 32 to be turned on and off. The gate switch 30 is configured to conduct the first switching path or the second switching path under the control of a control signal.

Illustratively, the control signal receiving PIN 34 and the gating switch control PIN 15 are both general purpose input/output PINs, such as PIN PINs. The signals output from the control signal receiving pin 34 and the gate switch control pin 15 are signals having a high level and a low level, which are denoted by 1 and 0, respectively. As shown in fig. 9 b: when the signal output from the gating switch control pin 15 is at a first level, for example, a high level, the second gating port 32 is coupled to the first gating port 31 to form a first switch path. As shown in fig. 12: when the signal output from the gate switch control pin 15 is a second voltage signal, for example, a low level, the second gate port 32 is coupled to the third gate port 33.

In some embodiments, as shown in fig. 6: the main control chip 10 further includes a power switch pin (TypeC _ switch _ GPIO)16 and an external detection pin (Connect _ detect _ GPIO) 17; the peripheral interface 60 further includes: a POWER Pin (POWER)63 and a detection input pin (VBUS) 64. The power switch PIN 16 and the external detection PIN 17 are both general-purpose input/output PINs, such as PIN PINs. The signals output from the power switch pin 16 and the external detection pin 17 are signals having a high level and a low level, which are respectively denoted by 1 and 0. The power supply PIN 63 and the detection input PIN 64 are PIN PINs, and signals output from the power supply PIN 63 and the detection input PIN 64 are signals having a high level and a low level, the high level being represented by 1, and the low level being represented by 0. The high level output by the main control chip 10 and the peripheral interface 60 provided by the present invention is +3.3V or +5V, and the low level output by the main control chip is 0. The first level of the above-described pin outputs appearing below is a high level, and the second level is a low level.

The power switch pin 16 is coupled to the power pin 63, and the power switch pin 16 is configured to provide power to the power pin 63. The external detection pin 17 is coupled to the detection input pin 64, and the detection input pin 64 is configured to output a first level of a first detection signal when the external interface 60 is connected to the upper computer, and output a second level of the first detection signal when the external interface 60 is not connected to the upper computer; the external connection detection pin 17 is configured to output a first level of the second detection signal when receiving a first level of the first detection signal, and to output a second level of the second detection signal when receiving a second level of the first detection signal.

It should be noted that the level of the first detection signal output by the detection input pin 64 has two states, and different levels are output when the peripheral interface 60 is connected to the upper computer and when the peripheral interface 60 is not connected to the upper computer, respectively, where the level of the first detection signal output by the detection input pin 64 when the peripheral interface 60 is connected to the upper computer is referred to as a first level, and the level of the first detection signal output by the detection input pin 64 when the peripheral interface 60 is not connected to the upper computer is referred to as a second level. The level of the second detection signal output by the external detection pin 17 has two states, and when different levels of the first detection signal are received, different levels are output, and the level of the second detection signal output when the external detection pin 17 receives the first level of the first detection signal is referred to as a first level, and the level of the second detection signal output when the external detection pin 17 receives the second level of the first detection signal is referred to as a second level. The first level and the second level of a certain signal are only an exemplary representation of the levels.

The main control chip 10 is configured to control the control signal output by the gating switch control pin 15 to be a first level, the first level controls the first switch path to be turned on and the second switch path to be turned off when detecting that the peripheral interface is connected to the upper computer, and the main control chip 10 is configured to control the control signal output by the gating switch control pin 15 to be a second level, the second level controls the first switch path to be turned off and the second switch path to be turned on when not detecting that the peripheral interface is connected to the upper computer.

Illustratively, the peripheral interface 60 is a type-C USB3.0 female connector, a power pin 63 of the type-C USB3.0 female connector is coupled to the power switch pin 16, and the main control chip 10 supplies power to the peripheral interface 60 through the power switch pin 16.

As shown in fig. 4 and fig. 6, the VBUS pin of the type-C USB3.0 female connector can be used as a detection input pin 64 and an external power supply pin, and when the VBUS pin is used as the detection input pin 64 and the peripheral interface 60 is connected to the upper computer, the VBUS pin receives power supplied by the upper computer, so that the level of the VBUS pin changes, for example, from 0 to 1, and whether the peripheral interface is connected to the upper computer or not can be detected. In addition, when the peripheral interface 60 is connected to the upper computer, the VBUS pin serves as an external power supply pin, receives power supplied from the upper computer, and supplies power to the gate switch 30, the interface converter 40, and the storage 50, thereby implementing a power supply function in the data export mode.

The VBUS pin is coupled with the external detection pin 17, and after the upper computer is connected to the peripheral interface 60, the upper computer provides power to the VBUS pin, so that the VBUS pin outputs a first level of the first detection signal, the external detection pin 17 outputs a first level of the second detection signal when receiving the first level of the first detection signal, and the external detection pin 17 feeds back the output first level of the second detection signal to the main control chip 10. When the main control chip 10 receives the first level of the second detection signal of the external detection pin 17, it can be judged that the external interface 60 is accessed to the upper computer; when the external detection pin 17 of the main control chip 10 outputs the second level of the second detection signal, it can be determined that the host computer is not accessed in the peripheral interface 60.

In some embodiments, the storage 50 is a memory card. Illustratively, the memory card may be, for example, a cf (compact flash) card, an mmc (multimedia card) card, or an sd (secure digital) card. Illustratively, the recorder housing is provided with a memory card interface that is coupled to the third port 43 of the interface converter 40, the memory card being pluggable to facilitate data transfer and transmission.

In some embodiments, the interface converter 40 further comprises a memory control unit. As shown in fig. 6, the interface converter 40 is configured to convert the format of the data received from the main control chip 10 by the first port 41 into a data format suitable for the storage 50, store the converted data in the storage control unit, and transmit the data to the storage 50 through the third port 43; and converting the data received from the storage 50 by the third port 43 into the usb format, storing the converted data in the memory control unit, and transmitting the data to the first port 41 or the second port 42.

The third port 43 is configured as a port to which the interface converter 40 is connected with the memory card 50. For example, the memory card is an SD card, and the third port 43 is an SDIO (secure Digital Input and output) port. Wherein the interface converter 40 converts the data into a USB data format and an SDIO data format to each other.

Illustratively, the interface converter 40 is a USB-SDIO HBA (USB to SDIO Host Bus Adapter) or a USB3.0 SD Card Reader, and when the interface converter 40 is a USB Card Reader, the storage control unit includes a Card Reader control chip and a USB3.0 control chip, wherein the USB3.0 control chip is coupled to the first port 41, the second port 42 and the Card Reader control chip, the Card Reader control chip is coupled to the third port 43, and the Card Reader control chip may adopt a Card Reader controller of a USB3.0 to SD4.0 memory Card.

In some embodiments, in the data storage mode, the power output pin of the port controller 12 supplies power to the interface converter 40 through the gating switch 30, and when the first and second gating ports 31 and 32 are interrupted, the current path between the power output pin of the port controller 12 and the interface converter 40 is interrupted.

In another aspect, some embodiments of the present invention provide a data processing method, which is applied to the recorder 100 according to any one of the above aspects. Wherein, the recorder 100 includes: a main control chip 10, a gating switch 30, an interface converter 40, a storage 50 and a peripheral interface 60.

Among them, as shown in fig. 6: a data processing method of the recorder 100, comprising: the main control chip 10 judges whether the peripheral interface 60 is connected to the upper computer, if so, the main control chip 10 controls the recorder 100 to enter a data storage mode or a data export mode; if not, the main control chip 10 controls the recorder 100 to enter the data storage mode.

In the data storage mode, the main control chip 10 controls the first switch path of the gate switch 30 to be turned on and configures the interface converter 40 to be in the working state, and the main control chip 10 transmits data to the storage 50 at the first speed through the first switch path of the gate switch 30 and the first port 41 of the interface converter 40.

In the data export mode, the host computer exports data in the storage 50 at a second speed through the peripheral interface 60 and the second port 42 of the interface converter 40.

Wherein the second speed is greater than the first speed.

Illustratively, the first and second strobe ports 31 and 32 are USB2.0 ports, and the third port 43 is a USB3.0 port. In the data storage mode, the main control chip 10 controls the first switch path of the strobe switch 30 to be turned on, and transmits data to the interface converter 40 through the first strobe port 31, the second strobe port 32 and the first port 41 in sequence, the interface converter 40 configures a working state after receiving the data, and in the working state, the interface converter 40 converts the format of the data from the main control chip 10 into a data format suitable for the storage 20, stores the converted data in the storage control unit, and transmits the data to the storage 50 through the third port 43. That is, the main control chip 10 establishes a first data transmission link composed of the first gate port 31, the second gate port 32, the first port 41, the storage main control chip, and the third port 43, which is controlled by the port controller 12 of the main control chip 10, and data is transmitted at a first speed, which is a derivation speed of the USB2.0 data link, that is, a transmission speed less than 40 MB/S.

In the data export mode, the main control chip 10 detects an external host computer in the peripheral interface 60, and according to the setting, the recorder 100 enters the data export mode. At this time, the main control chip 10 does not work, the upper computer controls data export, drives the interface converter 40, converts the format of the data from the storage 50 received by the third port 43 into the universal serial bus format, stores the converted data into the storage control unit, and transmits the converted data to the second port 42. Under the condition that the interface of the upper computer is a 3.0USB interface, data of the storage 50 is led out to the upper computer after sequentially passing through the third port 43, the storage control unit, the second port 42 and the peripheral interface 60, the third port 43, the storage main control chip, the second port 42 and the peripheral interface 60 form a second data transmission link, the second data transmission link leads out the data at a second speed, and the second speed is the leading-out speed of the USB3.0 data link, namely the transmission speed is greater than 50MB/S, so that the high-speed leading-out of the data is realized.

In some embodiments, as shown in fig. 6, in the data export mode, the main control chip 10 controls the second switch path of the gate switch 30 to be turned on, and the upper computer exports the data in the storage 50 through the peripheral interface 60, the second switch path of the gate switch, and the first port 41 of the interface converter 40 at a first speed.

Illustratively, the main control chip 10 detects an external upper computer in the peripheral interface 60, and according to the setting, the recorder 100 enters a data export mode, the main control chip controls the second switch path of the gating switch 30 to be conducted, and after the second switch path is conducted, the main control chip 10 stops working. The upper computer controls data export, drives the interface converter 40, converts the format of the data received from the memory 50 by the third port 43 into a universal serial bus format, stores the converted data in the storage control unit, and transmits the data to the first port 41. Under the condition that the interface of the upper computer is a 2.0USB interface, the data of the storage 50 is sequentially led out to the upper computer after passing through the third port 43, the storage control unit, the first port 41, the second switching path of the gating switch 30 and the peripheral interface 60, the third port 43, the storage control unit, the first port 41, the second switching path of the gating switch 30 and the peripheral interface 60 form a third data transmission link, and the third data transmission link leads out the data at the first speed to realize the low-speed data leading-out.

With reference to the logic architecture diagram for data storage and derivation of a recorder shown in fig. 7, a specific process of a data processing method of the recorder is as follows:

in some embodiments, a data processing method comprises: recorder 100 is turned on and gating switch 30 by default conducts the second switching path between second gating port 32 and third gating port 33. The peripheral interface 60 further includes a power pin 63, and a level of the second power signal output by the power pin 63 of the peripheral interface 60 is a first level by default, that is, the peripheral interface 60 is electrified by default. The main control chip 10 further includes a power switch pin 16, the main control chip 10 controls the power switch pin 16 to output the second level of the first power signal, and the power pin 63 receives the second level of the first power signal and switches the first level of the output second power signal to the second level.

Illustratively, the recorder 100 is powered on, the gating switch 30 defaults to turn on the second switch path, the power switch pin 16 of the main control chip 10 outputs the first level of the first power signal, the power pin 63 of the peripheral interface 60 receives the first level of the first power signal, and the level of the second power signal output by the power pin 63 of the peripheral interface 60 defaults to the first level. A conductive data link is now formed between the peripheral interface 60 and the memory 50. After the main control chip 10 runs normally, the software logic of the main control chip 10 pulls down the power switch pin 16, that is, the power switch pin 16 outputs the second level of the first power signal, and the power pin 63 receives the second level of the first power signal and switches the first level of the output second power signal to the second level. Peripheral interface 60 is powered down, and an interrupted data link is formed between peripheral interface 60 and storage 50.

In some embodiments, the main control chip 10 further includes an external detection pin 17; the peripheral interface 60 further includes: the input pin 64 is detected. The data processing method further comprises the step that the main control chip 10 judges whether the peripheral interface 60 is connected to an upper computer or not, and the step comprises the following steps: the peripheral interface 60 controls the detection input pin 64 to output a first level of the first detection signal when the host computer is connected, and controls the detection input pin 64 to output a second level of the first detection signal when the host computer is not connected. The external connection detection pin 17 switches the level of the output second detection signal to the first level when receiving the first level of the first detection signal, and switches the level of the output second detection signal to the second level when receiving the second level of the first detection signal. The main control chip 10 determines whether the first level of the second detection signal is queried, if so, it indicates that the peripheral interface 60 is accessed to the upper computer, and if not, it indicates that the peripheral interface 60 is not accessed to the upper computer. In the data export mode, the main control chip 10 further controls the power switch pin 16 to output the first level of the first power signal, and the power pin 63 receives the first level of the power signal and switches the level of the output second power signal to the first level.

Illustratively, as shown in fig. 6, the power switch pin 16 is pulled down by the voltage under the control of the main control chip 10, the upper computer is connected to the peripheral interface 60, and the upper computer provides power to the peripheral interface 60, so that the detection input pin 64 outputs the first level of the first detection signal. The external connection detection pin 17 switches the level of the output second detection signal to the first level after receiving the first level of the first detection signal. Similarly, the upper computer is not connected to the peripheral interface 60, and no external device is powered on the peripheral interface 60, so the detection input pin 64 outputs the second level of the first detection signal. The external connection detection pin 17 switches the level of the output second detection signal to the second level after receiving the second level of the first detection signal.

In some embodiments, the data processing method of the recorder 100 further comprises: in a state where the peripheral interface 60 is connected to the upper computer, the data processing method further includes priority policy setting. In some embodiments, the priority policy setting comprises: storing the priority policy and deriving the priority policy. Wherein, the storage priority policy causes the working mode of the recorder 100 to enter a data storage mode; the export priority policy causes the recorder 100 to enter a data export mode of operation. In the process that the main control chip 10 judges whether the peripheral interface 60 is connected to the upper computer or not, and under the condition that the main control chip 10 judges that the peripheral interface 60 is connected to the upper computer, the main control chip 10 controls the recorder to enter a data storage mode or a data export mode according to the priority strategy setting result.

For example, as shown in fig. 6, when the upper computer is not connected to the peripheral interface 60, the recorder 100 enters a data storage mode when running, that is, the main control chip 10 stores the acquired data in the storage 50. When the upper computer is connected to the peripheral interface 60, the user performs a priority policy setting in the recorder 100 in advance, and stores a priority policy setting structure in the main control chip in advance, and according to the priority policy setting structure, the recorder 100 can preferentially enter a data storage mode or a data export mode, and if the priority data storage mode is set, the recorder 100 preferentially stores data acquired by the main control chip 10 in the storage 50. If the priority data export mode is set, the recorder uploads the data in the storage 50 to the upper computer preferentially.

In some embodiments, the main control chip 10 further includes a gating switch control pin 15; the gating switch 30 further includes a control signal receiving pin 34. In the data storage mode, the main control chip 10 controls the first switch path of the gating switch 30 to be turned on, and includes: the main control chip 10 controls the gating switch control pin 15 to output a first level of the control signal. The control signal receiving pin 34 of the gating switch 30 receives a first level of the control signal, and the gating switch 30 controls the first switch path to be turned on and the second switch path to be turned off under the control of the first level of the control signal.

In the data export mode, the main control chip 10 controls the second switch path of the gating switch 30 to be turned on, including: the main control chip 10 controls the gating switch control pin 15 to output the second level of the control signal. The control signal receiving pin 34 of the gating switch 30 receives the second level of the control signal, and the gating switch 30 keeps the first switch path closed and the second switch path conductive under the control of the second level of the control signal.

Illustratively, at a first level, i.e., the power-on state of the gate switch 30, the first switching path between the second gate port 32 and the first gate port 31 is autonomously opened; in the power-off state of the gate switch 30, the second switch path between the second gate port 32 and the third gate port 33 is autonomously opened.

In some embodiments, a data processing method comprises: recorder 100 is turned on and gating switch 30 by default conducts the second switching path between second gating port 32 and third gating port 33. The peripheral interface 60 further includes a power pin 63, and a level of the second power signal output from the power pin 63 of the peripheral interface 60 is a first level by default. The main control chip 10 controls the power switch pin 16 to output the second level of the first power signal, and the power pin 63 receives the second level of the first power signal and switches the first level of the output second power signal to the second level.

In some embodiments, peripheral interface 60 also includes a first transmission pin 61 and a second transmission pin 62. In the data export mode, the upper computer performs adaptive detection of the interface specification and the communication protocol for the interface converter 40.

If the transmission port of the upper computer is an mth (e.g. third generation) universal serial bus port (e.g. USB3.0 port), an mth (e.g. third generation) universal serial bus data transmission link (e.g. USB3.0 data transmission link) is established between the first transmission pin 61 and the second port 42. The upper computer drives the interface converter 40 and exports the data in the storage 50 at a second speed over an mth generation (e.g., third generation) universal serial bus data transfer link. If the transmission port of the upper computer is an nth generation (e.g., second generation) universal serial bus port (e.g., USB2.0 port), an nth generation (e.g., second generation) universal serial bus data transmission link (e.g., USB2.0 data transmission link) is established between the second transmission pin 62 and the third strobe port 33 of the strobe switch 3; the host computer drives the interface switch 40 and exports data from the storage 50 at a first rate through an nth generation (e.g., second generation) universal serial bus data transfer link, the second switch path 32, and the first port 41 of the interface switch 40.

In some specific scenes, taking the recorder 100 as a train recorder as an example, the invention has different operation processes in different scenes:

exemplarily, as shown in connection with fig. 7, 8 and 9a and 9 b: in a first application scenario, the recorder 100 is mounted on a mounting rack of a train for the storage 50 to store a scenario, and the workflow of the scenario includes:

l1, the user powers on the recorder 100 to start, and the initialization state of the recorder is as shown in fig. 9 a: the default state is designed as follows:

a. the enabled gating switch 30 defaults to a coupled state of the second gating port 32 and the third gating port 33.

b. The peripheral interface 60 is powered by default, and both the transmission link between the peripheral interface 60 and the second strobe port 32 and the transmission link between the peripheral interface 60 and the third strobe port 33 have communication capability.

After the initialization state of the recorder is finished, the operation state of the recorder is as shown in fig. 9b, and the workflow of this scenario includes:

the L2 and the main control chip 10 pull down the power switch pin 16 to power down the external interface 60, and at this time, there is no communication capability between the external interface 60 and the second strobe port 32 and between the external interface 60 and the third strobe port 33. The second port 42 and the third strobe port 33 are physically isolated from the peripheral interface 60.

L3, master control chip 10 judge whether peripheral interface 60 inserts the host computer, and this step includes: the peripheral interface 60 controls the detection input pin 64 to output a first level of the first detection signal when the host computer is connected, and controls the detection input pin 64 to output a second level of the first detection signal when the host computer is not connected. The external connection detection pin 17 switches the level of the output second detection signal to the first level when receiving the first level of the first detection signal, and switches the level of the output second detection signal to the second level when receiving the second level of the first detection signal. The main control chip 10 determines whether to query the first level of the second detection signal, if so, it indicates that the peripheral interface 60 is accessed to the upper computer, and enters L5, and if not, it indicates that the peripheral interface 60 is not accessed to the upper computer, and enters L4.

L4, normal start-up enters recorder 100 operating state: the data acquired by the data recording device 20 is encoded and stored in a file and the recorder 100 enters a data storage mode.

L5, selecting to enter data storage mode or data export mode according to user priority policy setting, comprising: it is determined whether the priority policy setting is the priority data storage mode S1, and if so, the process proceeds to L6, and if not, the process proceeds to L7.

L6, select the storage priority policy, the recorder 100 enters the data storage mode, and the main control chip 10 controls the gating switch control pin 15 to output a first level of the control signal, for example, a high level. The control signal receiving pin 34 of the gating switch 30 receives a first level of the control signal, and the gating switch 30 controls the first switch path to be turned on and the second switch path to be turned off under the control of the first level of the control signal.

For example, as shown in fig. 9b, the main control chip 10 pulls up the gate switch control pin 15, switches the gate switch 30 to the first gate port 31 and the second gate port 32, the port controller 12 runs the driving logic, the interface converter 40 is configured to be in the data storage operation state, the interface converter 40 converts the input USB data format into the data format corresponding to the storage 50, for example, converts the USB data format into the SDIO data format, and writes the data into the storage 50. The main control chip 10 transfers data to the storage 50 at a first speed through the gate switch 30 and the interface converter 40.

L7, selecting the priority strategy, the recorder enters the data export mode, the main control chip 10 pulls up the power switch pin 16, switches the peripheral interface 60 to the power-on state, at this time, the peripheral interface 60 and the memory 50 have the communication capability, and the data export mode enters G1-G3 or H1-H3. .

As shown in fig. 10 and 11: in the second application scenario, after the recorder 100 is disconnected from the mounting rack and then connected to the upper computer, the upper computer is connected to the USB2.0 to perform the low-speed data export function. The work flow comprises the following steps:

g1, recorder 100 outage, through peripheral interface 60 with the host computer connection.

G2, the upper computer completes the adaptive detection, drive and read-write access to the memory 50 of the interface specification and communication protocol to the interface converter 40, thereby realizing the export operation of the USB interface to the data of the recorder 100. In the self-adaptive detection stage, a proper transmission link is selected according to whether a transmission port of the upper computer is an Mth generation (for example, a third generation) universal serial bus port (USB3.0 port). If so, the process proceeds to H3, and if not, the process proceeds to G3.

If the upper computer is provided with a USB2.0 port and is connected with the peripheral interface 60 through a data line, the upper computer enters G3; if the upper computer is provided with a USB3.0 port and is connected with the peripheral interface 60 through a data line, the H3 is entered.

An nth generation (e.g., second generation) universal serial bus data transmission link (USB2.0 data transmission link) is established among the G3, the second transmission pin 62 and the third strobe port 33. The host computer exports the data in the memory 50 at a first speed through the peripheral interface, the second switch path of the strobe switch 30, and the first port 41 of the interface converter 40.

At this time, as shown in fig. 11, data transmission channels are formed among the memory 50, the third port 43 and the first port of the interface converter 40, the second strobe port 32 and the third strobe port 33 of the strobe switch, and the second transmission pin 62 of the peripheral interface 60, and a USB2.0 data transmission link is established between the second transmission pin 62 and the third strobe port 33, so as to implement low-speed data export.

Under the condition that the recorder 100 is not externally connected, the level of the control signal output by the gating switch control pin 15 is a second level, for example, a low level, the level of the gating switch control pin 15 is the same as the level of the common ground terminal, that is, the second switch path between the second gating port 32 and the third gating port 33 is turned on, and the upper computer performs read/write operations on the storage 50 through the second transmission pin 62 of the external interface 60. At this time, the interface converter 40 is configured to be in the data export operation state, the interface converter 40 converts the format of the data input from the storage 50 into the USB data format, for example, converts the USB data format into the SDIO data format, and the host computer starts to perform the data export operation of the storage 50. At this time, the data export speed is the first speed, and the compatibility of the recorder 100 provided by the invention to the USB2.0 port of the upper computer is realized.

As shown in fig. 10 and 12: in a third application scenario, after the recorder 100 is disconnected from the mounting rack and then connected to the upper computer, the upper computer is connected to the USB3.0 to perform a high-speed data export function. The work flow comprises the following steps:

h1 and recorder 100 are powered off and connected with the upper computer through peripheral interface 60.

H2, the upper computer completes the adaptive detection, drive and read-write access to the memory 50 of the interface specification and communication protocol to the interface converter 40, thereby realizing the export operation of the USB interface to the data of the recorder 100. In the self-adaptive detection stage, a proper transmission link is selected according to whether a transmission port of the upper computer is an Mth generation (for example, a third generation) universal serial bus port (USB3.0 port). If so, the process proceeds to H3, and if not, the process proceeds to G3.

If the upper computer is provided with a USB2.0 port and is connected with the peripheral interface 60 through a data line, the upper computer enters G3; if the host computer has a USB3.0 port and is connected to the peripheral interface 60 via a data line, the process proceeds to H3.

An mth generation (e.g., third generation) universal serial bus data transmission link (USB3.0 data transmission link) is established between H3, the first transmission pin 61, and the second port 42. The host computer exports the data in the storage 50 at a second speed through the peripheral interface 60 and the second port 42 of the interface converter 40.

At this time, as shown in fig. 12, a data transmission channel is formed among the memory 50, the third port 43 and the second port of the interface converter 40, and the second transmission pin 62 of the peripheral interface 60, and a USB3.0 data transmission link is established between the first transmission pin 61 and the second port 42, so that high-speed data export is realized.

Under the condition that the recorder 100 is not externally connected, the upper computer performs read-write operation on the storage 50 through the first transmission pin 61 of the external interface 60. At this time, the interface converter 40 is configured to be in the data export operation state, the interface converter 40 converts the format of the data input from the storage 50 into the USB data format, for example, converts the USB data format into the SDIO data format, and the upper computer starts to perform the data export operation of the storage 50. At this time, the data transmission speed is the second speed, and the function of high-speed data export is realized.

In yet another aspect, a computer program is provided. When the computer program is executed on a computer (e.g., a single chip machine), the computer program causes the computer to execute the data processing method according to any one of the above embodiments.

In yet another aspect, the present invention also provides a computer-readable storage medium comprising computer-executable instructions that, when executed on a computer, cause the computer to perform the data processing method of any of the above-mentioned another aspects.

In yet another aspect, a computer program product is provided that is stored on a non-transitory computer readable storage medium. The computer program product comprises computer program instructions which, when executed on a computer (e.g. a single-chip microcomputer), cause the computer to perform the data processing method as described in any of the above embodiments.

The beneficial effects of the above computer-readable storage medium, computer program product, and computer program are the same as the beneficial effects of the data processing method described in some embodiments, and are not described herein again.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A recorder, comprising: the system comprises a main control chip, a gating switch, an interface converter, a storage and an external interface; wherein the content of the first and second substances,

the master control chip comprises a port controller, the gating switch comprises a first gating port and a second gating port, and the interface converter comprises a first port, a second port and a third port;

the port controller of the main control chip is coupled with the first gating port of the gating switch, the second gating port of the gating switch is coupled with the first port of the interface converter, the second port of the interface converter is coupled with the peripheral interface, and the third port of the interface converter is coupled with the storage;

the port controller is configured to transmit data to the gating switch;

the gating switch is configured to conduct a first switching path between the first gating port and the second gating port;

the main control chip can transmit data to the storage at a first speed through a first switch path of the gating switch and a first port of the interface converter;

the peripheral interface is configured to couple with a host computer for exporting data in the storage at a second speed through the peripheral interface and a second port of the interface translator;

the second speed is greater than the first speed.

2. The recorder of claim 1, wherein the strobe switch further comprises a third strobe port, the third strobe port coupled with the peripheral interface;

the gating switch is configured to conduct a second switching path between the second gating port and the third gating port;

the upper computer is used for exporting the data in the storage at the first speed through the peripheral interface, the second switch path of the gating switch and the first port of the interface converter.

3. Recorder according to claim 2,

the port controller is an Nth generation universal serial bus controller;

the second port is an Mth generation universal serial bus port, and the peripheral interface is an Mth generation universal serial bus interface; the data transmission speed supported by the Nth generation of universal serial bus is lower than that supported by the Mth generation of universal serial bus.

4. The recorder according to claim 2 or 3, wherein the peripheral interface comprises:

a first transmission pin coupled to the second port, wherein a data transmission link between the first transmission pin and the second port is an Mth generation universal serial bus data transmission link;

and the second transmission pin is coupled with the third gated port, and a data transmission link between the second transmission pin and the third gated port is an Nth generation universal serial bus data transmission link.

5. The recorder of claim 1, wherein the recorder further comprises a data recording device, and the main control chip further comprises: a data input port;

the data input port is configured to receive data input by a data logging device.

6. The recorder of claim 2, wherein the master control chip further comprises a gating switch control pin; the gating switch also comprises a control signal receiving pin;

the gating switch control pin is coupled with the control signal receiving pin, and is configured to output a control signal to the control signal receiving pin, where the control signal is used to control the first switch path to be turned on or control the second gating switch to be turned on;

the gate switch is configured to conduct the first switching path or the second switching path under the control of the control signal.

7. The recorder according to claim 6, wherein the main control chip further comprises a power switch pin and an external detection pin;

the peripheral interface further comprises: a power supply pin and a detection input pin;

the power switch pin is coupled with the power pin, the power switch pin configured to provide power to the power pin;

the external detection pin is coupled with the detection input pin; the detection input pin is configured to output a first level of a first detection signal when the peripheral interface is connected to the upper computer, and output a second level of the first detection signal when the peripheral interface is not connected to the upper computer; the external detection pin is configured to output a first level of a second detection signal when receiving a first level of the first detection signal, and output a second level of the second detection signal when receiving a second level of the first detection signal;

the master control chip is configured to control the gating switch control pin to output a first level of a control signal under the condition that the peripheral interface is detected to be connected to the upper computer, wherein the first level is used for controlling the first switch path to be conducted; the master control chip is configured to control the gating switch control pin to output a second level of a control signal under the condition that the peripheral interface is not detected to be connected to the upper computer, wherein the second level is used for controlling the second switch to be conducted.

8. The recorder according to any one of claims 1 to 3, wherein the memory is a memory card; the interface converter further comprises a storage control unit; the interface converter is configured to convert the format of the data received by the first port from the main control chip into a data format suitable for the storage, store the converted data into the storage control unit, and transmit the converted data to the storage through the third port; and the interface converter is configured to convert the format of the data received by the third port from the storage into a universal serial bus format, store the converted data in the storage control unit, and transmit the converted data to the first port or the second port.

9. A data processing method applied to the recorder of any one of claims 1 to 8, the recorder comprising: the system comprises a main control chip, a gating switch, an interface converter, a storage and an external interface;

the data processing method comprises the following steps:

the main control chip judges whether the peripheral interface is connected to an upper computer or not;

if the peripheral interface is connected to an upper computer, the main control chip controls the recorder to enter a data storage mode or a data export mode; or if the peripheral interface is not accessed to the upper computer, the main control chip controls the recorder to enter a data storage mode;

in the data storage mode, the main control chip controls the conduction of the first switch path of the gating switch and configures the interface converter to be in a working state, and the main control chip transmits data to the storage at a first speed through the first switch path of the gating switch and the first port of the interface converter;

in the data export mode, the upper computer is used for exporting the data in the storage at a second speed through the peripheral interface and a second port of the interface converter;

wherein the second speed is greater than the first speed.

10. The data processing method of claim 9,

in the data export mode, the main control chip controls the conduction of the second switch path of the gating switch, and the upper computer exports the data in the storage at the first speed through the peripheral interface, the second switch path of the gating switch and the first port of the interface converter.

11. The data processing method of claim 10, further comprising: in a state where the peripheral interface is accessed to the upper computer, the data processing method further includes setting a priority policy, where the priority policy includes:

storing a priority strategy to enable the working mode of the recorder to enter a data storage mode;

exporting a priority strategy, and enabling the working mode of the recorder to enter a data export mode;

and judging that the peripheral interface is accessed to an upper computer based on the main control chip, and controlling the recorder to enter a data storage mode or a data export mode according to a priority strategy setting result.

12. The data processing method of claim 11, wherein the main control chip further comprises a power switch pin and an external detection pin; the peripheral interface includes: a power supply pin and a detection input pin;

under the condition that the peripheral interface is detected to be connected to the upper computer, controlling the detection input pin to output a first level of a first detection signal; under the condition that the peripheral interface is not detected to be connected to the upper computer, controlling the detection input pin to output a second level of a first detection signal;

the external detection pin switches the level of the output second detection signal to a first level under the condition of receiving the first level of the first detection signal, and switches the level of the output second detection signal to a second level under the condition of receiving the second level of the first detection signal;

the main control chip judges whether a first level of the second detection signal is inquired, if so, the peripheral interface is judged to be accessed to the upper computer, and if not, the peripheral interface is judged not to be accessed to the upper computer;

in the data export mode, the main control chip further controls the power switch pin to output a first level of a first power supply signal, and the power switch pin is used for receiving the first level of the first power supply signal and switching the level of an output second power supply signal to the first level.

13. The data processing method according to any one of claims 10 to 12, wherein the main control chip further comprises a gating switch control pin; the gating switch also comprises a control signal receiving pin;

in the data storage mode, the main control chip controls the conduction of a first switch path of the gating switch, and the data storage mode includes: the master control chip controls the gating switch control pin to output a first level of a control signal; the control signal receiving pin of the gating switch is used for receiving a first level of the control signal, and the gating switch is used for controlling the first switch path to be conducted under the control of the first level of the control signal;

in the data export mode, the main control chip controls the conduction of a second switch path of the gating switch, and the method includes: the master control chip controls the gating switch control pin to output a second level of the control signal; and the control signal receiving pin of the gating switch is used for receiving the second level of the control signal, and the gating switch is used for controlling the second switch to be conducted under the control of the second level of the control signal.

14. The data processing method of claim 13, wherein the peripheral interface further comprises a first transmission pin and a second transmission pin;

in the data export mode, the upper computer is used for carrying out self-adaptive detection on the interface specification and the communication protocol of the interface converter;

if the transmission port of the upper computer is an Mth generation universal serial bus port, an Mth generation universal serial bus data transmission link is established between the first transmission pin and the second port; the upper computer is used for driving the interface converter and exporting data in the storage at the second speed through the Mth generation universal serial bus data transmission link;

if the transmission port of the upper computer is an Nth generation universal serial bus port, an Nth generation universal serial bus data transmission link is established between the second transmission pin and a third gating port of the gating switch; the upper computer is used for driving the interface converter and exporting data in the storage at the first speed through the Nth generation universal serial bus data transmission link, the second switch channel and the first port of the interface converter.

15. The data processing method according to claim 10, 11, 12 or 14, characterized in that the data processing method further comprises:

after the recorder is started, the gating switch conducts a second switch path between the second gating port and the third gating port by default; the level of a second power supply signal output by a power supply pin of the peripheral interface is defaulted to be a first level;

the main control chip controls the power switch pin to output a second level of the first power supply signal, and the power pin of the peripheral interface is used for receiving the second level of the first power supply signal and switching the first level of the output second power supply signal into the second level.