CN114374391A - High-speed SAR ADC circuit - Google Patents
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- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
The invention discloses a high-speed SAR ADC circuit, which comprises: the device comprises a capacitance DAC array, a comparator, a REF circuit, a clock logic circuit and a data logic circuit, wherein the REF circuit is connected with the capacitance DAC array; the capacitor DAC array is connected with two input ends of the comparator; the comparator is connected with the clock logic circuit and the data logic circuit; the clock logic circuit outputs a comparator clock to the comparator; the data logic circuit outputs DAC control signals to the capacitor DAC array; the data logic circuit is additionally provided with an extra M-bit DFF unit on the basis of the N-bit DFF unit, and is also additionally provided with an M-bit data processing unit on the basis of the N-bit data processing unit, wherein N, M are positive integers. According to the invention, the speed and the performance of the asynchronous SAR ADC can be kept stable under PVT through the automatic regulation circuit delay and the current of the reference voltage circuit, and the power consumption is reduced.
Description
Technical Field
The invention relates to a successive approximation type (SAR) analog-to-digital converter (ADC).
Background
The successive approximation type analog-to-digital converter is widely applied due to the characteristics of low power consumption and low delay, but due to the characteristics of successive approximation, an SAR ADC with an N-bit resolution ratio needs at least N conversion cycles, so the speed is low. Although the asynchronous timing SAR ADC has improved speed, the total time of N conversion cycles in practical design varies greatly with PVT (Process, Voltage, Temperature) Corner, the speed is easily doubled at the fastest and slowest PVT Corner, and the driving capability of the delay unit and the reference level driving circuit is set at the slowest Corner in the conventional design, so that the Typical and faster reference level driving circuits are over-designed, resulting in larger power consumption of the SAR ADC.
Disclosure of Invention
The invention aims to provide a high-speed SAR ADC circuit, which can keep the speed and the performance of an asynchronous SAR ADC stable under PVT through automatically adjusting the circuit delay and the current of a reference voltage circuit, and reduce the power consumption.
The technical scheme for realizing the purpose is as follows:
a high speed SAR ADC circuit, comprising: a capacitor DAC array, a comparator, a REF circuit, a clock logic circuit and a data logic circuit,
the REF circuit is connected with the capacitance DAC array;
the capacitor DAC array is connected with two input ends of the comparator;
the comparator is connected with the clock logic circuit and the data logic circuit;
the clock logic circuit outputs a comparator clock to the comparator;
the data logic circuit outputs DAC control signals to the capacitor DAC array;
the data logic circuit is additionally provided with an additional M-bit DFF unit on the basis of the N-bit DFF unit, and is also additionally provided with an M-bit data processing unit on the basis of the N-bit data processing unit, wherein N, M are positive integers.
Preferably, each DFF unit is connected with a corresponding data processing unit;
the data logic circuit comprises a delay control module for receiving a sampling clock CKS;
the M bit output of the M bit DFF unit is connected with the input end of the delay control module;
each bit of the data processing unit is connected with the comparator;
a capacitance DAC control output CTL end of the N-bit data processing unit is connected with the capacitance DAC array;
the delay control module is respectively connected with the REF circuit and the clock logic circuit.
Preferably, the clock logic circuit comprises an inverter, a first nand gate, a second nand gate and a delay unit;
the input end of the NOT gate is connected with a sampling clock CKS;
two input ends of the first NAND gate are connected with the comparator;
the output end of the first NAND gate is connected with the N + M bit DFF unit;
the output end of the NOT gate, the output end of the first NAND gate and the common connection end of the M-bit DFF unit are connected with three input ends of the second NAND gate;
the output end of the second NAND gate is connected with the input end of the delay unit;
the output end of the delay unit is connected with the comparator;
the delay unit is connected with the delay control module.
Preferably, the sampling clock CKS is connected to the N + M-bit DFF unit through two connected not gates, and is connected to one input terminal of the and gate subordinate to the first-bit DFF unit through one not gate, and is connected to the first-bit DFF unit through the other input terminal of the and gate subordinate to the first-bit DFF unit; the output end of the AND gate subordinate to the first bit DFF unit is connected with a corresponding data processing unit;
and two input ends of the respective AND gates of the other DFF units except the first DFF unit are respectively connected with the subordinate DFF unit and the previous DFF unit, and the output ends of the respective AND gates of the other DFF units except the first DFF unit are connected with the corresponding data processing units.
Preferably, the method further comprises the following steps: a data calculation unit and an output DFF unit;
the data calculation unit is respectively connected with the delay control module, the sampling clock CKS and the N + M bit data processing unit;
the DFF unit is connected with the data calculation unit and is connected with a sampling clock CKS through a NOT gate.
Preferably, the REF circuit includes: the Current DAC and the REF buffer,
the Current DAC is connected with the delay control module and the REF buffer;
the REF buffer is connected with the capacitor DAC array.
The invention has the beneficial effects that: the invention automatically adjusts the time delay and the current of the reference level driving circuit according to different Corner where the chip is located. The extra conversion bits are inserted to detect the current state of the SAR ADC, the number of the extra conversion bits can be used as the conversion time margin, and the requirements of different systems on the error rate and robustness of the SAR ADC can be met only by adjusting the number of the conversion bits. Compared with the traditional method that the currents of the delay unit and the reference level driving circuit are set to the slowest corner, the method has the advantages that the default gear is set under the Tyfocal corner of the PVT, the time delay of the delay unit is reduced under the slowest corner to accelerate the speed, the bias Current of the reference level driving circuit is increased through the Current DAC, and the capacitor DAC establishment time in the SAR ADC is shortened; and the aim of saving power consumption is fulfilled by increasing the time delay of the time delay unit and reducing the bias Current of the reference level driving circuit through the Current DAC under the slower corner. Because the statistical proportion of the slowest PVT Corner is very small, the purpose of saving power consumption on the premise of meeting high-speed application can be effectively achieved by a method of automatically adjusting time delay and current. Finally, the invention counts the data output of the extra conversion bit, can play a role of improving the SAR ADC noise, relieves the compromise problem of the comparator in high-speed application speed and noise performance, and effectively improves the speed of the whole SAR ADC.
Drawings
FIG. 1 is a circuit diagram of a high speed SAR ADC circuit of the present invention;
FIG. 2 is a block diagram of a SAR ADC in the present invention;
FIG. 3 is a timing diagram of an exemplary 5-bit asynchronous SAR ADC according to the present invention
Fig. 4 is a flow chart of the high speed SAR ADC operation of the present invention.
Detailed Description
The invention will be further explained with reference to the drawings.
Fig. 2 is a block diagram of an SAR ADC, which mainly includes a capacitor DAC (Digital to Analog converter) array, a comparator, a REF circuit (reference level driver circuit), a clock logic circuit, and a data logic circuit. The REF circuit is connected with the capacitance DAC array; the capacitor DAC array is connected with two input ends of the comparator; the comparator is connected with the clock logic circuit and the data logic circuit; the clock logic circuit outputs a comparator clock cmp _ en to the comparator; the data logic circuit outputs a DAC control signal DAC _ CTL to the capacitor DAC array.
Fig. 3 is a timing diagram illustrating an example of a 5-bit asynchronous SAR ADC. In the sampling phase of the ADC, the sampling clock CKS is at a high level, and the capacitor DAC array samples the input signals Vin +, Vin-into the capacitor DAC array. During the transition phase, CKS is low and the clock logic generates the comparator clocks cmp _ en one by one. In the 5-bit asynchronous SAR ADC of fig. 3, cmp _ en generates 5 high levels, wherein the high level time of cmp _ en is different due to the difference in comparison time of the comparator at each time. The clock loops and data loops for bit <4>, bit <3> are illustrated in FIG. 3. Wherein a clock loop refers to the loop in fig. 2 from comparator to clock logic fed back to the comparator via the comparator clock cmp _ en; the DAC loop refers to the loop from the capacitor DAC array to the comparator to the data logic in fig. 2, and finally fed back to the capacitor DAC array by the DAC control signal DAC _ CTL. In FIG. 3, the clock loop of bit <4> starts from the bit <4> rising edge of cmp _ en, the comparator starts to compare, and the comparison result generates a cmp _ en falling edge through the logic delay of the clock logic module; the comparator starts to reset at the falling edge of cmp _ en, and after the reset is completed, the comparator passes through clock logic, the delay of the clock logic is logic delay 2 of fig. 3, the rising edge of cmp _ en is triggered, and the period of bit <3> is started. On the DAC loop, when the rising edge of bit <4> of cmp _ en means that the DAC is built completely, after the comparator result is obtained, the control signal of the DAC is changed through a data logic circuit (the delay of the control signal is 'data delay' in figure 3), and the DAC building is started, wherein the building time is 'bit-3 DAC building' in figure 3; to achieve better SAR ADC performance, the Bit-3 DAC setup is required to complete before the Bit <3> high rising edge of cmp _ en. The conversion speed of an asynchronous SAR ADC is directly dependent on the speed of the clock loop, i.e., cmp _ en is to complete a full 5 cycles. Its components include the "bit-n comparator setup", "logic delay 1", "comparator reset", "logic delay 2" of fig. 3. The delays of these 4 parts are all different under different horns.
As shown in fig. 1, the high-speed SAR ADC circuit of the present invention includes: the circuit comprises a capacitance DAC array, a comparator, a REF circuit, a clock logic circuit and a data logic circuit. In the figure, the K1 block corresponds to a clock logic circuit. The K2 plus K3 blocks correspond to data logic circuits. The K4 module corresponds to a REF circuit.
The data logic circuit is additionally provided with an additional M-bit DFF (D flip-flop) unit (corresponding to 3-bit DFFs I11-I13 in FIG. 1) on the basis of the N-bit DFF units (I6-I10), and is additionally provided with an additional M-bit data processing unit (corresponding to L7-L9 in FIG. 1) on the basis of the N-bit data processing units (L2-L6), wherein N, M are positive integers.
Each DFF unit is connected with a corresponding data processing unit. The data logic circuit includes a delay control module (delay control) L10 that receives the sampling clock CKS. The common connection end of the M-bit DFF units I11-I13 is connected with the input end of the delay control module L10. Each bit data processing unit is connected with the Q terminal and the QB terminal of the comparator Lx. DAC control terminals (CTL terminals) of the N-bit data processing units L2-L6 are connected to corresponding capacitors in the capacitor DAC array. The delay control module L10 is connected to the REF circuit and the clock logic circuit, respectively.
The clock logic circuit includes an not gate I1, a first nand gate I4, a second nand gate I2, and a delay unit (delay dac) L0. The input of the not gate I1 is terminated by the sampling clock CKS. Two input ends of the first nand gate I4 are connected to the Q terminal and the QB terminal of the comparator Lx. The output end of the first NAND gate I4 is connected with the CK end of the N + M-bit DFF unit. The output end of the NOT gate I1, the output end of the first NAND gate I4 and the common non-inverting terminal (Q terminal) of the M-bit DFF units I11-I13 are connected with three input ends of a second NAND gate I2. The output end of the second nand gate I2 is connected to the input end of the delay unit L0. The output of the delay unit L0 is connected to the comparator Lx. The delay unit L0 is connected to the delay control module L10 and receives the control signal d _ dac _ ctl.
The sampling clock CKS is connected with the rst end of each of the N + M bit DFF units through two connected NOT gates on one hand, and is connected with one input end of the AND gate subordinate to the first bit DFF unit I6 through one NOT gate on the other hand, and is connected with the Q-inverse end of the first bit DFF unit I6 through the other input end of the AND gate subordinate to the first bit DFF unit I6; the output terminal of the AND gate subordinate to the first bit DFF unit I6 is connected to the EN terminal of the corresponding data processing unit L2. Two input ends of the AND gates of the DFF units I7-I13 except the first DFF unit are respectively connected with the Q-inverse end of the slave DFF unit I7-I13 and the Q-end of the previous DFF unit I6-I12, and the output ends of the AND gates are connected with the corresponding data processing units L3-L9.
The invention also includes: a data calculation unit and an output DFF unit. The data calculation units are respectively connected to the delay control module L10, the sampling clock CKS, and the D terminals of the N + M-bit data processing units L2-L9.
The output DFF unit is connected to the data calculation unit and to the sampling clock CKS via a not gate I5.
The REF circuit includes: current DAC (Current mode digital-to-analog converter) and REF buffer (reference voltage drive circuit),
the Current DAC L11 is connected to the delay control module L10, and receives the control signal i _ DAC _ ctl to adjust the bias Current Ibias of REF buffer L12. REF buffer L12 is connected to the capacitance DAC array, providing VREF + and VREF-.
As shown in fig. 4, which is a flow chart of the high-speed SAR ADC, the present invention will be described with reference to fig. 1 and 4.
When the circuit is powered up or reset, the Delay control module L10 is in the default configuration, leaving the Delay DAC L0 and the Current DAC L11 in the default gear. In this gear, the SAR ADC can perform exactly N normal conversions (5 in fig. 1) and M-1 additional conversions (2 in fig. 1) under typical corners (PVT is all the middle gear). For a SAR ADC circuit at some unknown Corner, the circuit attempts 5 normal conversions and 3 additional conversions in the default mode. The process is as follows: after sampling is finished, the rising edge of cmp _ en triggers the comparator Lx to start comparison, when the comparison is finished, the valid signal (comparator comparison completion signal from the output end of the first NAND gate I4) in the K1 module obtains a rising edge, and triggers the corresponding DFF (I6-I13) to output Q = 1; before Q =1, LEN < n > or LREN < m > of the corresponding bit is high, the corresponding logic cell (L2-L9 in the K2 block) is made to be in the enabled state, the comparison result of the bit is stored, and the corresponding DAC switch is changed. The logic unit comprises 2 latches for latching signals of Q and QB, when an EN signal is 1, the 2 latches are respectively connected to Q, QB signals for latching, and a D end outputs a positive signal of the latch corresponding to Q; when the EN signal is 0, the latches are disconnected from Q, QB, 2 latches keep the state, and the output D also maintains the original state; the rst signal is a reset signal, and when the rst signal is at a high level, the latch is reset; DAC control signals are also contained in the L2-L6, and the DAC control signals DAC _ CTL are output through internal logic according to the result of the latch.
After trying N + M transitions, at the next rising edge of CKS, the delay control block L10 of fig. 1 counts the completion status of the additional M transitions, i.e. the delay control block L10 counts whether the Q-side output of DFF units I10, I11, I12 is 1. When Q =1 of I10 and I11 and Q =0 of Q12, the Current DAC and the delay DAC are not adjusted, and the values are converged to proper values; when Q =1 for I10, I11, Q12, indicating that the delay is too small, the Current DAC Current is reduced and the delay of the delay DAC is increased; when Q =0 for I11, indicating too large a delay, the Current DAC Current is increased and the delay of the delay DAC is decreased. The synchronous adjustment Current DAC and the delay DAC can obtain proper time delay and adjust the DAC establishment speed at the same time, and the effect of saving the power consumption of the reference level driving circuit is achieved.
And after the Current DAC and the delay DAC are adjusted, obtaining data output according to the condition that the conversion is completed. The last 1bit (LSB) of the normal transition, such as DO <0> and RDO <2:0> of FIG. 1, is counted. At the time of CKS rising edge, the L6-L9 outputs DO <0> and RDO <2:0> corresponding to Q =1 of DFF (I10-I13) are effective values, the number of 1 in the effective values is counted statistically, when the number of 1 occupies most effective values, DO1<0> =1, otherwise DO1<0> = 0. For example BEN <0> = BREN <1> =1, BREN <2> =0, the valid value is 3; when DO <0> =1, RDO <0> = RDO <1> =0, then data 1 is not greater than 3 ÷ 2=1.5, so DO1<0> =1, DO1<4:1> = DO <4:1 >. After DO1<4:0> passes through the DFF output unit, the ADC outputs DOUT <4:0>, and the SAR ADC completes the conversion. According to the logic, the last 1bit can be averaged, and the noise performance of the ADC is improved.
In summary, the present invention detects the current state of the SAR ADC by inserting additional conversion bits, and as an example, an additional 3-bit additional conversion bits are inserted in fig. 1, and the number of the conversion bits can be actually adjusted according to the requirement of the system on the SAR ADC, so as to achieve the purpose of designing the conversion time margin. When the requirement of the error rate of the system is higher, extra conversion bits more than 2 bits can be inserted to obtain larger time margin; when the system error rate requirement is low, the extra conversion bit can be reduced to 2 bits to obtain higher SAR ADC speed.
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore all equivalent technical solutions should also fall within the scope of the present invention, and should be defined by the claims.
Claims (6)
1. A high speed SAR ADC circuit, comprising: a capacitor DAC array, a comparator, a REF circuit, a clock logic circuit and a data logic circuit,
the REF circuit is connected with the capacitance DAC array;
the capacitor DAC array is connected with two input ends of the comparator;
the comparator is connected with the clock logic circuit and the data logic circuit;
the clock logic circuit outputs a comparator clock to the comparator;
the data logic circuit outputs DAC control signals to the capacitor DAC array;
the data logic circuit is additionally provided with an additional M-bit DFF unit on the basis of the N-bit DFF unit, and is also additionally provided with an M-bit data processing unit on the basis of the N-bit data processing unit, wherein N, M are positive integers.
2. The high-speed SAR ADC circuit according to claim 1, wherein each of the DFF units is connected to a corresponding data processing unit;
the data logic circuit comprises a delay control module for receiving a sampling clock CKS;
the M bit output of the M bit DFF unit is connected with the input end of the delay control module;
each bit of the data processing unit is connected with the comparator;
a capacitance DAC control output CTL end of the N-bit data processing unit is connected with the capacitance DAC array;
the delay control module is respectively connected with the REF circuit and the clock logic circuit.
3. The high-speed SAR ADC circuit of claim 2, wherein the clock logic circuit comprises a not-gate, a first nand-gate, a second nand-gate, and a delay unit;
the input end of the NOT gate is connected with a sampling clock CKS;
two input ends of the first NAND gate are connected with the comparator;
the output end of the first NAND gate is connected with the N + M bit DFF unit;
the output end of the NOT gate, the output end of the first NAND gate and the common connection end of the M-bit DFF unit are connected with three input ends of the second NAND gate;
the output end of the second NAND gate is connected with the input end of the delay unit;
the output end of the delay unit is connected with the comparator;
the delay unit is connected with the delay control module.
4. The high-speed SAR ADC circuit according to claim 2, wherein the sampling clock CKS is connected to the N + M-bit DFF unit through two connected not gates on the one hand, and connected to one input terminal of the and gate belonging to the first bit DFF unit through one not gate on the other hand, and connected to the first bit DFF unit through the other input terminal of the and gate belonging to the first bit DFF unit; the output end of the AND gate subordinate to the first bit DFF unit is connected with a corresponding data processing unit;
and two input ends of the respective AND gates of the other DFF units except the first DFF unit are respectively connected with the subordinate DFF unit and the previous DFF unit, and the output ends of the respective AND gates of the other DFF units except the first DFF unit are connected with the corresponding data processing units.
5. The high-speed SAR ADC circuit of claim 3, further comprising: a data calculation unit and an output DFF unit;
the data calculation unit is respectively connected with the delay control module, the sampling clock CKS and the N + M bit data processing unit;
the DFF unit is connected with the data calculation unit and is connected with a sampling clock CKS through a NOT gate.
6. The high-speed SAR ADC circuit of claim 3, wherein the REF circuit comprises: the Current DAC and the REF buffer,
the Current DAC is connected with the delay control module and the REF buffer;
the REF buffer is connected with the capacitor DAC array.
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| CN117614453A (en) * | 2023-12-06 | 2024-02-27 | 灿芯半导体(上海)股份有限公司 | Logic circuit applied to high-speed SAR ADC |
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