CN114360424A - Signal processing circuit, display device and signal processing method - Google Patents

Abstract

The embodiment of the application provides a signal processing circuit, a display device and a signal processing method. The signal processing circuit includes: a first switching unit and a charge sampling conversion unit; the first end and the second end of the first switch unit are respectively used for receiving a first voltage and an excitation voltage signal, and the first voltage is obtained based on charges generated by sensing a biological signal; and the charge sampling conversion unit is used for correspondingly outputting a first group of differential signals from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage when the excitation voltage signal is at a first level, and the first end and the third end of the first switch unit are connected with the second end and the fourth end. The embodiment of the application can sample twice in one excitation voltage period, so that low-frequency noise in the sampled data is reduced, the accuracy of the sampled data is improved, and power consumption or area required by a signal processing circuit is reduced by multiplexing the charge sampling conversion unit.

Description

Signal processing circuit, display device and signal processing method

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a signal processing circuit, a display device, and a signal processing method.

Background

In a display device, a signal processing circuit mainly includes a charge amplifier, an integrator, a sampling circuit, an analog-to-digital converter, and the like, and these circuits or modules are all in a single-ended output or unidirectional amplification mode. At present, a signal processing circuit only samples once in a signal of one period, so that low-frequency noise in sampling data is large, and the accuracy of the sampling data is reduced.

Meanwhile, the existing signal processing circuit needs to be realized by two sampling and holding amplifiers, but the problems of larger power consumption and larger area are often caused because the sampling capacitor and the holding capacitor need larger areas, and the circuit is not suitable for application conditions with higher requirements on the power consumption and the area.

Disclosure of Invention

The signal processing circuit, the display device and the signal processing method are provided for overcoming the defects of the prior art, and are used for solving the technical problems that the signal processing circuit only samples once in a signal of one period in the prior art, so that low-frequency noise in sampled data is high, and the accuracy of the sampled data is reduced or the power consumption and the area of the signal processing circuit are high.

In a first aspect, an embodiment of the present application provides a signal processing circuit, including: a first switching unit and a charge sampling conversion unit;

the first end and the second end of the first switch unit are respectively used for receiving a first voltage and an excitation voltage signal, and the third end and the fourth end of the first switch unit are respectively electrically connected with the reverse input end and the forward input end of the charge sampling conversion unit; the first voltage is derived based on the charge generated by sensing the bio-signal;

the charge sampling conversion unit is used for correspondingly outputting a first group of differential signals from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage when the excitation voltage signal is at a first level, and the first end and the third end of the first switch unit are connected with the second end and the fourth end; and when the excitation voltage signal is at a second level, the first end and the fourth end of the first switch unit are conducted, and the second end and the third end of the first switch unit are conducted, the second group of differential signals are correspondingly output from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage.

In one possible implementation manner, the signal processing circuit further includes:

the control unit is electrically connected with the first switch unit and used for controlling the first end and the third end of the first switch unit and the second end and the fourth end of the first switch unit to be conducted when the excitation voltage signal is at a first level; and when the excitation voltage signal is at a second level, controlling the first end and the fourth end of the first switch unit to be conducted, and controlling the second end and the third end of the first switch unit to be conducted.

In one possible implementation, the first switching unit includes a first control switch, a second control switch, a third control switch, and a fourth control switch;

the first end of the first control switch and the first end of the third control switch are jointly used as the second end of the first switch unit;

the second end of the first control switch and the second end of the second control switch are used as the third end of the first switch unit together;

the first end of the second control switch and the first end of the fourth control switch are jointly used as the first end of the first switch unit;

a second terminal of the third control switch and a second terminal of the fourth control switch are used as a fourth terminal of the first switch unit together;

the control unit is electrically connected with the control ends of the first control switch, the second control switch, the third control switch and the fourth control switch and is used for controlling the connection and disconnection of the first control switch, the second control switch, the third control switch and the fourth control switch.

In one possible implementation, a charge sampling conversion unit includes: the circuit comprises a differential charge amplifier, a first reset module and a second reset module;

the positive input end, the reverse input end, the first output end and the second output end of the differential charge amplifier are respectively used as the positive input end, the reverse input end, the first output end and the second output end of the charge sampling conversion unit;

the first end and the second end of the first reset module are respectively and electrically connected with the reverse input end and the first output end of the differential charge amplifier;

the first end and the second end of the second reset module are respectively and electrically connected with the positive input end and the second output end of the differential charge amplifier;

the first reset module comprises a first reset capacitor and a first reset switch, and a first end of the first reset capacitor and a first end of the first reset switch are jointly used as a first end of the first reset module; the second end of the first reset capacitor and the second end of the first reset switch are jointly used as the second end of the first reset module;

the second reset module comprises a second reset capacitor and a second reset switch, and the first end of the second reset capacitor and the first end of the second reset switch are jointly used as the first end of the second reset module; the second end of the second reset capacitor and the second end of the second reset switch are jointly used as the second end of the second reset module;

the control unit is electrically connected with the first reset switch and the second reset switch and is used for controlling the connection and disconnection of the first reset switch and the second reset switch.

In one possible implementation manner, the signal processing circuit further includes: denoising a capacitor;

the first end of the denoising capacitor is electrically connected with the reverse input end of the charge sampling conversion unit;

the second end of the de-noising capacitor is used for receiving the excitation voltage signal.

In one possible implementation manner, the signal processing circuit further includes: a common mode level feedback unit and an operational amplifier;

the first input end and the second input end of the common mode level feedback unit are respectively and electrically connected with the first output end and the second output end of the charge sampling conversion unit; the output end of the common mode level feedback unit is electrically connected with the input end of the operational amplifier;

a common mode level feedback unit for outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage and a gate bias voltage; the set of differential signals comprises a first set of differential signals or a second set of differential signals, and the gate bias voltage is the gate bias voltage of the switching device connected with the input end of the operational amplifier.

In one possible implementation manner, the operational amplifier is configured to output a third set of differential signals or a fourth set of differential signals from the first output terminal and the second output terminal of the operational amplifier, respectively, based on the common-mode level feedback signal; the average value of the differential signals of the third group of differential signals is a predetermined common mode voltage; the average of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

In one possible implementation, the common mode level feedback unit includes: a first common mode level feedback sub-circuit;

the first common-mode level feedback sub-circuit comprises a fifth control switch, a sixth control switch, a seventh control switch, an eighth control switch, a first capacitor and a second capacitor;

the first end of the fifth control switch, the first end of the sixth control switch and the first end of the seventh control switch are respectively used for receiving a preset common-mode voltage, a grid bias voltage and one differential signal in a group of differential signals;

the second end of the fifth control switch, the second end of the seventh control switch and the first end of the first capacitor are electrically connected; the second end of the sixth control switch, the second end of the eighth control switch and the second end of the first capacitor are electrically connected;

the first end of the second capacitor is electrically connected with the first end of the seventh control switch, and the second end of the second capacitor is electrically connected with the first end of the eighth control switch and the output end of the common-mode level feedback unit.

In one possible implementation manner, the common mode level feedback unit further includes: a second common mode level feedback sub-circuit;

the second common mode level feedback sub-circuit comprises a ninth control switch, a tenth control switch, an eleventh control switch, a twelfth control switch, a third capacitor and a fourth capacitor;

the first end of the ninth control switch, the first end of the tenth control switch and the first end of the eleventh control switch are respectively used for receiving a predetermined common mode voltage, a grid bias voltage and another differential signal in a group of differential signals;

the second end of the ninth control switch, the second end of the eleventh control switch and the first end of the fourth capacitor are electrically connected; a second end of the tenth control switch, a second end of the twelfth control switch and a second end of the fourth capacitor are electrically connected;

the first end of the third capacitor is electrically connected with the first end of the eleventh control switch, and the second end of the third capacitor is electrically connected with the first end of the twelfth control switch and the output end of the common-mode level feedback unit.

In one possible implementation manner, the signal processing circuit further includes: a signal conversion unit;

the first input end and the second input end of the signal conversion unit are respectively used for being electrically connected with the first output end and the second output end of the charge sampling conversion unit;

and the signal conversion unit is used for comparing the third group of differential signals or the fourth group of differential signals to obtain a comparison result and converting the comparison result into a digital signal.

In a second aspect, an embodiment of the present application provides a display device, including: a display panel and a signal processing circuit as in the first aspect;

the display panel comprises a plurality of touch electrodes, and the touch electrodes are electrically connected with the first ends of the first switch units.

In a third aspect, an embodiment of the present application provides a signal processing method, which is applied to the signal processing circuit of the first aspect, and includes:

in a first charge sampling conversion stage, when an excitation voltage signal is at a first level, and when the excitation voltage signal is at the first level, controlling the first end and the third end of the first switch unit and the second end and the fourth end to be conducted, so that a first group of differential signals are correspondingly output from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage;

and in a second charge sampling conversion stage, when the excitation voltage signal is at a second level, controlling the first end and the fourth end of the first switching unit and the second end and the third end to be conducted, so that a second group of differential signals are correspondingly output from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage.

In one possible implementation manner, controlling the first terminal and the third terminal of the first switching unit and the second terminal and the fourth terminal to be conducted includes:

the second control switch and the third control switch of the first switch unit are controlled to be on, and the first control switch and the fourth control switch of the first switch unit are controlled to be off;

control first end and fourth end and second end and the third end conduction of first switch cell, include:

the second control switch and the third control switch which control the first switch unit are both switched off, and the first control switch and the fourth control switch of the first switch unit are both switched on.

In one possible implementation manner, the signal processing method further includes:

outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage, and a gate bias voltage; the group of differential signals comprises a first group of differential signals or a second group of differential signals, and the grid bias voltage is the grid bias voltage of a switching device connected with the input end of the operational amplifier;

correspondingly outputting a third group of differential signals or a fourth group of differential signals from the first output end and the second output end of the operational amplifier based on the common-mode level feedback signal; the average value of the differential signals of the third group of differential signals is a predetermined common mode voltage; the average of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:

the signal processing circuit of the embodiment of the application comprises a first switch unit and a charge sampling conversion unit, wherein when an excitation voltage signal is at a first level, a first end and a third end of the first switch unit are conducted, and a second end and a fourth end of the first switch unit are conducted; when the excitation voltage signal is at the second level, the first end and the fourth end of the first switch unit are conducted, and the second end and the third end of the first switch unit are conducted. Therefore, according to the embodiment of the application, the charge sampling conversion unit can be multiplexed twice through conduction of different ends of the first switch unit, sampling can be performed twice in one excitation voltage period, two groups of differential signals are generated, subsequent processing is facilitated, low-frequency noise in sampling data is greatly reduced, accuracy of the sampling data is improved, and subsequent flexible signal processing is facilitated.

Meanwhile, the charge sampling conversion unit can be directly adopted in the embodiment of the application, so that an integrator and a sampling circuit in the structure of the existing signal processing circuit are omitted, and the power consumption or the area required by the signal processing circuit is greatly reduced.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of a signal processing circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another signal processing circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a first switching unit and a charge sampling conversion unit of a signal processing circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a touch front end applied to a signal processing circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a common mode level feedback unit of a signal processing circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an operational amplifier of a signal processing circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of an application scenario in which a signal processing circuit is applied to a touch front end according to an embodiment of the present disclosure

Fig. 8 is a flowchart of a signal processing method according to an embodiment of the present application.

Reference numerals:

1-a signal processing circuit;

10-a first switch unit, 8-a first control switch, 7-a second control switch, 6-a third control switch, 5-a fourth control switch;

20-a charge sampling conversion unit, 9-a differential charge amplifier, 21-a first reset module, 22-a second reset module, 10-a first reset capacitor, 11-a first reset switch, 12-a second reset capacitor, 13-a second reset switch and 4-a noise removal capacitor;

30-a control unit;

14-common mode level feedback unit;

141-a fifth control switch, 142-a sixth control switch, 143-a seventh control switch, 144-an eighth control switch, 145-a ninth control switch, 146-a tenth control switch, 147-an eleventh control switch, 148-a twelfth control switch;

17-signal conversion circuit, 171-analog-to-digital converter, 15-thirteenth control switch, 16-fourteenth control switch;

410-touch capacitance, 420-parasitic capacitance, 430-touch node

18-operational amplifier, 181-first current source module, 182-second current source module, 183-differential pair tube module, 184-floating current module, 185-first current mirror module and 186-second current mirror module.

Detailed Description

Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The inventor of the present application has found that, in the display device, the signal processing circuit mainly includes a charge amplifier, an integrator, a sampling circuit, an analog-to-digital converter, and the like, and these circuits or modules are all in a single-ended output or unidirectional amplification manner. When the existing signal processing circuit and the system framework thereof are adopted, the characteristic is that the analog data processing and integration are realized, the high-frequency analog-digital converter ADC is suitable for being adopted, and the source data is difficult to add digital filtering processing. Correlation double sampling was originally proposed in the field of optoelectronic correlation, but there is no mature correlation application in touch sampling systems. On the premise of the prior art, a basic correlation double-sampling specific example is realized by adopting two sampling and holding amplifiers, but because a sampling capacitor and a holding capacitor need larger areas, the matching performance of the method is better, but the power consumption and the area are larger, and the method is not suitable for application conditions with higher requirements on the power consumption and the area.

The present application provides a signal processing circuit, a display device and a signal processing method, which are intended to solve the above technical problems in the prior art.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.

The embodiment of the present application provides a signal processing circuit, and as shown in fig. 1, the signal processing circuit 1 includes: a first switching unit 10 and a charge sampling conversion unit 20.

A first end and a second end of the first switching unit 10 are respectively used for receiving a first voltage and an excitation voltage signal, and a third end and a fourth end of the first switching unit 10 are respectively electrically connected with a reverse input end and a forward input end of the charge sampling conversion unit 20; the first voltage is derived based on the charge generated by sensing the bio-signal.

The charge sampling conversion unit 20 is configured to correspondingly output a first group of differential signals from a first output end and a second output end of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage when the excitation voltage signal is at a first level, the first end and the third end of the first switching unit 10 are connected, and the second end and the fourth end of the first switching unit 10 are connected; when the excitation voltage signal is at the second level, the first terminal and the fourth terminal of the first switch unit 10 are turned on, and the second terminal and the third terminal of the first switch unit 10 are turned on, the second group of differential signals are correspondingly output from the first output terminal and the second output terminal of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the first set of differential signals comprises two differential signals; the second set of differential signals includes two differential signals. The charge sampling conversion unit 20 is based on the principle of a charge amplifier, and samples and converts the first voltage to obtain a differential signal representing the first voltage information.

Optionally, the first level of the embodiment of the present application is lower than the second level, that is, the first level is a low level, and the second level is a high level. Similarly, the first level is a high level, the second level is a low level, and the principle that the terminals of the first switch unit 10 are turned on is the same.

Alternatively, the bio-signal is a signal related to the body of the living being, and the bio-signal may be an autonomous signal that the user subconsciously controls, such as: a finger contacts the touch screen; the bio-signal may also be a signal generated by the user from a self-body function, such as: including at least one of an electrocardiogram signal, an electroencephalogram signal, an electromyogram signal, an electrooculogram signal, a electrodermal potential, or any other suitable type of bioelectric signal.

Optionally, the first voltage may be obtained by outputting the charge C received by the touch electrode of the corresponding display panel, so that the charge C is converted into a voltage signal.

According to the embodiment of the application, the charge sampling conversion unit can be multiplexed twice through the conduction of different ends of the first switch unit 10, sampling can be performed twice in one excitation voltage period, two groups of differential signals are generated, low-frequency noise in sampling data is greatly reduced, the accuracy of the sampling data is improved, and subsequent flexible signal processing is facilitated.

Meanwhile, the charge sampling conversion unit 20 can be directly adopted in the embodiment of the application, and an integrator and a sampling circuit in the structure of the existing signal processing circuit are omitted, so that the power consumption or the area required by the signal processing circuit is greatly reduced.

The embodiment of the present application is to implement the charge sampling conversion unit 20 to be twice multiplexed by different combinations of controlling the switch to be turned off and on in one period of the excitation voltage signal, and the change including but not limited to the switch combination logic control is within the scope of the present patent application.

In some embodiments, referring to fig. 2, the signal processing circuit 1 further includes: a control unit 30.

The control unit 30 is electrically connected to the first switch unit 10, and the control unit 30 is configured to control the first end and the third end of the first switch unit 10 and the second end and the fourth end of the first switch unit 10 to be conducted when the excitation voltage signal is at the first level; when the excitation voltage signal is at the second level, the first terminal and the fourth terminal of the first switch unit 10 are controlled to be conducted, and the second terminal and the third terminal are controlled to be conducted.

Alternatively, the first switch unit 10 is a combination of a plurality of control switches, and different terminals of the first switch unit 10 are turned on by controlling a form in which part of the control switches are turned off and part of the control switches are turned on, so that corresponding signals are input to the charge sampling conversion unit 20.

In some embodiments, referring to fig. 3, the first switching unit 10 includes a first control switch 8, a second control switch 7, a third control switch 6, and a fourth control switch 5.

A first terminal of the first control switch 8 and a first terminal of the third control switch 6 together serve as a second terminal of the first switching unit 10.

A second terminal of the first control switch 8 and a second terminal of the second control switch 7 are used together as a third terminal of the first switch unit 10.

A first terminal of the second control switch 7 and a first terminal of the fourth control switch 5 together serve as a first terminal of the first switching unit 10.

A second terminal of the third control switch 6 and a second terminal of the fourth control switch 5 are commonly used as a fourth terminal of the first switching unit 10.

The control unit 30 is electrically connected to the control ends of the first control switch 8, the second control switch 7, the third control switch 6 and the fourth control switch 5, and is used for controlling the on and off of the first control switch 8, the second control switch 7, the third control switch 6 and the fourth control switch 5.

Alternatively, the control unit 30 controls the conduction of the different terminals of the first switching unit 10 based on the excitation voltage signal and the sampling signal. The sampling signal is a signal that triggers the charge sampling conversion unit 20 to perform signal sampling of the first voltage.

Alternatively, the control unit 30 may be a logic control circuit that receives the excitation voltage signal and the sampling signal and outputs a control signal to each control switch of the first switching unit 10 according to the received excitation voltage signal and the sampling signal. Those skilled in the art can select the signal connected to the input terminal of the control unit 30 according to actual design, so that the control signal output by the control unit 30 satisfies the above condition.

Optionally, the control ends of the control switches appearing in the embodiment of the present application may be electrically connected to the control unit 30, and the control sequence of the control unit 30 controls the on and off of each control switch.

Alternatively, the first switching unit 10 may comprise only two control switches, and one control switch may control two paths. For example, one terminal of one control switch is electrically connected to the positive input terminal of the charge sampling conversion unit 20, and the other terminal may be electrically connected to the first terminal or the second terminal of the first switch unit 10; one terminal of a control switch is electrically connected to the inverting input terminal of the charge sampling conversion unit 20, and the other terminal may be electrically connected to the first terminal or the second terminal of the first switching unit 10.

Alternatively, referring to fig. 3, Vex represents the excitation voltage signal, High represents a High level (corresponding to the second level), and LOW represents a LOW level (corresponding to the first level). The excitation voltage signal Vex is a rectangular wave signal having high and low levels. V_OPRepresenting the signal, V, output by the first output of the charge sample conversion unit 20_ONRepresenting the signal, V, output by the second output of the charge sample conversion unit 20_OPAnd V_ONA set of differential signals is formed. When the excitation voltage signal is at a first level, the output group of differential signals is a first group of differential signals; when the excitation voltage signal is at the second level, the output group of differential signals is a second group of differential signals.

Referring to fig. 3, when the excitation voltage signal Vex is at a low level in one period, the second control switch 7 and the third control switch 6 are turned on, the first control switch 8 and the fourth control switch 5 are turned off, the excitation voltage signal Vex is connected to the positive input terminal of the charge sampling conversion unit 20, and the first voltage V is_IThe signal is connected to the inverting input of the charge sample conversion unit 20. Since the excitation voltage signal Vex is now low and connected to the positive input of the charge sampling conversion unit 20, V is generated_OPGreater than V_ONI.e., the first set of differential signal outputs.

On the contrary, when the excitation voltage signal VeWhen the x signal is at a high level in one period, the second control switch 7 and the third control switch 6 of the switching component are turned off, the first control switch 8 and the fourth control switch 5 are turned on, the excitation voltage signal Vex is connected to the inverting input terminal of the charge sampling conversion unit 20, and the first voltage V is applied_IThe signal is connected to the positive input of the charge sample conversion unit 20. Since the excitation voltage signal Vex is now high and connected to the inverting input of the charge sampling conversion unit 20, V is generated_OPLess than V_ONI.e., the second set of differential signal outputs.

In some embodiments, referring to fig. 3, the charge sampling conversion unit 20 includes: a differential charge amplifier 9, a first reset block 21 and a second reset block 22.

The positive input end, the negative input end, the first output end and the second output end of the differential charge amplifier 9 are respectively used as the positive input end, the negative input end, the first output end and the second output end of the charge sampling conversion unit 20.

The first end and the second end of the first reset module 21 are electrically connected to the inverting input terminal and the first output terminal of the differential charge amplifier 9, respectively.

The first end and the second end of the second reset module 22 are electrically connected to the positive input end and the second output end of the differential charge amplifier 9, respectively.

The first reset module 21 includes a first reset capacitor 10 and a first reset switch 11, and a first end of the first reset capacitor 10 and a first end of the first reset switch 11 are used as a first end of the first reset module 21; a second terminal of the first reset capacitor 10 and a second terminal of the first reset switch 11 are commonly used as a second terminal of the first reset module 21.

The second reset module 22 includes a second reset capacitor 12 and a second reset switch 13, and a first end of the second reset capacitor 12 and a first end of the second reset switch 13 are used as a first end of the second reset module 22; a second terminal of the second reset capacitor 12 and a second terminal of the second reset switch 13 are commonly used as a second terminal of the second reset module 22.

The control unit 30 is electrically connected to both the first reset switch 11 and the second reset switch 13, and is configured to control on and off of the first reset switch 11 and the second reset switch 13.

Alternatively, referring to fig. 3, CA denotes the sub-charge amplifier 9, Cfb1 denotes the first reset capacitor 10, Cfb2 denotes the second reset capacitor 12, reset1 denotes the first reset switch 11, and reset2 denotes the second reset switch 13.

Optionally, the first voltage V_IThe signals are respectively connected to the positive input end and the negative input end of the differential charge amplifier 9 through the fourth control switch 5 and the second control switch 7, and the positive input end and the negative input end of the differential charge amplifier 9 are further connected with the excitation voltage signal Vex through the third control switch 6 and the first control switch 8. Inverting input terminal of differential charge amplifier 9 and differential signal V_OPA capacitor Cfb1 and a reset switch reset1 are connected between the positive input end of the differential charge amplifier 9 and the differential signal V_ONBetween which is connected a capacitor Cfb2 and a reset switch reset 2. A first voltage V_IThe output section to the differential charge amplifier 9 performs a function of converting the electric charge into a voltage, and realizes generation of a detection signal.

Referring to fig. 3, when the driving voltage signal Vex is at the low level stage in one cycle, the first charge sampling process is performed, since both ends of the differential charge amplifier 9 are input with the low level of the driving voltage signal Vex, after the first reset switch 11 and the second reset switch 13 are reset, the capacitor Cfb2 acts on the forward input end and the second output end of the differential charge amplifier 9, the charge on the capacitor Cfb2 is 0 since the second reset switch 13 is turned on, and after the second reset switch 13 is turned off, the difference between the reverse input end and the forward input end of the differential charge amplifier 9 is obtained, and after the amplification by the differential charge amplifier 9, the V is obtained_OPAnd V_ONOf the signal of (1). Since the excitation voltage signal Vex is now low and connected to the positive input, V is generated_OPGreater than V_ONThe differential signal of (2). On the contrary, when the excitation voltage signal Vex is in a high level stage of one period, the second charge sampling process is performed, which is similar to the principle of the first charge sampling process. Since the excitation voltage signal Vex is now high and connectedInverting the input terminal to thereby generate V_OPLess than V_ONThe differential signal of (2).

Alternatively, referring to fig. 4, as an example, the first voltage V_IThe first end of the first switch unit 10 is electrically connected to the touch output end of the touch front end structure, which includes a touch capacitor 410, a parasitic capacitor 420 and a touch node 430. In fig. 4, Cf represents the touch capacitor 410, and Cp represents the parasitic capacitor 420. The touch panel generates a touch capacitance Cf from the touch node 430 to ground when touched by a finger, and the parasitic capacitance Cp refers to the sum of the parasitic capacitances from the touch node 430 to a signal line, such as a Gate (Gate) line or a Data (Data) line in the touch panel, and to other touch nodes because the electronic device inevitably has a parasitic capacitance Cp. In practical application, the voltage V output by the touch output terminal can be adjusted_IAs a charge C due to touch.

Alternatively, the capacitance of the touch detection is mainly the capacitance from the touch node to the ground, as shown in fig. 3 and fig. 4, that is, the capacitance of the touch detection is mainly the touch capacitance Cf, which is not large enough, if the parasitic capacitance Cp is added, the total amount of the finally detected charge C will be increased, thereby causing a touch detection error.

Based on the above analysis, in some embodiments, the signal processing circuit 1 further includes: and a denoising capacitor 4.

The first end of the denoising capacitor 4 is electrically connected with the reverse input end of the charge sampling conversion unit 20;

the second end of the de-noising capacitor 4 is used for receiving the excitation voltage signal.

Optionally, the excitation voltage Signal Vex is a variety of electrical signals input into the circuit for observing the characteristics of a circuit system, and the excitation voltage Signal Vex is also called a Guard Signal (Guard Signal), which can effectively eliminate the negative influence on the touch capacitance caused by the parasitic capacitance.

Referring to fig. 3, ccanchor represents the noise removal capacitor 4, vcanchor represents the voltage signal received at the second end of the noise removal capacitor 4, and vcanchor may be the excitation voltage signal Vex.

The embodiment of the present application sets the excitation voltage signal V of the de-noising capacitor 4 (i.e., the capacitor Ccancle)_EXAnd the influence on the size of the touch capacitor Cf caused by the parasitic capacitor Cp can be effectively eliminated, so that the touch detection error is reduced.

The first reset capacitor 10, the second reset capacitor 12 and the denoising capacitor 4 in the embodiment of the application can be adjusted in size, so that when the capacitance value is correspondingly changed, the output voltage amplitude of the charge sampling conversion unit 20 is correspondingly changed, and the output signals of the charge sampling conversion unit 20 and the signal processing circuit are dynamically adjustable.

In some embodiments, as shown in fig. 5 and 6 in combination, the signal processing circuit 1 further includes: a common mode level feedback unit 14 and an operational amplifier 18.

A first input end and a second input end of the common mode level feedback unit 14 are electrically connected to a first output end and a second output end of the charge sampling conversion unit 20, respectively; the output of the common mode level feedback unit 14 is electrically connected to the input of the operational amplifier 18.

A common mode level feedback unit 14 for outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage and a gate bias voltage; the set of differential signals includes a first set of differential signals or a second set of differential signals, and the gate bias voltage is a gate bias voltage of a switching device connected to the input terminal of the operational amplifier 18.

In some embodiments, referring to fig. 5, the common mode level feedback unit 14 includes: a first common mode level feedback sub-circuit.

The first common mode level feedback sub-circuit includes a fifth control switch 141, a sixth control switch 142, a seventh control switch 143, an eighth control switch 144, a first capacitor and a second capacitor.

The first terminal of the fifth control switch 141, the first terminal of the sixth control switch 142, and the first terminal of the seventh control switch 143 are respectively configured to receive a predetermined common mode voltage, a gate bias voltage, and one differential signal of a set of differential signals.

A second end of the fifth control switch 141 and a second end of the seventh control switch 143 are electrically connected to the first end of the first capacitor; a second terminal of the sixth control switch 142, a second terminal of the eighth control switch 144 and a second terminal of the first capacitor are electrically connected.

A first end of the second capacitor is electrically connected to the first end of the seventh control switch 143, and a second end of the second capacitor is electrically connected to the first end of the eighth control switch 144 and the output end of the common mode level feedback unit 14.

Optionally, the predetermined common mode voltage is an input common mode level of the subsequent analog-to-digital converter ADC.

In some embodiments, referring to fig. 5, the common mode level feedback unit 14 further includes: a second common mode level feedback sub-circuit.

The second common mode level feedback sub-circuit comprises a ninth control switch 145, a tenth control switch 146, an eleventh control switch 147, a twelfth control switch 148, a third capacitor and a fourth capacitor.

A first terminal of the ninth control switch 145, a first terminal of the tenth control switch 146, and a first terminal of the eleventh control switch 147 are respectively configured to receive a predetermined common mode voltage, a gate bias voltage, and another differential signal of the set of differential signals.

A second end of the ninth control switch 145 and a second end of the eleventh control switch 147 are electrically connected to a first end of the fourth capacitor; a second terminal of the tenth control switch 146, a second terminal of the twelfth control switch 148 and a second terminal of the fourth capacitor are electrically connected.

A first end of the third capacitor is electrically connected to the first end of the eleventh control switch 147, and a second end of the third capacitor is electrically connected to the first end of the twelfth control switch 148 and the output end of the common mode level feedback unit 14.

Alternatively, referring to fig. 5, VCM represents a predetermined common mode voltage, VBN1 represents a gate bias voltage, VOP1 (i.e., one differential signal corresponding to the output of the differential charge amplifier 9) represents one differential signal of a set of differential signals, VON1 represents one differential signal of a set of differential signals (i.e., the other differential signal corresponding to the output of the differential charge amplifier 9), and VCMFB represents a common mode level feedback signal. The capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 are respectively a first capacitor, a second capacitor, a third capacitor and a fourth capacitor.

Alternatively, as shown in fig. 5, VOPs 1 and VON1 are connected to the output signal VCMFB through symmetrical capacitances as input signals of the common mode level feedback unit 14. VCM is the input common mode level of the subsequent ADC, i.e. the predetermined common mode voltage in the embodiment of the present application. VBN1 is a gate bias voltage (corresponding to the bias voltage of the gates of MN7 and MN8 in fig. 7), and all voltage signal terminals and capacitors are connected through a sixth control switch 142, a seventh control switch 143, an eighth control switch 144, a ninth control switch 145, a tenth control switch 146, an eleventh control switch 147 and a twelfth control switch 148. In that

In phase, i.e. the fifth control switch 141 and the sixth control switch 142 are turned on, the ninth control switch 145 and the tenth control switch 146 are turned on, the lower plates of the two capacitors C1 and C4 are charged to the VBN1 original bias voltage potential, the upper plates of the two capacitors C1 and C4 are charged to the desired VCM common mode level potential, and the VCM and bias voltage nodes are connected together in this phase. In that

In the phase, i.e. the seventh control switch 143 and the eighth control switch 144 are turned on, the eleventh control switch 147 and the twelfth control switch 148 are turned on, the capacitor C1 is connected in parallel with the capacitor C2, and the capacitor C3 is connected in parallel with the capacitor C4, since the voltage on the capacitor cannot change suddenly, the voltage on the capacitor is substantially unchanged if the phase period is small enough. Therefore VBN1 is transmitted to VCMFB, VOP1 and VON2 connect their common mode potential to VCM through charged capacitor C1 and capacitor C4, resulting in common mode level feedback signal VCMFB, which is output to the input of operational amplifier 18.

Those skilled in the art should appreciate that other techniques similar to the common mode level feedback unit 14 of the embodiments of the present application or other techniques similar to the principles of this patent may be implemented differently and still fall within the scope of the present patent.

In some embodiments, referring to fig. 6, the operational amplifier 18 is configured to output a third set of differential signals or a fourth set of differential signals from the first output terminal and the second output terminal of the operational amplifier 18, respectively, based on the common mode level feedback signal; the average value of the differential signals of the third group of differential signals is a predetermined common mode voltage; the average of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

Alternatively, referring to fig. 6, the first current source module 181 and the second current source module 182 are a P-type current source and an N-type current source, respectively, and the first current source module 181 and the second current source module 182 may be in the form of Cascode-structured amplifiers, which provide current to the differential pair transistor module 183. The first current source module 181 is formed by connecting two PMOS transistors of MP3 and MP4 in series, and the second current source module 182 is formed by connecting two NMOS transistors of MN3 and MN4 in series to form a differential pair transistor module 183, which includes MP1, MN1, MP2, and MN 2. The MP1 and MP2 are coupled to the first current source module 181 at the source terminals, and the MN1 and MN2 are coupled to the second current source module 82 at the source terminals, and when the input voltages INN and INP are both low, the PMOS differential pair transistor is on, and the NMOS differential pair transistor is off or weakly on. When the input voltages INN and INP are both high, the NMOS differential pair transistors are turned on, and the PMOS differential pair transistors are turned off or weakly turned on. The first current mirror module 185 and the second current mirror module 186 are Cascode current mirrors of P-type and N-type Cascode amplifiers, respectively, and are used as loads of the folded Cascode differential pair transistors. The floating current module 184 is a floating current part, and the basic charge amplifier structure of the embodiment of the present application has an N-type and a P-type input differential pair transistor, so the common mode range of the input signal is very large and can be from the ground to the power supply.

Alternatively, referring to fig. 6, the operational amplifier 18 according to the embodiment of the present application is a basic example of a rail-to-rail operational amplifier, and the first current source module 181 and the first current mirror module 185 are cascode current mirrors formed by PMOS to provide current loads. The second current source block 182 and the second current mirror block 186 are cascode current mirrors formed of NMOS and provide current loads. The gate terminal voltages of MP3 and MP4 are bias voltages VBP1 and VBP2, the gate terminals of MP5 and MP6 share the same gate, the gate terminal voltages are bias voltages VBP3, the gate terminals of MP7 and MP8 share the same gate, and the gate terminal voltages are bias voltages VBP 4. The gate terminal voltages of MN3 and MN4 are bias voltages VBN2 and VBN1, the gate terminals of MN5 and MN6 share the gate, the gate terminal voltages are bias voltages VBN3, the gate terminals of MN7 and MN8 share the gate, and the gate terminal voltages are bias voltages VBN 4. The differential pair transistor module 183 is composed of two pairs of input pair transistors, MN1, MN2, MP1, and MP2, and their gate input voltages are INP, INN, INP and INN, respectively. MN1, MN2 common source, and the source signal nvg is connected to the second current source module 182. MP1, MP2 common source, the source signal pvg is connected to the first current source module 181. The drain terminal voltages p12 and p11 of MN1 and MN2 are respectively connected to the drain terminals of MP6 and MP 5. Drain terminal voltages n12 and n11 of the MP1 and MP2 are respectively connected to drain terminals of MN8 and MN 7. A floating current module 184 is added between the first current mirror module 185 and the second current mirror module 186, a floating current is formed by MP9, MN9, MP10 and MN10, and the current is determined by the bias voltage input from the gate terminal. pmg and nmg are respectively connected to the drain terminals of MP7 and MN5, and pog and nog are respectively connected to the drain terminals of MP8 and MN 6. The gate terminals of the NMOS current mirror primary mirrors MN7 and MN8 in the second current mirror module 186 are used together as the input terminal of the operational amplifier 18 to receive the common mode level feedback signal VCMFB.

Alternatively, based on the circuit configurations shown in fig. 5 and 6, the differential charge amplifier 9 adjusts the first and second sets of differential signals (corresponding to VON1 and VOP1) based on the predetermined common mode level VCM, and then outputs the third and fourth sets of differential signals (corresponding to VON2 and VOP2) for subsequent processing. The average value of the differential signals of the third set of differential signals is a predetermined common-mode voltage VCM; the average of the differential signals of the fourth set of differential signals is a predetermined common-mode voltage VCM.

Alternatively, the operational amplifier 18 may be located within the charge sampling conversion unit 20.

In some embodiments, the signal processing circuit 1 further includes: a signal conversion unit 17.

The first input end and the second input end of the signal conversion unit 17 are respectively used for being electrically connected with the first output end and the second output end of the charge sampling conversion unit 20.

And the signal conversion unit 17 is configured to compare the third group of differential signals or the fourth group of differential signals to obtain a comparison result, and convert the comparison result into a digital signal.

Optionally, the signal conversion unit 17 includes: a comparator and a converter.

The first input terminal and the second input terminal of the comparator are respectively used as the first input terminal and the second input terminal of the signal conversion circuit 17.

The output end of the comparator is electrically connected with the input end of the converter.

And the comparator is used for comparing the first group of differential signals or the second group of differential signals to obtain a comparison result and outputting the comparison result to the converter.

And the converter is used for converting the comparison result into a digital signal.

Consider that prior art signal processing circuits are single-ended output, or unidirectional amplification. When the existing signal processing circuit and the system framework thereof are adopted, the characteristics are that the analog data processing and integration are realized, the high-frequency analog-to-digital converter is suitable for being adopted, and the source data is difficult to add digital filtering processing.

Based on the above problems in the prior art, the signal processing circuit of the present application performs sampling twice in one excitation voltage period through the charge sampling conversion unit 20, obtains two sets of sampling data after the analog-to-digital converter, and further filters, integrates and processes source data through the digital circuit, so as to effectively reduce the influence of middle and low frequency noise on the sampling data.

When this application embodiment adopted digital filtering, single analog-to-digital converter's area can be done littleer to the source data that analog-to-digital converter produced can be very easy carry out algorithm processing through digital filtering, and the data application that comes out like this gets up the flexibility higher, and the mistake that data took place the deviation can obviously be reduced, and it is not high to adopt digital filtering can be fine to use and require the analog-to-digital converter speed to expect much, but needs the area little, the more nimble signal processing circuit of data.

The signal processing circuit of the embodiment of the application can dynamically adjust the input voltage range, so that the signal processing circuit is greatly helpful to the performance of the analog-to-digital converter. When the performance of the analog-to-digital converter is deteriorated under some extreme conditions, the amplitude of the input voltage range of the analog-to-digital converter is reduced, and the actual conversion effective digit of the analog-to-digital converter can be effectively improved. Moreover, the application of the double-sampling concept of realizing two-time sampling in one excitation voltage period in the field of touch sampling can effectively filter the low-and-medium-frequency noise, and improve the anti-noise performance, stability, sensitivity and accuracy of the whole chip.

Alternatively, the functions of the comparator and the converter may be obtained by the design of the analog-to-digital converter ADC.

Optionally, the digital front end unit comprises a converter having a function of converting the comparison result into a digital signal. The converter is located within the digital front end unit. The comparison result output by the comparator is directly output to the digital front end unit, and the digital front end unit carries out bit number conversion. The Digital Front End unit may employ a Digital Front End module (DFE).

Optionally, in the signal conversion circuit of the embodiment of the present application, at the analog end, after the input signal passes through the charge conversion circuit, the input signal is directly connected to the analog-to-digital converter ADC for analog-to-digital conversion without passing through the function INT, and the converted digital signal is sent to the digital front-end module DFE portion for digital integration and integration. The signal conversion circuit of the embodiment of the application is based on digital signal processing and integration, is easier to perform digital filtering processing on source data, is suitable for being realized by adopting a medium-frequency analog-to-digital converter (ADC), and has the defect that the number of interactive signals between analog and digital is too large.

Optionally, the two groups of differential signals of the embodiment of the application are processed by the analog-to-digital converter to obtain two groups of sampling data, and the influence of the middle-low frequency noise on the sampling data can be effectively reduced by further noise filtering, integration and processing of the source data by the digital circuit.

Those skilled in the art will understand that: the embodiment of the application can realize twice sampling in one period, so that two groups of data signals are obtained after the analog-to-digital converter, and the digital noise filtering mode which can be used can be very flexible. If an integral algorithm is adopted, averaging, weighted averaging, integration after weighting and the like are adopted, and methods such as high-pass filtering, low-pass filtering and the like can be adopted according to actual requirements, the embodiment of the application can effectively reduce noise influence and improve the signal-to-noise ratio.

In some embodiments, the converter includes a plurality of digital signal outputs.

And the converter is used for converting the comparison result into a plurality of parallel digital signals with designed digit and outputting the plurality of digital signals in a one-to-one correspondence mode through a plurality of digital signal output ends.

Optionally, since the signal processing circuit 1 of the present application does not perform the integration process, n Analog to Digital converters (ADCs) are used for the n touch nodes. Referring to fig. 7, each ADC has a plurality of digital signal outputs, each ADC outputs 10 bits of data, and the total number of interaction signals becomes 10 × n, which may result in excessive interaction ports between digital and analog circuits. The output of each converter becomes serial data, i.e. there are only 1 output signal per converter. The comparator output (i.e. serial data) can be directly input into the digital front-end unit, and the serial data can be converted into parallel data with 10 bit number in the digital front-end unit, so that the digital signals of n D [9:0] can be reduced into digital signals of n D [0], and the number of the interactive signals is reduced by 10 times.

Optionally, digital filtering modes, such as integration in a figure, or averaging, weighted re-integration, and the like, can be freely selected by the analog-to-digital converter in the digital front-end unit, and the digital data generated by the analog-to-digital converter can be very easily processed by an algorithm through digital filtering, so that the flexibility of the data application is higher, and error tolerance and correction of the data, that is, errors of data deviation, can be significantly reduced.

Alternatively, referring to fig. 7, an application scenario of the signal processing circuit 1 and a specific structure of the signal processing circuit 1 are shown. The signal processing circuit 1 includes a first switching unit 10, a charge sampling conversion unit 20, a common mode level feedback unit 14, and a signal conversion circuit 17, which are electrically connected in sequence. In fig. 7, CMFB denotes the common mode level feedback unit 14, ADC denotes the analog-to-digital converter 171, and the signal conversion circuit 17 includes the analog-to-digital converter 171. The operational amplifier 18 is not shown, and may be located in the differential charge amplifier 9 of the charge sampling conversion unit 20, the first set of differential signals or the second set of differential signals output by the differential charge amplifier 9 are input to the common mode level feedback unit 14, the output end of the common mode level feedback unit 14 is electrically connected to the input end of the operational amplifier 18 in the charge sampling conversion unit 20, the common mode level feedback signal VCMFB is output to the operational amplifier 18, the third set of differential signals or the fourth set of differential signals generated by the operational amplifier 18 are output from the first output end and the second output end of the charge sampling conversion unit 20, the first output end and the second output end of the operational amplifier 18 correspond to the first output end of the charge sampling conversion unit 20, the second output terminal may be electrically connected to the first output terminal and the second output terminal of the differential charge amplifier 9.

Optionally, referring to fig. 7, circuit structures of the first switching unit 10 and the charge sampling conversion unit 20 are the same as the circuit structure shown in fig. 3, the common mode level feedback unit 14 shown in fig. 5 may be selected as the common mode level feedback unit 14 in fig. 7, the operational amplifier 18 is not shown, and the operational amplifier 18 structure described in fig. 6 may be adopted, which is not described again.

Alternatively, referring to fig. 7, the signal conversion circuit 17 includes an analog-to-digital converter 171, a thirteenth control switch 15, and a fourteenth control switch 16, where a first end of the thirteenth control switch 15 and a first end of the fourteenth control switch 16 are electrically connected to the second output end and the first output end of the charge sampling conversion unit 20, respectively (i.e., electrically connected to the second output end and the first output end of the operational amplifier 18, respectively), a second end of the thirteenth control switch 15 and a second end of the fourteenth control switch 16 are electrically connected to the first input end and the second input end of the analog-to-digital converter, respectively, and a first input end (positive input end) and a second input end (negative input end) of the analog-to-digital converter are respectively used as the first input end and the second input end of the comparator. The analog-to-digital converter comprises a comparator and a converter, wherein the converter comprises a plurality of digital signal output ends, and the comparison result can be converted into a plurality of parallel digital signals with designed bit numbers.

Alternatively, V_INNAnd V_INPIs and V_OPAnd V_ONA corresponding set of differential signals, that is, a third differential signal or a fourth differential signal, a control terminal of the thirteenth control switch 15 and a control terminal of the fourteenth control switch 16 are electrically connected to the control unit 130, and the control unit 130 is configured to control the thirteenth control switch 15 and the fourteenth control switch 16 to be turned on and off synchronously.

Based on the same inventive concept, an embodiment of the present application provides a display device, including: a display panel and a signal processing circuit 1 as any of the embodiments of the present application;

the display panel includes a plurality of touch electrodes electrically connected to the first end of the first switch unit 10.

Optionally, the touch electrodes are connected to the touch output end, and each touch electrode is connected to the touch output end through a touch lead.

Optionally, referring to fig. 7, an application scenario in the field of signal processing circuit touch is provided, where the display panel includes a touch screen, and multiple touch electrodes of the touch screen are provided, and the touch electrodes correspond to the touch nodes 430, and are in contact with the touch nodes 430 through a human body to generate charge changes, so as to form touch information, and the touch information of the finger is converted into recognizable digital information through technologies such as a sampling circuit, a conversion circuit, and an amplification circuit, so as to perform display and reaction processing in the next step.

The display device of the embodiment of the application can be widely applied to various fields with touch functions, such as mobile phones, tablet computers, vehicle-mounted screens, touch televisions, touch electronics and the like. Meanwhile, the signal processing circuit of the embodiment of the present application can also be applied to other similar devices that obtain relevant information by sensing biological signals.

The display device of the embodiment of the application includes the signal processing circuit, so that the display device has the same beneficial effects as the signal processing circuit, and the detailed description is omitted here.

Based on the same inventive concept, an embodiment of the present application provides a signal processing method, which is applied to the signal processing circuit 1 of any embodiment of the present application, and as shown in fig. 8, the signal processing method includes: step S801 to step S802.

S801, in a first charge sampling and converting phase, when the excitation voltage signal is at a first level, controlling the first terminal and the third terminal of the first switch unit 10 and the second terminal and the fourth terminal of the first switch unit 10 to be conducted, so that the charge sampling and converting unit 20 correspondingly outputs a first group of differential signals from the first output terminal and the second output terminal of the charge sampling and converting unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the first level is a low level and the second level is a high level.

Optionally, the control unit 30 receives the excitation voltage signal Vex, and outputs a control signal to each control switch of the first switch unit 10 according to the received excitation voltage signal Vex and the sampling signal SHA, so as to control each control switch to be turned on and off correspondingly, thereby implementing different signals to be input into the charge sampling conversion unit 20.

Optionally, when the excitation voltage signal is at the first level, the control unit 30 controls the first terminal and the third terminal of the first switching unit 10 and the second terminal and the fourth terminal to be conducted, so that the charge sampling conversion unit 20 correspondingly outputs the first group of differential signals from the first output terminal and the second output terminal of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

S802, in the second charge sampling and converting stage, when the excitation voltage signal is at the second level, controlling the first terminal and the fourth terminal of the first switch unit 10 and the second terminal and the third terminal of the first switch unit 10 to be conducted, so that the charge sampling and converting unit 20 correspondingly outputs a second group of differential signals from the first output terminal and the second output terminal of the charge sampling and converting unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the control unit 30 controls the first terminal and the fourth terminal of the first switching unit 10 and the second terminal and the third terminal to be conducted, so that the charge sampling conversion unit 20 correspondingly outputs a second set of differential signals from the first output terminal and the second output terminal of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the first charge sampling conversion phase corresponds to a first half period of the excitation voltage signal, and the second charge sampling conversion phase corresponds to a second half period of the excitation voltage signal.

Alternatively, step S802 may be performed after step S801 is performed; step S801 may be executed after step S802 is executed.

In some embodiments, referring to fig. 3, controlling the first terminal and the third terminal of the first switching unit 10 to be conducted and the second terminal and the fourth terminal to be conducted includes:

the second control switch 7 and the third control switch 6 controlling the first switching unit 10 are both turned on, and the first control switch 8 and the fourth control switch 5 of the first switching unit 10 are both turned off.

Controlling the first end and the fourth end of the first switch unit 10 and the second end and the third end to be conducted includes:

the second control switch 7 and the third control switch 6 controlling the first switching unit 10 are both turned off, and the first control switch 8 and the fourth control switch 5 of the first switching unit 10 are both turned on.

Optionally, the signal processing method further includes:

in the first charge sampling conversion stage, when the excitation voltage signal is at the first level, the second reset module 22 is turned on and off with the forward input end and the first output end of the differential charge amplifier 9, so that a voltage difference exists between the reverse input end and the forward input end of the differential charge amplifier 9, and after the voltage difference is amplified by the differential charge amplifier 9, a first group of differential signals is obtained.

Alternatively, as shown in fig. 3, when the excitation voltage signal Vex is at the low level stage in one cycle, the first charge sampling process is performed, since both ends of the differential charge amplifier 9 are input with the low level of the excitation voltage signal Vex, after the first reset switch 11 and the second reset switch 13 are reset, the capacitor Cfb2 acts on the forward input end and the second output end of the differential charge amplifier 9, the charge on the capacitor Cfb2 is 0 since the second reset switch 13 is turned on, and after the second reset switch 13 is turned off, since the voltage difference exists between the inverting input end and the forward input end of the differential charge amplifier 9, after the amplification by the differential charge amplifier 9, V is obtained_OPAnd V_ONOf the signal of (1). Since the excitation voltage signal Vex is now low and connected to the positive input, V is generated_OPGreater than V_ONThe differential signal of (2).

In the second charge sampling and converting stage, when the excitation voltage signal is at the second level, the first reset module 21 is turned on and off with the inverting input terminal and the first output terminal of the differential charge amplifier 9, so that a voltage difference exists between the inverting input terminal and the forward input terminal of the differential charge amplifier 9, and after the voltage difference is amplified by the differential charge amplifier 9, a second group of differential signals is obtained.

Alternatively, the second charge sampling and converting phase is similar in principle to the first charge sampling and converting phase, and when the excitation voltage signal Vex is in a high level phase in one period, the second charge sampling process is performed, similar in principle to the first charge sampling process. Since the excitation voltage signal Vex is now high and connected at the inverting input, V is generated_OPLess than V_ONThe differential signal of (2).

In some embodiments, the signal processing method further comprises:

outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage, and a gate bias voltage; the set of differential signals includes a first set of differential signals or a second set of differential signals, and the gate bias voltage is a gate bias voltage of a switching device connected to the input terminal of the operational amplifier 18.

Correspondingly outputting a third set of differential signals or a fourth set of differential signals from the first output end and the second output end of the operational amplifier 18 based on the common mode level feedback signal; the average value of the differential signals of the third group of differential signals is a predetermined common mode voltage; the average of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

Alternatively, referring to fig. 5, the circuit based on the common mode level feedback unit 14 outputs the common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage and a gate bias voltage, and includes:

and controlling the fifth control switch 141 and the sixth control switch 142 to be conducted, and controlling the ninth control switch 145 and the tenth control switch 146 to be conducted, so that the lower plates of the first capacitor and the fourth capacitor are charged to the VBN1 original bias voltage potential, and the upper plates of the two first capacitors and the fourth capacitor are charged to the desired VCM common mode level potential.

And the seventh control switch 143 and the eighth control switch 144 are controlled to be turned on, the eleventh control switch 147 and the twelfth control switch 148 are controlled to be turned on, the first capacitor is connected with the second capacitor in parallel, and the third capacitor is connected with the fourth capacitor in parallel.

Alternatively, after the above-mentioned switching control, VBN1 is transmitted to VCMFB, and VOP1 and VON1 connect their common-mode potentials to VCM through the charged first and fourth capacitors, so as to obtain a common-mode level feedback signal VCMFB, which is output to the input terminal of the operational amplifier 18.

Optionally, the signal processing method further includes: in the signal conversion phase, the control unit 30 controls the thirteenth control switch 15 and the fourteenth control switch 16 to be turned on synchronously. Referring to fig. 7, a specific signal conversion is illustrated by taking the converter located in the digital front end unit DFE as an example.

Optionally, after the control unit 30 controls the thirteenth control switch 15 and the fourteenth control switch 16 to be turned on synchronously, the method further includes:

the output of each converter is converted into serial data, and the serial data is converted into parallel data with 10 bit number in a digital module.

Through the signal conversion process, the digital signals of n D [9:0] can be reduced to the digital signals of n D [0], and the number of the interaction signals is reduced by 10 times, so that two groups of data signals are obtained based on the first group of differential signals and the second group of differential signals.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

(1) the charge sampling conversion unit 20 of the embodiment of the application can realize charge sampling conversion into differential output voltage signals in a period, different switch combinations are started through the circuit framework of the cross conversion input end switch sampling channel, charge sampling twice in a period can be realized, two groups of sampling data can be obtained after the follow-up analog-to-digital converter 171, further noise filtering, integration and processing of source data are realized through a digital circuit, and the influence of middle and low frequency noise on the sampling data can be effectively reduced.

(2) In the embodiment of the present application, a sample-and-hold amplifier is not used, so that the areas of the sample amplifier and the related sampling capacitor and hold capacitor are omitted, and at the same time, only one differential charge amplifier 9 is used, so that the power consumption of the part of the signal processing circuit 1 can be greatly reduced.

(3) The embodiment of the application adopts the realization method of the common-mode feedback circuit, so that the charge can be directly sampled and converted into the differential signal with the preset common-mode voltage twice in one period, the application of the double-sampling concept in the field of touch sampling can effectively filter the low-and-medium-frequency noise, and the anti-noise performance, the stability, the sensitivity and the accuracy of the whole chip are improved.

(4) The analog-to-digital converter 171 according to the embodiment of the present application can convert serial data into serial data through the output of the converter, convert the serial data into parallel data with 10-bit number in the digital module, and reduce the number of the interaction signals by 10 times, thereby obtaining two sets of data signals based on the first set of differential signals and the second set of differential signals.

Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims (14)

1. A signal processing circuit, comprising: a first switching unit and a charge sampling conversion unit;

the first end and the second end of the first switch unit are respectively used for receiving a first voltage and an excitation voltage signal, and the third end and the fourth end of the first switch unit are respectively electrically connected with the reverse input end and the forward input end of the charge sampling conversion unit; the first voltage is derived based on the charge generated by sensing the bio-signal;

the charge sampling conversion unit is used for correspondingly outputting a first group of differential signals from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage when the excitation voltage signal is at a first level, and the first end and the third end of the first switch unit are connected with the second end and the fourth end; and when the excitation voltage signal is at a second level, and the first end and the fourth end of the first switch unit are conducted with the second end and the third end, correspondingly outputting a second group of differential signals from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage.

2. The signal processing circuit of claim 1, further comprising:

the control unit is electrically connected with the first switch unit and used for controlling the conduction of the first end and the third end of the first switch unit and the conduction of the second end and the fourth end when the excitation voltage signal is at a first level; and when the excitation voltage signal is at a second level, controlling the first end and the fourth end of the first switch unit to be conducted, and controlling the second end and the third end of the first switch unit to be conducted.

3. The signal processing circuit according to claim 2, wherein the first switching unit includes a first control switch, a second control switch, a third control switch, and a fourth control switch;

a first terminal of the first control switch and a first terminal of the third control switch are used as a second terminal of the first switch unit together;

the second end of the first control switch and the second end of the second control switch are used as the third end of the first switch unit together;

a first end of the second control switch and a first end of the fourth control switch are used as a first end of the first switch unit together;

a second terminal of the third control switch and a second terminal of the fourth control switch are used as a fourth terminal of the first switch unit together;

the control unit is electrically connected with the control ends of the first control switch, the second control switch, the third control switch and the fourth control switch and is used for controlling the connection and disconnection of the first control switch, the second control switch, the third control switch and the fourth control switch.

4. The signal processing circuit of claim 2, wherein the charge sampling conversion unit comprises: the circuit comprises a differential charge amplifier, a first reset module and a second reset module;

a positive input end, a negative input end, a first output end and a second output end of the differential charge amplifier are respectively used as the positive input end, the negative input end, the first output end and the second output end of the charge sampling conversion unit;

the first end and the second end of the first reset module are respectively and electrically connected with the reverse input end and the first output end of the differential charge amplifier;

the first end and the second end of the second reset module are respectively and electrically connected with the positive input end and the second output end of the differential charge amplifier;

the first reset module comprises a first reset capacitor and a first reset switch, and a first end of the first reset capacitor and a first end of the first reset switch are jointly used as a first end of the first reset module; a second end of the first reset capacitor and a second end of the first reset switch are jointly used as a second end of the first reset module;

the second reset module comprises a second reset capacitor and a second reset switch, and a first end of the second reset capacitor and a first end of the second reset switch are jointly used as a first end of the second reset module; a second end of the second reset capacitor and a second end of the second reset switch are jointly used as a second end of the second reset module;

the control unit is electrically connected with the first reset switch and the second reset switch and is used for controlling the connection and disconnection of the first reset switch and the second reset switch.

5. The signal processing circuit of claim 1, further comprising: denoising a capacitor;

the first end of the denoising capacitor is electrically connected with the reverse input end of the charge sampling conversion unit;

and the second end of the de-noising capacitor is used for receiving an excitation voltage signal.

6. The signal processing circuit of claim 1, further comprising: a common mode level feedback unit and an operational amplifier;

the first input end and the second input end of the common mode level feedback unit are respectively and electrically connected with the first output end and the second output end of the charge sampling conversion unit; the output end of the common mode level feedback unit is electrically connected with the input end of the operational amplifier;

the common mode level feedback unit is used for outputting a common mode level feedback signal based on a group of differential signals, a preset common mode voltage and a grid bias voltage; the set of differential signals comprises a first set of differential signals or a second set of differential signals, and the gate bias voltage is the gate bias voltage of a switching device connected with the input end of the operational amplifier.

7. The signal processing unit of claim 6, wherein the operational amplifier is configured to output a third set of differential signals or a fourth set of differential signals from the first output terminal and the second output terminal of the operational amplifier, respectively, based on the common mode level feedback signal; an average value of the differential signals of the third set of differential signals is a predetermined common mode voltage; an average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

8. The signal processing circuit of claim 7, wherein the common mode level feedback unit comprises: a first common mode level feedback sub-circuit;

the first common-mode level feedback sub-circuit comprises a fifth control switch, a sixth control switch, a seventh control switch, an eighth control switch, a first capacitor and a second capacitor;

the first end of the fifth control switch, the first end of the sixth control switch and the first end of the seventh control switch are respectively used for receiving a preset common-mode voltage, a grid bias voltage and one differential signal in a group of differential signals;

a second end of the fifth control switch and a second end of the seventh control switch are electrically connected with the first end of the first capacitor; a second end of the sixth control switch, a second end of the eighth control switch and a second end of the first capacitor are electrically connected;

the first end of the second capacitor is electrically connected with the first end of the seventh control switch, and the second end of the second capacitor is electrically connected with the first end of the eighth control switch and the output end of the common mode level feedback unit.

9. The signal processing circuit of claim 8, wherein the common mode level feedback unit further comprises: a second common mode level feedback sub-circuit;

the second common mode level feedback sub-circuit comprises a ninth control switch, a tenth control switch, an eleventh control switch, a twelfth control switch, a third capacitor and a fourth capacitor;

the first end of the ninth control switch, the first end of the tenth control switch and the first end of the eleventh control switch are respectively used for receiving a predetermined common mode voltage, a grid bias voltage and another differential signal in a group of differential signals;

a second end of the ninth control switch and a second end of the eleventh control switch are electrically connected with a first end of the fourth capacitor; a second end of the tenth control switch, a second end of the twelfth control switch and a second end of the fourth capacitor are electrically connected;

the first end of the third capacitor is electrically connected with the first end of the eleventh control switch, and the second end of the third capacitor is electrically connected with the first end of the twelfth control switch and the output end of the common mode level feedback unit.

10. The signal processing circuit of claim 7, further comprising: a signal conversion unit;

the first input end and the second input end of the signal conversion unit are respectively used for being electrically connected with the first output end and the second output end of the charge sampling conversion unit;

the signal conversion unit is configured to compare the third group of differential signals or compare the fourth group of differential signals to obtain a comparison result, and convert the comparison result into a digital signal.

11. A display device, comprising: a display panel and a signal processing circuit according to any one of claims 1-10;

the display panel comprises a plurality of touch electrodes, and the touch electrodes are electrically connected with the first ends of the first switch units.

12. A signal processing method applied to a signal processing circuit according to any one of claims 1 to 10, comprising:

in a first charge sampling conversion stage, when an excitation voltage signal is at a first level, controlling a first end and a third end of a first switch unit and a second end and a fourth end of the first switch unit to be conducted, so that a first group of differential signals are correspondingly output from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and a first voltage;

and in a second charge sampling conversion stage, when the excitation voltage signal is at a second level, controlling the first end and the fourth end of the first switch unit and the second end and the third end to be conducted, so that a second group of differential signals are correspondingly output from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage.

13. The method according to claim 12, wherein the controlling the first terminal and the third terminal of the first switch unit to be conducted and the second terminal and the fourth terminal to be conducted comprises:

controlling the second control switch and the third control switch of the first switch unit to be on, and controlling the first control switch and the fourth control switch of the first switch unit to be off;

the control the first end and the fourth end of first switch unit and second end and third end switch on, include:

and the second control switch and the third control switch which control the first switch unit are both switched off, and the first control switch and the fourth control switch of the first switch unit are both switched on.

14. The signal processing method of claim 13, further comprising:

outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage, and a gate bias voltage; the group of differential signals comprises a first group of differential signals or a second group of differential signals, and the grid bias voltage is the grid bias voltage of a switching device connected with the input end of the operational amplifier;

correspondingly outputting a third group of differential signals or a fourth group of differential signals from a first output end and a second output end of the operational amplifier based on the common mode level feedback signal; an average value of the differential signals of the third set of differential signals is a predetermined common mode voltage; an average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

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