CN114356014B - Low-voltage reference voltage generating circuit and chip - Google Patents
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Abstract
The invention discloses a low-voltage reference voltage generating circuit and a chip, wherein the circuit comprises a reference current source module, a buffer module and a high-order temperature compensation module, wherein the reference current source module is used for respectively providing zero-temperature current for the buffer module and the high-order temperature compensation module and providing negative-temperature characteristic voltage for the buffer module; the buffer module is used for generating an offset voltage with positive temperature characteristic according to the zero-temperature current, and superposing the offset voltage and the negative temperature characteristic voltage to output a first bandgap reference voltage; the high-order temperature compensation module is used for performing high-order temperature compensation on the first bandgap reference voltage according to the zero-temperature current so that the buffer module outputs the low-temperature drift bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and meanwhile, the design complexity and the power consumption of the circuit can be reduced.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a low voltage reference voltage generating circuit and a chip.
Background
The band gap reference voltage circuit can provide a reference voltage which is irrelevant to the process, voltage and temperature, so that the band gap reference voltage circuit is widely applied to various analog circuits, along with the rapid development of a high-precision data acquisition system in the industrial field, the sampling precision of a chip in the acquisition system and the variation of the sampling precision along with the temperature are seriously dependent on a high-precision reference source on the chip, in order to ensure that the absolute sampling precision does not change along with the temperature when the chip works in a wide temperature range, the development of the high-precision band gap reference voltage source which works in a low-temperature drift and wide temperature range is needed, and meanwhile, along with the continuous shrinkage of process nodes, the working voltage of the chip is gradually reduced, and higher requirements are also provided for the minimum working voltage of the chip reference source.
The prior related band gap reference source solution is to add a high-order temperature compensation loop to the conventional band gap reference source circuit to realize the high-order temperature compensation of the band gap reference voltage, thereby improving the precision of the reference source, but the method is difficult to realize the further reduction of the reference voltage and cannot meet the low-voltage reference voltage in a wide working voltage range, and meanwhile, the method also greatly increases the design complexity and the power consumption.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first object of the present invention is to provide a low-voltage reference voltage generating circuit, which not only can output a low-temperature drift band gap reference voltage, but also can make the low-temperature drift band gap reference voltage in a wide operating voltage range, and can reduce the complexity of circuit design and power consumption.
A second object of the invention is to propose a chip.
In order to achieve the above objective, an embodiment of a first aspect of the present invention provides a low-voltage reference voltage generating circuit, which includes a reference current source module, a buffer module, and a high-order temperature compensation module, wherein the reference current source module is configured to provide zero temperature current to the buffer module and the high-order temperature compensation module, respectively, and provide negative temperature characteristic voltage to the buffer module; the buffer module is used for generating an offset voltage with positive temperature characteristic according to the zero-temperature current, and superposing the offset voltage and the negative temperature characteristic voltage to output a first bandgap reference voltage; the high-order temperature compensation module is used for performing high-order temperature compensation on the first bandgap reference voltage according to the zero-temperature current so that the buffer module outputs the low-temperature drift bandgap reference voltage.
According to the low-voltage reference voltage generating circuit provided by the embodiment of the invention, zero-temperature current is respectively provided for the buffer module and the high-order temperature compensation module through the reference current source module, negative temperature characteristic voltage is provided for the buffer module, the buffer module generates offset voltage with positive temperature characteristic according to the zero-temperature current, the offset voltage is overlapped with the negative temperature characteristic voltage provided by the reference current source module to output first bandgap reference voltage, and high-order temperature compensation is performed on the first bandgap reference voltage through the high-order temperature compensation module according to the zero-temperature current, so that the buffer module outputs low-temperature drift bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and meanwhile, the design complexity and the power consumption of the circuit can be reduced.
According to one embodiment of the invention, the buffer module comprises at least one buffer.
According to one embodiment of the present invention, when there are a plurality of buffers, the plurality of buffers are cascaded.
According to one embodiment of the present invention, a buffer includes: the source electrode of the first transistor is connected to a preset power supply, and the grid electrode of the first transistor is connected with the reference current source module; the source electrode of the second transistor is connected with the source electrode of the third transistor and then is connected with the drain electrode of the first transistor, the grid electrode of the second transistor is connected with the reference current source module, and the grid electrode of the third transistor is connected with the drain electrode and then is used as a cascade output end of the buffer; a grid electrode of the fourth transistor is connected with the drain electrode and then connected to the drain electrode of the second transistor, and a source electrode of the fourth transistor is grounded; and the grid electrode of the fifth transistor is connected with the grid electrode of the fourth transistor, the drain electrode of the fifth transistor is connected with the drain electrode of the third transistor, and the source electrode of the fifth transistor is grounded.
According to one embodiment of the present invention, the first transistor, the second transistor, and the third transistor are PMOS transistors, and the fourth transistor and the fifth transistor are NMOS transistors.
According to one embodiment of the present invention, the second transistor, the third transistor, the fourth transistor, and the fifth transistor operate in a sub-threshold region.
According to one embodiment of the present invention, the size ratio of the second transistor to the third transistor is 1: the size ratio of the fourth transistor to the fifth transistor is P:1, wherein M and P are positive integers greater than 1.
According to one embodiment of the present invention, a reference current source module includes: a source electrode of the sixth transistor is connected with a source electrode of the seventh transistor and then is connected to a preset power supply, and a grid electrode of the sixth transistor is connected with a grid electrode of the seventh transistor and is provided with a first node; an eighth transistor, the emitter of which is connected with the drain of the sixth transistor and has a second node, and the base of which is connected with the collector and then grounded; one end of the first resistor is connected with the drain electrode of the seventh transistor and is provided with a third node; a ninth transistor, the emitter of which is connected with the other end of the first resistor, and the base of which is connected with the collector and then grounded; the positive input end of the error amplifier is connected with the third node, the negative input end of the error amplifier is connected with the second node, and the output end of the error amplifier is connected with the first node and then connected to the grid electrode of the first transistor; one end of the second resistor is connected with the negative input end of the error amplifier; one end of the third resistor is connected with the positive input end of the error amplifier, the other end of the third resistor is connected with the other end of the second resistor and is provided with a fourth node, and the fourth node is connected to the grid electrode of the second transistor; and one end of the fourth resistor is connected with the fourth node, and the other end of the fourth resistor is grounded.
According to one embodiment of the present invention, the ratio of emitter areas of the eighth transistor to the ninth transistor is 1: and N, wherein N is an integer greater than 1.
According to one embodiment of the invention, the high-order temperature compensation module comprises: a tenth transistor, a source electrode of which is connected to a preset power supply, and a gate electrode of which is connected to an output end of the error amplifier; an eleventh transistor having an emitter connected to the drain of the tenth transistor and a fifth node, and a collector connected to the base and then grounded; one end of the fifth resistor is connected with the fifth node, and the other end of the fifth resistor is connected with the second node; and one end of the sixth resistor is connected with the fifth node, and the other end of the sixth resistor is connected with the third node.
According to one embodiment of the present invention, the eighth transistor, the ninth transistor, and the eleventh transistor are bipolar transistors.
According to one embodiment of the present invention, the sixth transistor, the seventh transistor and the tenth transistor are PMOS transistors and are equal in size.
According to one embodiment of the present invention, the final low temperature drift band gap reference voltage output by the buffer module is determined according to an emitter-base voltage of the eighth transistor, an emitter-base voltage of the eleventh transistor, a resistance of the second resistor, a resistance of the fourth resistor, a resistance of the fifth resistor, and a difference between a gate-source voltage of the third transistor and a gate-source voltage of the fourth transistor.
To achieve the above object, an embodiment of a second aspect of the present invention provides a chip including a low voltage reference voltage generating circuit as in the embodiment of the first aspect.
According to the chip provided by the embodiment of the invention, through the low-voltage reference voltage generating circuit, not only can the output of the low-temperature drift band gap reference voltage be realized, but also the low working voltage can be in a wide working voltage range, and meanwhile, the complexity of circuit design and the consumption of power consumption can be reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic diagram of a low-voltage reference voltage generating circuit according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a low voltage reference voltage generating circuit according to a second embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
The low voltage reference voltage generating circuit and the chip according to the embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a low voltage reference voltage generating circuit according to a first embodiment of the present invention. As shown in fig. 1, the low voltage reference voltage generating circuit includes a reference current source module 100, a buffer module 200, and a high order temperature compensation module 300.
The reference current source module 100 is configured to provide zero temperature current to the buffer module 200 and the high-order temperature compensation module 300, and provide negative temperature characteristic voltage to the buffer module 200; the buffer module 200 is configured to generate an offset voltage with a positive temperature characteristic according to the zero temperature current, and superimpose the offset voltage with a negative temperature characteristic voltage to output a first bandgap reference voltage; the high-order temperature compensation module 300 is configured to perform high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current, so that the buffer module 300 outputs a low-temperature drift bandgap reference voltage.
Specifically, when the low voltage reference voltage generating circuit works, the reference current source module 100 can generate a current which does not change along with temperature, namely zero temperature current, and can form a voltage with negative temperature characteristic, the buffer module 200 is connected with the reference current source module 100 and is used for receiving the zero temperature current generated by the reference current source module 100 and the negative temperature characteristic voltage, the buffer module 200 can form an offset voltage with positive temperature characteristic according to the received zero temperature current, the offset voltage with positive temperature characteristic is overlapped with the negative temperature characteristic voltage directly obtained from the reference current source module 100, so that a first bandgap reference voltage is formed, and the first bandgap reference voltage is overlapped by the offset voltage with positive temperature characteristic and the negative temperature characteristic voltage, so that a bandgap reference voltage with zero temperature characteristic is finally formed, and therefore, the application of the buffer module can be realized under a wide working voltage range, the high-order temperature compensation module 300 is respectively connected with the reference current source module 100 and the buffer module 200, and the high-order temperature compensation module 300 can accurately compensate the first bandgap reference voltage formed by the buffer module 200 according to the zero temperature current obtained by the reference current from the reference current source module 100, and the final bandgap reference voltage is realized, and the low voltage reference circuit is enabled to have a final bandgap voltage.
According to the low-voltage reference voltage generating circuit provided by the embodiment of the invention, zero-temperature current is respectively provided for the buffer module and the high-order temperature compensation module through the reference current source module, negative temperature characteristic voltage is provided for the buffer module, the buffer module generates offset voltage with positive temperature characteristic according to the zero-temperature current, the offset voltage is overlapped with the negative temperature characteristic voltage provided by the reference current source module to output first bandgap reference voltage, and high-order temperature compensation is performed on the first bandgap reference voltage through the high-order temperature compensation module according to the zero-temperature current, so that the buffer module outputs low-temperature drift bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and meanwhile, the design complexity and the power consumption of the circuit can be reduced.
In some embodiments, the buffer module 200 includes at least one buffer; when there are multiple buffers, the number of the buffers can be selectively set according to actual requirements, for example, as shown in fig. 2, the buffer module 200 includes two buffers.
Further, with continued reference to fig. 2, each buffer includes: a first transistor (e.g., M1), a second transistor (e.g., M2), a third transistor (e.g., M3), a fourth transistor (e.g., M4), and a fifth transistor (e.g., M5), wherein a source of the first transistor (e.g., M1) is connected to a predetermined power supply VDD, and a gate of the first transistor (e.g., M1) is connected to the reference current source module 100; the source electrode of the second transistor (such as M2) is connected with the source electrode of the third transistor (such as M3) and then is connected to the drain electrode of the first transistor (such as M1), the grid electrode of the second transistor (such as M2) is connected with the reference current source module 100, and the grid electrode of the third transistor (such as M3) is connected with the drain electrode and then is used as a cascade output end of the buffer; the grid electrode of the fourth transistor (such as M4) is connected with the drain electrode and then connected to the drain electrode of the second transistor (such as M2), and the source electrode of the fourth transistor (such as M4) is grounded GND; the gate of the fifth transistor (e.g., M5) is connected to the gate of the fourth transistor (e.g., M4), the drain of the fifth transistor (e.g., M5) is connected to the drain of the third transistor (e.g., M3), and the source of the fifth transistor (e.g., M5) is connected to GND.
Specifically, taking the buffer module 200 as an example, referring to fig. 2, the two buffers are a first buffer and a second buffer respectively, the two buffers are connected in cascade, the source electrodes of the transistor M1 in the first buffer and the transistor M1' in the second buffer are both connected to the preset power supply VDD, the gate electrodes of the transistor M1 and the transistor M1' are connected to the reference current source module 100, the source electrodes of the transistor M2 and the transistor M3 in the first buffer are connected to the drain electrode of the transistor M1, the gate electrode of the transistor M2 is connected to the reference current source module 100, the gate electrode of the transistor M3 is connected to the gate electrode of the transistor M2' in the second buffer, the gate electrode of the transistor M4 in the first buffer is connected to the drain electrode of the transistor M2 after being connected to the drain electrode, the source electrode of the transistor M4 is grounded, the gate electrode of the transistor M5 in the first buffer is connected to the gate electrode of the transistor M4, the drain electrode of the transistor M5 is connected to the drain electrode of the transistor M3 is grounded, and the drain electrode of the transistor M5 is connected to the ground GND; the source electrode of the transistor M2 'and the source electrode of the transistor M3' in the second buffer are connected and then connected to the drain electrode of the transistor M1', the grid electrode of the transistor M3' is connected with the drain electrode and then used as a cascade output end of the buffer, the grid electrode of the transistor M4 'in the second buffer is connected with the drain electrode and then connected to the drain electrode of the transistor M2', the source electrode of the transistor M4 'is grounded GND, the grid electrode of the transistor M5' in the second buffer is connected with the grid electrode of the transistor M4', the drain electrode of the transistor M5' is connected with the drain electrode of the transistor M3', and the source electrode of the transistor M5' is grounded GND.
In some embodiments, the first transistor (e.g., M1), the second transistor (e.g., M2), and the third transistor (e.g., M3) are PMOS transistors, and the fourth transistor (e.g., M4) and the fifth transistor (e.g., M5) are NMOS transistors. That is, as shown in fig. 2, the transistors M1, M2 and M3 in the first buffer are PMOS transistors, and the transistors M4 and M5 are NMOS transistors; transistors M1', M2' and M3' in the second buffer are PMOS transistors, and transistors M4' and M5' are NMOS transistors.
In some embodiments, the second transistor (e.g., M2), the third transistor (e.g., M3), the fourth transistor (e.g., M4), and the fifth transistor (e.g., M5) operate in sub-threshold regions. That is, as shown in fig. 2, the transistors M2, M3, M4, and M5 in the first buffer operate in the sub-threshold region; m2', M3', M4 'and M5' in the second buffer operate in the subthreshold region.
In some embodiments, the ratio of the dimensions of the second transistor (e.g., M2) to the third transistor (e.g., M3) is 1: the dimension ratio of the fourth transistor (e.g., M4) to the fifth transistor (e.g., M5) is P:1, wherein M and P are positive integers greater than 1. That is, as shown in fig. 2, the size ratio of the transistor M2 to the transistor M3 in the first buffer is 1: the dimension ratio of the transistor M4 to the transistor M5 is P:1, a step of; the size ratio of the transistor M2 'to the transistor M3' in the second buffer is 1: the dimension ratio of the transistor M4 'to the transistor M5' is P:1.
specifically, when the buffer module 200 is operated, the transistor M1 in the first buffer and the transistor M1' in the second buffer are controlled by the reference current source module 100 to flow the same current, and the transistors M2, M3, M4 and M5 in the first buffer operate in the subthreshold region, and by utilizing the characteristic that the transistors operate in the subthreshold region, the size ratio of the transistors is designed, for example, the size ratio of the transistor M2 to the transistor M3 in the first buffer is set to be 1: the dimension ratio of the transistor M4 to the transistor M5 is P:1, an offset voltage with positive temperature characteristics can be generated; the structure of the second buffer is the same as that of the first buffer, and the transistors M2', M3', M4' and M5' in the second buffer also work in the subthreshold region, so that an offset voltage with positive temperature characteristics can be generated, and the grid electrode of the transistor M2' in the second buffer is connected with the grid electrode of the transistor M3 in the first buffer, so that cascade connection of the buffers is realized, and finally, the negative temperature characteristic voltage formed by the reference current source module 100 is overlapped according to the offset voltage with positive temperature characteristics formed by the first buffer and the second buffer, so that a band gap reference voltage with zero temperature characteristics, namely a first band gap reference voltage, is obtained.
In some embodiments, as shown in fig. 2, the reference current source module 100 includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first resistor R1, a ninth transistor M9, an error amplifier a, a second resistor R2, a third resistor R3, and a fourth resistor R4.
The source of the sixth transistor M6 is connected to the source of the seventh transistor M7 and then connected to the preset power supply VDD, and the gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7 and has a first node; an emitter of the eighth transistor M8 is connected to a drain of the sixth transistor M6 and has a second node, and a base of the eighth transistor M8 is connected to a collector and then to the ground GND; one end of the first resistor R1 is connected with the drain electrode of the seventh transistor M7 and is provided with a third node; an emitter of the ninth transistor M9 is connected with the other end of the first resistor R1, and a base and a collector of the ninth transistor M9 are connected and then grounded GND; the positive input end of the error amplifier A is connected with the third node, the negative input end of the error amplifier A is connected with the second node, and the output end of the error amplifier A is connected with the first node and then connected to the grid electrode of the first transistor (such as M1); one end of the second resistor R2 is connected with the negative input end of the error amplifier A; one end of the third resistor R3 is connected with the positive input end of the error amplifier A, the other end of the third resistor R3 is connected with the other end of the second resistor R2 and is provided with a fourth node, and the fourth node is connected to the grid electrode of the second transistor (such as M2); one end of the fourth resistor R4 is connected to the fourth node, and the other end of the fourth resistor R4 is grounded GND.
Specifically, the output terminal of the operational amplifier a is connected to the sixth transistor M6 and the seventh transistor M7, respectively, the sixth transistor M6 and the seventh transistor M7 are controlled by the operational amplifier a, the magnitude of the generated current is proportional to the size of the generated current, the eighth transistor M8 and the ninth transistor M9 generate a current proportional to the temperature, that is, a positive temperature current, and transmit the current to the first resistor R1, and the second resistor R2, the third resistor R3 and the fourth resistor R4 generate a negative temperature current, and the current in the seventh transistor M7 is the sum of the currents flowing through the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, so that by adjusting the proportion of the first resistor R1 to the second resistor R2, the third resistor R3 and the fourth resistor R4, a first-order zero temperature current can be obtained and transmitted to the buffer module 200 and the high-order temperature compensation module 300, respectively.
In some embodiments, the ratio of emitter areas of the eighth transistor M8 to the ninth transistor M9 is 1: and N, wherein N is an integer greater than 1. That is, the ratio of the saturation currents of the eighth transistor M8 and the ninth transistor M9 is 1: n.
In some embodiments, as shown in fig. 2, the high-order temperature compensation module 300 includes: a tenth transistor M10, an eleventh transistor M11, a fifth resistor R5, and a sixth resistor R6.
The source electrode of the tenth transistor M10 is connected to a preset power supply VDD, and the grid electrode of the tenth transistor M10 is connected with the output end of the error amplifier A; an emitter of the eleventh transistor M11 is connected to a drain of the tenth transistor M10 and has a fifth node, and a collector of the eleventh transistor M11 is connected to the base and then to the ground GND; one end of the fifth resistor R5 is connected with a fifth node, and the other end of the fifth resistor R5 is connected with a second node; one end of the sixth resistor R6 is connected to the fifth node, and the other end of the sixth resistor R6 is connected to the third node.
Specifically, the output terminal of the operational amplifier a is connected to the tenth transistor M10, and the tenth transistor M10 is controlled by the operational amplifier a, so that the current in the seventh transistor M7 can be mirrored to the tenth transistor M10, and then the tenth transistor M10 can provide the current with zero temperature coefficient to the eleventh transistor M11, and the emitters of the eighth transistor M8 and the ninth transistor M9 are connected to the emitter of the eleventh transistor M11 through the fifth resistor R5 and the sixth resistor R6, respectively, so that the high-order temperature compensation of the bandgap reference voltage is realized based on the difference between the positive temperature coefficient current in the eighth transistor M8 and the ninth transistor M9 and the zero temperature coefficient current in the eleventh transistor M11.
In some embodiments, the eighth transistor M8, the ninth transistor M9, and the eleventh transistor M11 are bipolar transistors.
In some embodiments, the sixth transistor M6, the seventh transistor M7, and the tenth transistor M10 are PMOS transistors and are equal in size.
In some embodiments, the final low temperature bandgap reference voltage output by the buffer module 200 is determined according to the emitter-base voltage of the eighth transistor M8, the emitter-base voltage of the eleventh transistor M11, the resistance of the second resistor R2, the resistance of the fourth resistor R4, the resistance of the fifth resistor R5, and the difference between the gate-source voltage of the third transistor (e.g., M3) and the gate-source voltage of the fourth transistor (e.g., M4).
As a specific example, as shown in fig. 2, assume that shippingThe gain of the operational amplifier A is large enough and the input impedance is infinite, the voltages at the positive and negative inputs of the operational amplifier A are equal, the mismatch in the circuit, such as the mismatch between resistors, the mismatch between transistors and the mismatch between bipolar transistors, is ignored, and the emitter-base voltage of the eighth transistor M8 is assumed to be V EB1 The emitter-base voltage of the ninth transistor M9 is V EB2 The emitter-base voltage of the eleventh crystal M11 is V EB3 The relationship between collector current and its emitter-base voltage of a bipolar transistor is:
wherein I is C Is the collector current of a bipolar transistor, I S Is the saturation current of the bipolar transistor, V T Is thermal voltage, V T =kt/q, q is electron charge, V EB Is the emitter-base voltage of the bipolar transistor, K is the Boltzmann constant, and T is the absolute temperature.
The current in the bipolar transistor is:
wherein I is Q Is a bipolar transistor current, I E Is the emitter current of a bipolar transistor, I B Is the base current of a bipolar transistor, beta F Is the current amplification factor.
The emitter-base voltage of the bipolar transistor can thus be deduced as:
the current of the transistor operating in the subthreshold region is:
wherein I is ds Is the drain-source voltage of the transistor, I D0 Is the saturation current at the drain of the transistor,the n subthreshold ramp factor is a process-related constant, typically 1-1.5, V, for the aspect ratio of the transistor GS The gate-source voltage of the transistor, K is the Boltzmann constant, T is absolute temperature, and q is the electron charge.
Neglecting the channel length effect of the transistors, in this application, the size ratio of the transistor M2 to the transistor M3 in the first buffer is 1: the dimension ratio of the transistor M4 to the transistor M5 is P:1, combining the above formula to obtain the offset voltage of the positive temperature characteristic formed by the first buffer:
ΔV GS ＝V GS1 -V GS2 ＝nV T ln[P×M]
wherein DeltaV GS Offset voltage of positive temperature characteristic, V GS1 For the third transistor M3 gate-source voltage, V GS2 Is the fourth transistor M4 gate-source voltage. The offset voltage of the positive temperature characteristic formed by the second buffer is the same as the offset voltage of the positive temperature characteristic formed by the second buffer.
And superposing the offset voltage of the positive temperature characteristic formed by the two buffers and the negative temperature characteristic voltage, thereby obtaining a first bandgap reference voltage:
wherein V is EB1 The emitter-base voltage of the eighth transistor M8, R2 is the second resistor, and R4 is the fourth resistor.
Since the sixth transistor M6, the seventh transistor M7 and the tenth transistor M10 are PMOS transistors and have the same size, the currents of the third transistor M6, the seventh transistor M7 and the tenth transistor M10 are equal, and the eighth transistor M8 has the current I M8 And a ninth transistor M9 currentI M9 For positive temperature current, current I in second resistor R2 R2 As a negative temperature current, by adjusting the magnitude of the second resistor R2, a current relating to weak temperature can be obtained:
wherein I is M6 Sixth transistor M6 current, I M7 Seventh transistor M7 current, I M10 Tenth transistor M10 current, V EB1 For the emitter-base voltage, V, of the eighth transistor M8 EB2 The emitter-base voltage of the ninth transistor M9, R1 is a first resistor, R2 is a second resistor, and R4 is a fourth resistor.
Performing high-order temperature compensation on the first bandgap reference voltage according to the zero-temperature current to finally obtain a low-temperature drift bandgap reference voltage:
wherein V is EB1 For the emitter-base voltage, V, of the eighth transistor M8 EB3 An emitter-base voltage of the eleventh transistor M11, R2 is a second resistor, R4 is a fourth resistor, R4 is a fifth resistor, and DeltaV GS Is an offset voltage with positive temperature characteristics.
In summary, according to the low voltage reference voltage generating circuit of the embodiment of the present invention, the reference current source module provides zero temperature current to the buffer module and the high order temperature compensation module, and provides negative temperature characteristic voltage to the buffer module, the buffer module generates offset voltage with positive temperature characteristic according to the zero temperature current, and superimposes the offset voltage with the negative temperature characteristic voltage provided by the reference current source module to output a first bandgap reference voltage, and the high order temperature compensation module performs high order temperature compensation on the first bandgap reference voltage according to the zero temperature current, so that the buffer module outputs the low temperature drift bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and meanwhile, the design complexity and the power consumption of the circuit can be reduced.
The embodiment of the invention also provides a chip which comprises the low-voltage reference voltage generating circuit.
In the present application, the chip may be an ADC chip, or may be a reference voltage source chip, a switching power supply chip, or the like, which may generate a reference voltage, which is not particularly limited herein.
According to the chip provided by the embodiment of the invention, through the low-voltage reference voltage generating circuit, not only can the output of the low-temperature drift band gap reference voltage be realized, but also the low working voltage can be in a wide working voltage range, and meanwhile, the complexity of circuit design and the consumption of power consumption can be reduced.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (13)
1. A low-voltage reference voltage generating circuit is characterized by comprising a reference current source module, a buffer module and a high-order temperature compensation module, wherein,
the reference current source module is used for providing zero-temperature current for the buffer module and the high-order temperature compensation module respectively and providing negative temperature characteristic voltage for the buffer module; the reference current source module includes: a source electrode of the sixth transistor is connected with a source electrode of the seventh transistor and then is connected to a preset power supply, and a grid electrode of the sixth transistor is connected with a grid electrode of the seventh transistor and is provided with a first node; an emitter of the eighth transistor is connected with a drain of the sixth transistor and is provided with a second node, and a base of the eighth transistor is connected with a collector and then grounded; one end of the first resistor is connected with the drain electrode of the seventh transistor and is provided with a third node; an emitter of the ninth transistor is connected with the other end of the first resistor, and a base electrode of the ninth transistor is connected with a collector electrode and then grounded; the positive input end of the error amplifier is connected with the third node, the negative input end of the error amplifier is connected with the second node, and the output end of the error amplifier is connected with the first node and then connected to the buffer module; one end of the second resistor is connected with the negative input end of the error amplifier; one end of a third resistor is connected with the positive input end of the error amplifier, the other end of the third resistor is connected with the other end of the second resistor and is provided with a fourth node, the fourth node is connected to one end of the buffer module and the fourth resistor, and the other end of the fourth resistor is grounded;
the buffer module is used for generating an offset voltage with positive temperature characteristic according to the zero-temperature current, and superposing the offset voltage and the negative temperature characteristic voltage to output a first bandgap reference voltage;
the high-order temperature compensation module is used for performing high-order temperature compensation on the first bandgap reference voltage according to the zero-temperature current, so that the buffer module outputs a low-temperature drift bandgap reference voltage.
2. The low voltage reference voltage generating circuit of claim 1, wherein the buffer module comprises at least one buffer.
3. The low voltage reference voltage generating circuit according to claim 2, wherein when the number of the buffers is plural, plural ones of the buffers are cascade-connected.
4. A low voltage reference voltage generating circuit according to claim 2 or 3, wherein the buffer comprises:
a first transistor, a source electrode of which is connected to the preset power supply, and a gate electrode of which is connected to the first node;
the source electrode of the second transistor is connected with the source electrode of the third transistor and then connected to the drain electrode of the first transistor, the grid electrode of the second transistor is connected with the fourth node, and the grid electrode of the third transistor is connected with the drain electrode and then used as a cascade output end of the buffer;
a gate of the fourth transistor is connected with the drain and then connected to the drain of the second transistor, and a source of the fourth transistor is grounded;
and the grid electrode of the fifth transistor is connected with the grid electrode of the fourth transistor, the drain electrode of the fifth transistor is connected with the drain electrode of the third transistor, and the source electrode of the fifth transistor is grounded.
5. The low voltage reference voltage generating circuit according to claim 4, wherein the first transistor, the second transistor, and the third transistor are PMOS transistors, and the fourth transistor and the fifth transistor are NMOS transistors.
6. The low voltage reference voltage generating circuit according to claim 5, wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor operate in a sub-threshold region.
7. The low voltage reference voltage generating circuit according to claim 5, wherein a size ratio of the second transistor to the third transistor is 1: m, the size ratio of the fourth transistor to the fifth transistor is P:1, wherein M and P are positive integers greater than 1.
8. The low-voltage reference voltage generation circuit according to claim 1, wherein a ratio of emitter areas of the eighth transistor and the ninth transistor is 1: and N, wherein N is an integer greater than 1.
9. The low voltage reference voltage generating circuit of claim 4, wherein the high order temperature compensation module comprises:
a tenth transistor, a source electrode of which is connected to the preset power supply, and a gate electrode of which is connected to an output end of the error amplifier;
an eleventh transistor having an emitter connected to the drain of the tenth transistor and a fifth node, the collector connected to the base and then grounded;
one end of the fifth resistor is connected with the fifth node, and the other end of the fifth resistor is connected with the second node;
and one end of the sixth resistor is connected with the fifth node, and the other end of the sixth resistor is connected with the third node.
10. The low-voltage reference voltage generating circuit according to claim 9, wherein the eighth transistor, the ninth transistor, and the eleventh transistor are bipolar transistors.
11. The low voltage reference voltage generating circuit according to claim 9, wherein the sixth transistor, the seventh transistor, and the tenth transistor are PMOS transistors and are equal in size.
12. The low voltage reference voltage generating circuit according to claim 10, wherein the final low temperature drift band gap reference voltage output by the buffer module is determined according to an emitter-base voltage of the eighth transistor, an emitter-base voltage of the eleventh transistor, a resistance of the second resistor, a resistance of the fourth resistor, a resistance of the fifth resistor, and a difference between a gate-source voltage of the third transistor and a gate-source voltage of the fourth transistor.
13. A chip comprising a low voltage reference voltage generating circuit according to any one of claims 1-12.
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| CN116225142B (en) * | 2023-05-06 | 2023-07-21 | 上海灵动微电子股份有限公司 | Non-resistance band gap reference voltage source, reference voltage generating method and integrated circuit |
| CN117519403B (en) * | 2024-01-05 | 2024-04-09 | 深圳市山海半导体科技有限公司 | Band gap reference circuit and electronic equipment |
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