CN114337597A - Multistage equalization circuit and signal processing circuit board - Google Patents
Multistage equalization circuit and signal processing circuit board Download PDFInfo
- Publication number
- CN114337597A CN114337597A CN202210249965.9A CN202210249965A CN114337597A CN 114337597 A CN114337597 A CN 114337597A CN 202210249965 A CN202210249965 A CN 202210249965A CN 114337597 A CN114337597 A CN 114337597A
- Authority
- CN
- China
- Prior art keywords
- equalizer
- input
- field effect
- effect transistor
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008878 coupling Effects 0.000 claims abstract description 106
- 238000010168 coupling process Methods 0.000 claims abstract description 106
- 238000005859 coupling reaction Methods 0.000 claims abstract description 106
- 230000005669 field effect Effects 0.000 claims description 113
- 239000003990 capacitor Substances 0.000 claims description 42
- 230000008092 positive effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 11
- 230000002829 reductive effect Effects 0.000 abstract description 10
- 230000002238 attenuated effect Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000001914 filtration Methods 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Landscapes
- Amplifiers (AREA)
Abstract
The application relates to a multistage equalizer circuit and signal processing circuit board, multistage equalizer circuit includes: the balanced coupling units are connected in a cascading mode; each equalizing coupling unit comprises a first equalizer, a second equalizer, a first low-pass filter and a second low-pass filter; compared with the simple superposition of the gain of each equalizer in the prior art, the multi-stage equalizing circuit provided by the application can achieve a higher gain effect by using the same number of equalizers, and on the basis of ensuring the requirement of equalizing and compensating the gain of the attenuated signals, the number of the equalizers contained in the whole multi-stage equalizing circuit is less, so that the power consumption and the area of the multi-stage equalizing circuit are effectively reduced, the manufacturing cost of the multi-stage equalizing circuit is reduced, and the application range of the multi-stage equalizing circuit is expanded.
Description
Technical Field
The present application relates to the field of digital communication technologies, and in particular, to a multi-stage equalization circuit and a signal processing circuit board.
Background
In a high-speed serial communication system, with the continuous improvement of the data transmission rate, the attenuation of the high-frequency component of a signal in a transmission channel is also increased, so that the problem of intersymbol interference is caused, and the error rate of the serial communication system in the data transmission process is high, so that the high-frequency component of the signal needs to be compensated by an equalization technology, for example, a continuous time linear equalizer is used for compensating the attenuation of the signal, and the requirement of distortion-free transmission is met.
When the data transmission rate of the signal is continuously increased and the channel attenuation is continuously increased, the single-stage continuous time linear equalizer cannot realize the complete compensation of the attenuated signal. Therefore, in order to meet the circuit requirement of higher equalization compensation gain, a plurality of continuous time linear equalizers are generally cascaded, so that the superposition of gain is realized, and the requirement of signal compensation is met.
However, as the signal attenuation increases, the number of stages of the equalizer is also increasing, which results in larger power consumption and area of the whole equalizer circuit, increases the manufacturing cost of the equalizer circuit and limits the application range of the equalizer circuit.
Disclosure of Invention
In view of the above, it is necessary to provide a multi-stage equalization circuit and a signal processing circuit board that can reduce power consumption and area of the entire equalization circuit while ensuring that the signal compensation requirement is met.
In a first aspect, the present application provides a multi-stage equalization circuit. The multistage equalization circuit includes: the balanced coupling units are connected in a cascading mode; each equalizing coupling unit comprises a first equalizer, a second equalizer, a first low-pass filter and a second low-pass filter;
in each equalizing coupling unit, a first input end of a first equalizer is respectively connected with a first output end of a second equalizer and an input end of a first low-pass filter in one equalizing coupling unit which is connected in cascade, and a second input end of the first equalizer is respectively connected with a second output end of the second equalizer and an input end of the second low-pass filter in one equalizing coupling unit which is connected in cascade;
the first output end of the first equalizer is respectively connected with the output end of the first low-pass filter circuit and the first input end of the second equalizer; the second output end of the first equalizer is respectively connected with the output end of the second low-pass filter circuit and the second input end of the second equalizer;
the first output end of the second equalizer is connected with the first input end of the first equalizer in the next balanced coupling unit in cascade connection, and the second output end of the second equalizer is connected with the second input end of the first equalizer in the next balanced coupling unit in cascade connection;
the input end of the first equalizer in the first equalizing coupling unit receives input signals, and the output end of the second equalizer in the last equalizing coupling unit outputs gain signals.
In one embodiment, each equalizing coupling unit further comprises: a first subtractor and a second subtractor; the first input end of the first subtracter is connected with the first output end of the first equalizer, the second input end of the first subtracter is connected with the output end of the first low-pass filter, and the output end of the first subtracter is connected with the first input end of the second equalizer; the first input end of the second subtracter is connected with the second output end of the first equalizer, the second input end of the second subtracter is connected with the output end of the second low-pass filter, and the output end of the second subtracter is connected with the second input end of the second equalizer.
In one embodiment, the first equalizer comprises: the device comprises a first input positive field effect tube, a first input negative field effect tube, a first gain positive field effect tube, a first grounding negative field effect tube, a first positive load resistor, a first negative load resistor, a first feedback resistor and a first feedback capacitor; the drain electrode of the first input positive field effect transistor is respectively connected with a first positive load resistor, and the source electrode of the first input positive field effect transistor is respectively connected with a first feedback resistor, a first feedback capacitor and the drain electrode of the first grounding positive field effect transistor; the grid electrode and the source electrode of the first grounding positive field effect transistor are grounded; the drain electrode of the first input negative field effect tube is respectively connected with a first negative load resistor, and the source electrode of the first input negative field effect tube is respectively connected with a first feedback resistor, a first feedback capacitor and the drain electrode of the first grounding negative field effect tube; the grid electrode and the source electrode of the first grounded negative field effect transistor are grounded; the first positive load resistor and the first negative load resistor are connected with a preset power supply.
In one embodiment, the second equalizer comprises: the second input positive field effect transistor, the second input negative field effect transistor, the second grounding field positive effect transistor, the second grounding negative field effect transistor, the second positive load resistor, the second negative load resistor, the second feedback resistor and the second feedback capacitor; the drain electrode of the second input positive field effect transistor is respectively connected with a second positive load resistor, and the source electrode of the second input positive field effect transistor is respectively connected with a second feedback resistor, a second feedback capacitor and the drain electrode of the second grounding positive field effect transistor; the grid electrode and the source electrode of the second grounding positive field effect transistor are grounded; the drain electrode of the second input negative field effect tube is respectively connected with a second negative load resistor, and the source electrode of the second input negative field effect tube is respectively connected with a second feedback resistor, a second feedback capacitor and the drain electrode of the second grounding negative field effect tube; the grid electrode and the source electrode of the second grounded negative field effect transistor are grounded; the second positive load resistor and the second negative load resistor are connected with a preset power supply.
In one embodiment, the multistage equalization circuit further includes: a third input positive field effect transistor, a third input negative field effect transistor and a cascade field effect transistor; the grid electrode of the third input positive field effect transistor is connected with the output end of the first low-pass filter, and the drain electrode of the third input positive field effect transistor is respectively connected with the drain electrode of the first input positive field effect transistor and the grid electrode of the second input negative field effect transistor in the second equalizer; the source electrode of the third input positive field effect transistor is respectively connected with the drain electrode of the cascade field effect transistor and the source electrode of the third input negative field effect transistor; the grid electrode of the third input negative field effect tube is connected with the output end of the second low-pass filter, and the drain electrode of the third input negative field effect tube is respectively connected with the drain electrode of the first input negative field effect tube and the grid electrode of the second input positive field effect tube in the second equalizer.
In one embodiment, the first low-pass filter comprises a first resistor and a first capacitor, one end of the first resistor is connected with the first output end of the second equalizer, the other end of the first resistor is respectively connected with one end of the first capacitor and the gate of the third input positive field effect transistor, and the other end of the first capacitor is grounded; the second low-pass filter comprises a second resistor and a second capacitor, one end of the second resistor is connected with the second output end of the second equalizer, the other end of the second resistor is respectively connected with one end of the second capacitor and the grid electrode of the third input negative field effect transistor, and the other end of the second capacitor is grounded.
In one embodiment, the first resistor has the same resistance value as the second resistor, and the first capacitor has the same capacitance value as the second capacitor.
In one embodiment, the first positive load resistor has the same resistance value as the first negative load resistor, and the second positive load resistor has the same resistance value as the second negative load resistor.
In one embodiment, the multistage equalization circuit further includes: the third equalizer is connected with the last equalizing coupling unit in a cascade way; the first input end of the third equalizer is respectively connected with the first output end of the second equalizer and the input end of the first low-pass filter in the cascaded equalizing coupling unit; and a second input end of the third equalizer is respectively connected with a second output end of the second equalizer and an input end of the second low-pass filter in the cascaded equalizing coupling unit.
In a second aspect, the present application further provides a signal processing circuit board, where the signal processing circuit board includes the multi-stage equalization circuit in the first aspect or any one of the possible implementations of the first aspect.
The application provides a multistage equalization circuit and a signal processing circuit board, the multistage equalization circuit comprises at least one equalization coupling unit which is in cascade connection, and each equalization coupling unit comprises a first equalizer, a second equalizer, a first low-pass filter and a second low-pass filter. The first equalizer and the second equalizer are used for gaining the attenuation signal; the first low-pass filter and the second low-pass filter are used for filtering the signal output by the second equalizer and feeding the filtered signal back to the output end of the first equalizer. When the equalization compensation gain is performed on the attenuation signal in the application, firstly, the first equalizer performs signal gain processing on the attenuation signal input from the input end, then the multistage equalization circuit performs operation processing on the signal after the gain of the first equalizer and the signal fed back by the low-pass filter, inputs the signal after the operation processing to the second equalizer for further gain, and finally outputs the signal after the gain of the second equalizer to the next coupling unit. The low-pass filter forms a feedback circuit, the signal after the gain of the second equalizer is subjected to low-pass filtering processing, the high-frequency signal is filtered, the filtering signal containing more low-frequency signals is fed back to the output end of the first equalizer, and the signal after the gain of the first equalizer and the filtering signal are subjected to subtraction operation at the circuit intersection point, so that more low-frequency signals are restrained, the equalization compensation bandwidth of the equalization coupling unit is improved, the equalization compensation gain of the equalization coupling unit is increased, and the further gain of the signal after the gain of the first equalizer is realized. The feedback loop formed by the first equalizer, the second equalizer, the first low-pass filter and the second low-pass filter realizes three-level gain of the attenuation signal, compared with the simple superposition of the gain of each equalizer in the prior art, the feedback loop has the advantages that the number of the equalizers is the same, the higher gain effect is achieved, on the basis of ensuring the requirement of the gain of the equalization compensation of the attenuation signal, the number of the equalizers contained in the whole multistage equalization circuit is less, the power consumption and the area of the multistage equalization circuit are effectively reduced, the manufacturing cost of the multistage equalization circuit is reduced, and meanwhile, the application range of the multistage equalization circuit is expanded.
Drawings
FIG. 1 is a diagram illustrating a cascaded configuration of two equalizers in one embodiment;
FIG. 2 is a schematic diagram of a multi-stage equalization circuit in one embodiment;
FIG. 3 is a schematic diagram of the circuit structure of an equalizer in one embodiment;
FIG. 4 is a graph of the amplitude, frequency, phase and frequency characteristics of an equalizer in one embodiment;
FIG. 5 is a schematic diagram of another embodiment of a multi-stage equalizer circuit;
fig. 6 is a schematic circuit diagram of an embodiment of an equalizing coupling unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the prior art, equalization technology is often used to compensate for the high frequency component of a signal, for example, a continuous time linear equalizer is used to compensate for the attenuation of the signal, so as to meet the requirement of distortion-free transmission. When the data transmission rate of a signal is continuously increased and the channel attenuation is continuously increased, a plurality of continuous time linear equalizers are generally cascaded, so that the gains of the plurality of equalizers are superposed to meet the requirement of signal compensation, for example, when two equalizers in the prior art shown in fig. 1 are cascaded, the effect of doubling the gain signal can be achieved. However, as the signal attenuation increases and the signal gain needs to be increased, the number of stages of the equalizer needs to be increased, for example, the number of the equalizers shown in fig. 1 is increased, so that the power consumption and the area of the whole equalization circuit are increased, the manufacturing cost of the equalization circuit is increased, and the application range of the equalization circuit is limited.
Based on this, the application provides a multistage equalizer circuit and a signal processing circuit board, on the basis of guaranteeing the requirement of the equalization compensation gain of the signal, the power consumption and the area of the whole equalizer circuit can be reduced, the manufacturing cost of the equalizer circuit is reduced, and the application range of the equalizer circuit is widened.
The multistage equalization circuit provided by the embodiment of the application can be applied to sound equipment, energy storage equipment, high-definition serial digital interface transmission equipment and other equipment, and can also be applied to any equipment needing signal gain. Optionally, the multistage equalization circuit provided by the embodiment of the present application may also be applied to a signal processing circuit board. The multi-stage equalization circuit provided by the embodiment of the application can be applied to physical equipment as a chip, and can also be applied to a virtual machine as a virtual integrated circuit. This is not limited by the present application.
In one embodiment, as shown in fig. 2, a multi-stage equalization circuit is provided, the multi-stage equalization circuit comprising at least one equalization coupling unit, each equalization coupling unit being connected in a cascade manner; each equalizing coupling unit comprises a first equalizer, a second equalizer, a first low-pass filter and a second low-pass filter;
in fig. 2, a parameter n is the number of equalizers in the multi-stage equalization circuit, the CTLE1 is a first-stage Continuous Time Linear Equalizer (CTLE), the CTLE2 is a second-stage continuous time linear equalizer, the CTLEn-1 is an n-1-stage continuous time linear equalizer, the CTLEn is an nth-stage continuous time linear equalizer, Vinp and Vinn are differential input signals of the CTLE1, V1p and V1n are differential output signals of the CTLE1, Vp and Vn are differential input signals of the CTLE2, V2p and V2n are differential output signals of the CTLE2, V0p is an output signal of a low-pass filter (low-pass filter) connected to the CTLE2, V0n is an output signal of another low-pass filter (LPF ) connected to the CTLE2, the output signal of the Voutp and the differential output signal of the lcutn are coupled units.
Each equalizing coupling unit is formed by cascading two equalizers, and includes two low-pass filters, for example, in fig. 2, the first equalizing coupling unit is formed by cascading equalizers CTLE1 and CTLE2 in sequence, and includes two LPFs, and the last equalizing coupling unit is formed by cascading equalizers CTLEn-1 and CTLEn in sequence, and includes two LPFs.
Based on each equalizing coupling unit, if the equalizing coupling unit is the first equalizing coupling unit in the multistage equalizing circuit, two input ends of the first equalizer of the equalizing coupling unit are respectively connected with the differentially input attenuated signals. For example, the first equalizer may have a first input terminal connected to the differential signal Vinp and a second input terminal connected to the differential signal Vinn. If the equalizing coupling unit is other equalizing coupling units except the first equalizing coupling unit in the multistage equalizing circuit, two input ends of the first equalizer of the equalizing coupling unit are respectively connected with two output ends of the second equalizer in the equalizing coupling unit which is connected in cascade and the input ends of two equalizing filters. For example, the first input terminal of the first equalizer of the equalizing coupling unit may be connected to the first output terminal of the second equalizer and the input terminal of the first low-pass filter in the equalizing coupling unit connected in cascade, and the second input terminal of the first equalizer may be connected to the second output terminal of the second equalizer and the input terminal of the second low-pass filter in the equalizing coupling unit connected in cascade. The input end of a first equalizer of the equalizing coupling unit is used for receiving an attenuated signal of differential input or a signal after the gain of the equalizing coupling unit which is connected in the last cascade, and the equalizing coupling unit is used for carrying out signal gain processing on the signal received by the first equalizer.
Two output ends of a first equalizer of the equalizing coupling unit are respectively connected with the output ends of the two low-pass filters and two input ends of a second equalizer. For example, a first output terminal of a first equalizer of the equalizing coupling unit may be connected to an output terminal of the first low-pass filter circuit and a first input terminal of a second equalizer, and a second output terminal of the first equalizer may be connected to an output terminal of the second low-pass filter circuit and a second input terminal of the second equalizer, respectively. The output end of the first equalizer of the equalizing coupling unit is used for outputting the signal after the gain of the first equalizer, and the output end of the first equalizer is connected with the output end of the low-pass filter and the input end of the second equalizer, so that the signal after the gain of the first equalizer and the signal fed back by the low-pass filter can be operated at the circuit intersection point, and the signal after the operation processing is output to the input end of the second equalizer. If the phase of the signal after the gain of the first equalizer is the same as that of the signal fed back by the low-pass filter, the operation of the signal after the gain of the first equalizer and the signal fed back by the low-pass filter at the circuit intersection point is addition operation; if the phase of the signal after the first equalizer gain is opposite to that of the signal fed back by the low-pass filter, the operation performed at the circuit intersection point by the two is subtraction, and at this time, Vp = V1p-V0p and Vn = V1n-V0 n. Optionally, in order to further gain the signal after the first equalizer is gained, the phases of the signal after the first equalizer is gained and the signal fed back by the low-pass filter may be opposite, so that the two signals are subtracted at the circuit intersection, thereby achieving the effects of suppressing the low-frequency signal, improving the equalization compensation bandwidth, and increasing the equalization compensation gain, and further gain the signal after the first equalizer is gained. Two output ends of the second equalizer of the equalizing coupling unit are respectively connected with two input ends of the first equalizer in the equalizing coupling unit which is connected in the next cascade connection, so that the signal transmission between the equalizing coupling units is realized. For example, a first output terminal of the second equalizer may be connected to a first input terminal of a first equalizer in the equalizing coupling unit of the next cascade connection, and a second output terminal of the second equalizer may be connected to a second input terminal of the first equalizer in the equalizing coupling unit of the next cascade connection.
Based on the whole multi-stage equalization circuit, the input end of a first equalizer in a first equalization coupling unit of the multi-stage equalization circuit is used for receiving an input signal, and the output end of a second equalizer in the last equalization coupling unit is used for outputting a gain signal obtained by performing gain processing on the input signal by the multi-stage equalization circuit.
Alternatively, the equalizers in fig. 2 may be equalizers of any type of structure, such as the equalizer structure commonly used in the art as shown in fig. 3, where R isDIs a load resistance, CLIs a load capacitance, gmFor field effect transistors, the transconductance, R, of the field effect transistor may be characterizedSAs a feedback resistance, CSFor feedback capacitance, ISSIs a current source, VinIs the input of the equalizer, VoutIs the output of the equalizer. The amplitude-frequency characteristic curve and the phase-frequency characteristic curve of the equalizer are shown in fig. 4, wherein the first curve is the amplitude-frequency characteristic curve of the equalizer, the second curve is the phase-frequency characteristic curve of the equalizer,ω Z in order to be the zero point of the equalizer,ω P1 andω P2 is the pole of the equalizer and the zero of the equalizerω Z The calculation method of (2) is shown in the following formula (1):
poles of the equalizerω P1 The calculation method of (2) is shown in the following formula:
poles of the equalizerω P2 The calculation method of (2) is shown in the following formula (3):
equalizers use zerosω Z And poleω P1 The gain between the two is increased to compensate the channel.
The multistage equalization circuit provided by the embodiment of the application comprises at least one equalization coupling unit, wherein the equalization coupling units are connected in a cascade mode; each equalizing coupling unit includes a first equalizer, a second equalizer, a first low pass filter, and a second low pass filter. The first equalizer and the second equalizer are used for gaining the attenuation signal; the first low-pass filter and the second low-pass filter are used for filtering the signal output by the second equalizer and feeding the filtered signal back to the output end of the first equalizer. When the equalization compensation gain is performed on the attenuation signal in the application, firstly, the first equalizer performs signal gain processing on the attenuation signal input from the input end, then the multistage equalization circuit performs operation processing on the signal after the gain of the first equalizer and the signal fed back by the low-pass filter, inputs the signal after the operation processing to the second equalizer for further gain, and finally outputs the signal after the gain of the second equalizer to the next coupling unit. This application constitutes feedback circuit through low pass filter, carry out low pass filtering with the signal behind the second equalizer gain, filter out high frequency signal, will contain the filtered signal feedback of more low frequency signal to the output of first equalizer, make the signal behind the first equalizer gain and filtered signal after the circuit crossing point department carries out the operation back, the gain signal of first equalizer final output can restrain more low frequency signal, realized the further gain to the signal behind the first equalizer gain, the equalization compensation bandwidth of this equalization coupling unit has been improved, the equalization compensation gain of this equalization coupling unit has been increased. The feedback loop formed by the first equalizer, the second equalizer, the first low-pass filter and the second low-pass filter realizes three-level gain of the attenuation signal, compared with the simple superposition of the gain of each equalizer in the prior art, the feedback loop has the advantages that the number of the equalizers is the same, the higher gain effect is achieved, on the basis of ensuring the requirement of the gain of the equalization compensation of the attenuation signal, the number of the equalizers contained in the whole multistage equalization circuit is less, the power consumption and the area of the multistage equalization circuit are effectively reduced, the manufacturing cost of the multistage equalization circuit is reduced, and meanwhile, the application range of the multistage equalization circuit is expanded.
In practical applications, in each equalizing coupling unit in fig. 2, there are two possibilities of addition and subtraction operations performed at the circuit intersection by the signal after the gain of the first equalizer and the signal fed back by the low-pass filter. In order to increase the equalization compensation bandwidth of the equalization coupling unit and increase the equalization compensation gain of the equalization coupling unit, it is necessary to ensure that the operation performed at the circuit intersection between the signal after the first equalizer gain and the signal fed back by the low-pass filter is subtraction. Therefore, a subtracter can be arranged in each equalizing coupling unit to ensure the subtraction effect at the intersection of the circuits. Based on this, the present application further provides a multistage equalization circuit including a subtractor, as shown in fig. 5, and based on the circuit shown in fig. 2, each equalization coupling unit in this embodiment may further include: a first subtractor and a second subtractor. Wherein the first subtractor and the second subtractor are identified in fig. 5 using the letter J. Two input ends of any subtracter can be respectively connected with one output end of the first equalizer and the output end of any low-pass filter, and the output end of any subtracter can be connected with any input end of the second equalizer; two input terminals of the further subtractor may be respectively connected to the further output terminal of the first equalizer and the output terminal of the further low-pass filter, and an output terminal of the further subtractor may be connected to the further input terminal of the second equalizer. For example, a first input terminal of the first subtractor is connected to a first output terminal of the first equalizer, a second input terminal of the first subtractor is connected to an output terminal of the first low-pass filter, and an output terminal of the first subtractor is connected to a first input terminal of the second equalizer; the first input end of the second subtracter is connected with the second output end of the first equalizer, the second input end of the second subtracter is connected with the output end of the second low-pass filter, and the output end of the second subtracter is connected with the second input end of the second equalizer. In a specific implementation, the subtractor may receive the signal after the gain of the first equalizer and the signal fed back by the low-pass filter from the input end, perform subtraction on the two signals, and output the operation result from the output end to the input end of the second equalizer.
In the embodiment of the application, each equalizing coupling unit in the multistage equalizing circuit may further include a first subtractor and a second subtractor. The input end of the subtracter is connected with the output end of the first equalizer and the output end of the low-pass filter, and is used for receiving the signals after the gain of the first equalizer and the signals fed back by the low-pass filter and carrying out subtraction operation processing on the two signals; the output end of the subtracter is connected with the input end of the second equalizer and used for inputting the signal after the subtraction operation to the second equalizer. Therefore, in the embodiment of the application, the subtracter is added into each equalizing coupling unit to ensure that the operation of the signal after the gain of the first equalizer and the signal fed back by the low-pass filter at the circuit intersection is subtraction operation, so that the effect of inhibiting the low-frequency signal is achieved, the equalizing compensation bandwidth of the equalizing coupling units is improved, and the equalizing compensation gain is increased.
The equalizing coupling unit according to the foregoing embodiment may include a first equalizer, a second equalizer, a first low pass filter, and a second low pass filter. In the following embodiments, different circuit modules will be described by taking the circuit configuration shown in fig. 6 as an example.
In one embodiment, as shown in fig. 6, the first equalizer may include a first input positive fet Mp1, a first input negative fet Mn1, a first grounded positive fet Ms1p, a first grounded negative fet Ms1n, a first positive load resistor Rp1, a first negative load resistor Rn1, a first feedback resistor R1, and a first feedback capacitor C1. The drain of the first input positive field effect transistor Mp1 is connected to the first positive load resistor Rp1, and the source of the first input positive field effect transistor Mp1 is connected to the first feedback resistor R1, the first feedback capacitor C1 and the drain of the first grounded positive field effect transistor Ms1 p; the gate and source of the first grounded positive field effect transistor Ms1p are grounded; the drain electrode of the first input negative field effect transistor Mn1 is respectively connected with a first negative load resistor Rn1, and the source electrode of the first input negative field effect transistor Mn1 is respectively connected with the drain electrodes of a first feedback resistor R1, a first feedback capacitor C1 and a first grounding negative field effect transistor Ms1 n; the grid electrode and the source electrode of the first grounding negative field effect tube Ms1n are grounded; the first positive load resistor Rp1 and the first negative load resistor Rn1 are connected to a preset power supply. In order to ensure symmetry of the first equalizer, the first positive load resistor Rp1 and the first negative load resistor Rn1 may have the same resistance value.
Vinp and Vinn may be attenuated signals, or may be output signals of a second equalizer of an upper stage of the equalizing coupling unit connected in cascade to the equalizing coupling unit. When Vinp and Vinn are input into the equalizing coupling unit, the signals can be respectively input into a first equalizer of the equalizing coupling unit from the gates of the first input positive fet Mp1 and the first input negative fet Mn1, and the first equalizer can perform signal gain processing on the Vinp and Vinn and output the signals after gain from the drains of the first input positive fet Mp1 and the first input negative fet Mn 1.
The circuit structure of the second equalizer is substantially the same as that of the first equalizer, for example, referring to the structure shown in fig. 6, the second equalizer may include a second input positive fet Mp2, a second input negative fet Mn2, a second ground field positive fet Ms2p, a second ground negative fet Ms2n, a second positive load resistor Rp2, a second negative load resistor Rn2, a second feedback resistor R2, and a second feedback capacitor C2. The drain of the second input positive field effect transistor Mp2 is respectively connected to the second positive load resistor Rp2, and the source of the second input positive field effect transistor Mp2 is respectively connected to the second feedback resistor R2, the second feedback capacitor C2 and the drain of the second grounded positive field effect transistor Ms2 p; the gate and the source of the second grounded positive field effect transistor Ms2p are grounded; the drain electrode of the second input negative field effect transistor Mn2 is respectively connected with the second negative load resistor Rn2, and the source electrode of the second input negative field effect transistor Mn2 is respectively connected with the drain electrodes of the second feedback resistor R2, the second feedback capacitor C2 and the second grounding negative field effect transistor Ms2 n; the gate and the source of the second grounded negative field effect transistor Ms2n are grounded; the second positive load resistor Rp2 and the second negative load resistor Rn2 are connected to a preset power supply. In order to ensure symmetry of the second equalizer, the resistance values of the second positive load resistor Rp2 and the second negative load resistor Rn2 may be the same.
The second equalizer may perform signal gain processing on signals input from the gates of the second input positive fet Mp2 and the second input negative fet Mn2, and output the signals after gain from the drains of the second input positive fet Mp2 and the second input negative fet Mn2, respectively.
In one embodiment, as shown in fig. 6, the first low-pass filter may include a first resistor Rf1 and a first capacitor Cf1, one end of the first resistor Rf1 is connected to the first output terminal of the second equalizer, the other end of the first resistor Rf1 is connected to one end of the first capacitor Cf1 and the gate of the third input positive field effect transistor, respectively, and the other end of the first capacitor Cf1 is grounded; when the first gain signal output from the first output terminal of the second equalizer is input to the first low-pass filter from one end of the first resistor Rf1, the first low-pass filter may perform low-pass filtering processing on the first gain signal to filter out high-frequency components of the first gain signal, so that the low-pass filtered first gain signal includes more low-frequency components, and output the low-pass filtered first gain signal from the output terminal of the first low-pass filter.
The second low-pass filter may include a second resistor Rf2 and a second capacitor Cf2, one end of the second resistor Rf2 is connected to the second output terminal of the second equalizer, the other end of the second resistor Rf2 is connected to one end of the second capacitor Cf2 and the gate of the third input negative field effect transistor, respectively, and the other end of the second capacitor Cf2 is grounded. When the second gain signal output from the second output terminal of the second equalizer is input to the second low-pass filter from one end of the second resistor Rf2, the second low-pass filter may perform low-pass filtering processing on the second gain signal to filter out high-frequency components of the second gain signal, so that the low-pass filtered second gain signal includes more low-frequency components, and output the low-pass filtered second gain signal from the output terminal of the second low-pass filter.
In order to ensure the symmetry of the circuit, the resistance values of the first resistor Rf1 and the second resistor Rf2 may be the same, and the capacitance values of the first capacitor Cf1 and the second capacitor Cf2 may be the same.
In the foregoing embodiment, it is described that the operation performed at the circuit intersection by the subtractor to ensure that the signal after the first equalizer gain and the signal fed back by the low-pass filter are subtracted, and the subtractor in the embodiment of the present application may be composed of two field effect transistors with opposite phases. Based on this application, there is also provided an equalizing unit for implementing subtraction, as shown in fig. 6, each equalizing unit in the multistage equalizing circuit may further include: a third input positive fet Mp3, a third input negative fet Mn3, and a cascode fet Ms 3. The grid electrode of the third input positive field effect tube Mp3 is connected with the output end of the first low-pass filter, and the drain electrode of the third input positive field effect tube Mp3 is respectively connected with the drain electrode of the first input positive field effect tube Mp1 and the grid electrode of the second input negative field effect tube Mn2 in the second equalizer; the source electrode of the third input positive field effect transistor Mp3 is respectively connected with the drain electrode of the cascade field effect transistor and the source electrode of the third input negative field effect transistor Mn 3; the gate of the third input negative fet Mn3 is connected to the output of the second low-pass filter, and the drain of the third input negative fet Mn3 is connected to the drain of the first input negative fet Mn1 and the gate of the second input positive fet Mp2 in the second equalizer, respectively.
The drain of the third input positive fet Mp3 is connected to the gate of the second input negative fet Mn2 in the second equalizer, and the drain of the third input negative fet Mn3 is connected to the gate of the second input positive fet Mp2 in the second equalizer, where the two connections are the cascade connection between the first equalizer and the second equalizer in the equalizing coupling unit.
If the phase of the attenuated signal is x radians, the phases of the first input positive fet Mp1 and the third input positive fet Mp3 may be opposite, that is, the phase of the signal is unchanged after being output from the first input positive fet Mp1, and the phase of the signal is changed to (x + 180) radians after being output from the third input positive fet Mp 3; the phase of the signal output from the third input positive fet Mp3 may be constant, and the phase of the signal output from the first input positive fet Mp1 may be (x + 180) radians. Optionally, when the phase of the signal output from the first input positive fet Mp1 is unchanged and the phase of the signal output from the third input positive fet Mp3 is changed to (x + 180) radian, the phase of the signal after the gain of the first equalizer output from the drain of the first input positive fet Mp1 is unchanged, and the phase of the signal after the low-pass filtering output from the drain is changed to (x + 180) radian from the gate of the third input positive fet Mp3, an operation performed at a circuit intersection point of the signal output from the first output terminal of the first equalizer and the signal after the filtering processing by the phase-reversed first low-pass filter at the drain terminal of the third input positive fet Mp3 is an operation that is the signal output from the first output terminal of the first equalizer minus the signal after the filtering processing by the first low-pass filter.
The phases of the first input negative fet Mn1 and the third input negative fet Mn3 may be opposite, that is, the phase of the signal is unchanged after the signal is output from the first input negative fet Mn1, and the phase of the signal is changed to (x + 180) radians after the signal is output from the third input negative fet Mn 3; the phase of the signal output from the third input negative fet Mn3 may be constant, and the phase of the signal output from the first input negative fet Mn1 may be (x + 180) radians. Optionally, when the phase of the signal output from the first input negative fet Mn1 is unchanged and the phase of the signal output from the third input negative fet Mn3 is changed to (x + 180) radian, the phase of the signal after the gain of the first equalizer output from the drain of the first input negative fet Mn1 is unchanged, and the phase of the signal after the low-pass filtering output from the drain of the third input negative fet Mn3 is changed to (x + 180) radian, and the operation performed at the circuit intersection point of the signal output from the second output terminal of the first equalizer and the signal after the filtering processing by the phase-reversed second low-pass filter at the drain terminal of the third input negative fet Mn3 is the signal after the filtering processing by the second low-pass filter subtracted from the signal output from the second output terminal of the first equalizer.
In this embodiment, each equalizing coupling unit in the multistage equalizing circuit may further include a third input positive fet, a third input negative fet, and a cascade fet. The third input positive field effect transistor and the first input positive field effect transistor have opposite phases to form a first subtracter; the third input negative field effect tube and the first input negative field effect tube have opposite phases to form a second subtracter. In this embodiment of the present application, the first input positive fet or the third input positive fet may invert the phase of the signal output by the first output terminal of the first equalizer or the phase of the signal filtered by the first low-pass filter, so that the phases of the two signals are opposite, so that the two signals perform subtraction operation at the intersection of the circuits; the first input negative field effect transistor or the third input negative field effect transistor may invert the phase of the signal output by the second output terminal of the first equalizer or the phase of the signal filtered by the second low-pass filter, so that the two signals have opposite phases, so that the two signals perform subtraction at the intersection of the two circuits. In other words, in the embodiment of the application, the phases of the signal after the gain of the first equalizer and the signal fed back by the low-pass filter are opposite through the field effect transistors with opposite phases, so that the operation performed at the intersection of the two circuits is a subtraction operation, an effect of suppressing a low-frequency signal is achieved, the equalization compensation bandwidth of the equalization coupling unit is improved, and the equalization compensation gain is increased.
In the embodiments described above, it is described that the multistage equalizing circuit includes at least one equalizing coupling unit, and each equalizing coupling unit includes two equalizers. That is, if the number of equalizers in the multistage equalization circuit is even m, the number of equalizing coupling units in the multistage equalization circuit is 0.5 × m. However, if the number of the equalizers in the multi-stage equalizing circuit is an odd number n, the multi-stage equalizing circuit has one more equalizer, and the number of the equalizing coupling units is 0.5 (n-1). Considering the case where the number of equalizers in the multistage equalizing circuit is odd,
in one embodiment, in consideration of the case where the number of equalizers in the multi-stage equalizing circuit is an odd number, the multi-stage equalizing circuit may further include: the third equalizer is connected with the last equalizing coupling unit in a cascade way; and two input ends of the third equalizer are respectively connected with two output ends of the second equalizer and input ends of the two low-pass filters in the cascaded equalizing coupling unit. For example, the first input terminal of the third equalizer may be respectively connected to the first output terminal of the second equalizer and the input terminal of the first low-pass filter in the cascaded equalizing coupling units; and a second input end of the third equalizer is respectively connected with a second output end of the second equalizer and an input end of the second low-pass filter in the cascaded equalizing coupling unit. When the third equalizer receives signals output by two output ends of the second equalizer of the cascaded equalizing coupling unit from the gates of the first input end and the second input end, the third equalizer can perform signal gain processing on the signals and output the signals after gain from the drains of the first input end and the second input end. The signal after the gain is the signal after the attenuation signal gains in the multistage equalization circuit.
The embodiment of the application provides a specific structure of the multi-stage equalization circuit under the condition that the number of equalizers in the multi-stage equalization circuit is odd. When the number of the equalizers in the multistage equalizing circuit is even, the multistage equalizing circuit comprises at least one equalizing coupling unit; when the number of the equalizers in the multistage equalizing circuit is odd, the multistage equalizing circuit comprises at least one equalizing coupling unit and a third equalizer. It can be seen that the structure of the multi-stage equalization circuit in the present application can be flexibly set according to the number of equalizers, and the application range of the multi-stage equalization circuit is increased.
In one embodiment, the gain process for attenuating signals in the present application is explained based on the circuit structure of the balanced coupling unit shown in fig. 6. Vinp and Vinn are input from the first input terminal and the second input terminal (i.e., the gates of Mp1 and Mn 1) of the first equalizer of the equalizing coupling unit as attenuated signals or output signals of the second equalizer of the preceding equalizing coupling unit cascade-connected to the equalizing coupling unit. The first equalizer performs gain processing on the received signal to obtain a signal after the first equalizer gains, and outputs the signal from the first output terminal and the second output terminal (i.e., the drains of Mp1 and Mn 1). The first low pass filter and the second low pass filter perform low pass filtering processing on signals output from two output ends of the second equalizer, filter out high frequency signals, and feed back filtered signals containing more low frequency signals to the gates of Mp3 and Mn 3. The Mp3 and Mn3 perform phase inversion on the filtered signal, and output the filtered signal after phase inversion to two output ends of the first equalizer, so that the signal after gain of the first equalizer and the filtered signal are subtracted at the circuit intersection point of the drain ends of the Mp1 and Mn1, thereby achieving the effect of suppressing low-frequency signals, improving the equalization compensation bandwidth of the equalization coupling unit, increasing the equalization compensation gain of the equalization coupling unit, and realizing further gain, namely two-level gain, of the signal after gain of the first equalizer. The multistage equalizing circuit inputs the signals further gained by the subtracter from the first and second output terminals (i.e., the gates of Mp2 and Mn 2) of the second equalizer to the second equalizer, the second equalizer performs gain processing (i.e., three-stage gain) on the signals after the two-stage gain, and outputs the signals after the gain processing from the first and second output terminals (i.e., the drains of Mp2 and Mn 2). The output signal is the result of the balanced coupling unit after performing gain processing on Vinp and Vinn. The equalizing coupling unit in the present application realizes a three-level gain effect of a signal based on two equalizers, and compared with a simple superposition of two equalizer gains in the prior art, the multistage equalizing circuit provided in the embodiment of the present application can achieve a higher gain effect with the equalizers of the same number, and on the basis of ensuring the requirement of the equalizing compensation gain of an attenuated signal, the number of the equalizers included in the whole multistage equalizing circuit is less, so that the power consumption and the area of the multistage equalizing circuit are effectively reduced, the manufacturing cost of the multistage equalizing circuit is reduced, and the application range of the multistage equalizing circuit is expanded.
Based on the same inventive concept, the embodiment of the application also provides a signal processing circuit board. The signal processing circuit board comprises the multistage equalization circuit in the embodiment. The implementation scheme for solving the problem provided by the signal processing circuit board is similar to the implementation scheme described in the multi-stage equalization circuit, so specific limitations in the embodiments of one or more signal processing circuit boards provided below can be referred to the limitations of the multi-stage equalization circuit in the above, and details are not described here.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. A multi-stage equalization circuit, comprising: the balanced coupling units are connected in a cascading mode; each equalizing coupling unit comprises a first equalizer, a second equalizer, a first low-pass filter and a second low-pass filter;
in each of the equalizing coupling units, a first input end of the first equalizer is connected to a first output end of a second equalizer in one of the equalizing coupling units connected in cascade and an input end of the first low-pass filter, respectively, and a second input end of the first equalizer is connected to a second output end of the second equalizer in one of the equalizing coupling units connected in cascade and an input end of the second low-pass filter, respectively;
a first output end of the first equalizer is respectively connected with an output end of the first low-pass filter circuit and a first input end of the second equalizer; a second output end of the first equalizer is respectively connected with an output end of the second low-pass filter circuit and a second input end of the second equalizer;
a first output end of the second equalizer is connected with a first input end of a first equalizer in the equalizing coupling unit of the next cascade connection, and a second output end of the second equalizer is connected with a second input end of the first equalizer in the equalizing coupling unit of the next cascade connection;
the input end of the first equalizer in the first equalizing coupling unit receives input signals, and the output end of the second equalizer in the last equalizing coupling unit outputs gain signals.
2. The circuit of claim 1, wherein each of the balanced coupling units further comprises: a first subtractor and a second subtractor;
a first input end of the first subtractor is connected with a first output end of the first equalizer, a second input end of the first subtractor is connected with an output end of the first low-pass filter, and an output end of the first subtractor is connected with a first input end of the second equalizer;
and a first input end of the second subtracter is connected with a second output end of the first equalizer, a second input end of the second subtracter is connected with an output end of the second low-pass filter, and an output end of the second subtracter is connected with a second input end of the second equalizer.
3. The circuit of claim 1, wherein the first equalizer comprises: the device comprises a first input positive field effect tube, a first input negative field effect tube, a first grounding positive field effect tube, a first grounding negative field effect tube, a first positive load resistor, a first negative load resistor, a first feedback resistor and a first feedback capacitor;
the drain electrode of the first input positive field effect transistor is respectively connected with the first positive load resistor, and the source electrode of the first input positive field effect transistor is respectively connected with the first feedback resistor, the first feedback capacitor and the drain electrode of the first grounding positive field effect transistor; the grid electrode and the source electrode of the first grounding positive field effect transistor are grounded;
the drain electrode of the first input negative field effect transistor is respectively connected with the first negative load resistor, and the source electrode of the first input negative field effect transistor is respectively connected with the first feedback resistor, the first feedback capacitor and the drain electrode of the first grounding negative field effect transistor; the grid electrode and the source electrode of the first grounded negative field effect transistor are grounded;
the first positive load resistor and the first negative load resistor are connected with a preset power supply.
4. The circuit of claim 2, wherein the second equalizer comprises: the second input positive field effect transistor, the second input negative field effect transistor, the second grounding field positive effect transistor, the second grounding negative field effect transistor, the second positive load resistor, the second negative load resistor, the second feedback resistor and the second feedback capacitor;
the drain electrode of the second input positive field effect transistor is respectively connected with the second positive load resistor, and the source electrode of the second input positive field effect transistor is respectively connected with the second feedback resistor, the second feedback capacitor and the drain electrode of the second grounding positive field effect transistor; the grid electrode and the source electrode of the second grounded positive field effect transistor are grounded;
the drain electrode of the second input negative field effect transistor is respectively connected with the second negative load resistor, and the source electrode of the second input negative field effect transistor is respectively connected with the second feedback resistor, the second feedback capacitor and the drain electrode of the second grounding negative field effect transistor; the grid electrode and the source electrode of the second grounded negative field effect transistor are grounded;
and the second positive load resistor and the second negative load resistor are connected with a preset power supply.
5. The circuit of claim 4, wherein the multi-stage equalization circuit further comprises: a third input positive field effect transistor, a third input negative field effect transistor and a cascade field effect transistor;
the grid electrode of the third input positive field effect transistor is connected with the output end of the first low-pass filter, and the drain electrode of the third input positive field effect transistor is respectively connected with the drain electrode of the first input positive field effect transistor and the grid electrode of the second input negative field effect transistor in the second equalizer; the source electrode of the third input positive field effect transistor is respectively connected with the drain electrode of the cascade field effect transistor and the source electrode of the third input negative field effect transistor;
and the grid electrode of the third input negative field effect tube is connected with the output end of the second low-pass filter, and the drain electrode of the third input negative field effect tube is respectively connected with the drain electrode of the first input negative field effect tube and the grid electrode of the second input positive field effect tube in the second equalizer.
6. The circuit according to claim 5, wherein the first low-pass filter comprises a first resistor and a first capacitor, one end of the first resistor is connected to the first output end of the second equalizer, the other end of the first resistor is connected to one end of the first capacitor and the gate of the third input positive field effect transistor, respectively, and the other end of the first capacitor is grounded;
the second low-pass filter comprises a second resistor and a second capacitor, one end of the second resistor is connected with the second output end of the second equalizer, the other end of the second resistor is respectively connected with one end of the second capacitor and the grid electrode of the third input negative field effect transistor, and the other end of the second capacitor is grounded.
7. The circuit of claim 6, wherein the first resistor has the same resistance value as the second resistor, and wherein the first capacitor has the same capacitance value as the second capacitor.
8. The circuit of claim 6 or 7, wherein the first positive load resistance has the same resistance value as the first negative load resistance, and wherein the second positive load resistance has the same resistance value as the second negative load resistance.
9. The circuit of claim 1, wherein the multi-stage equalization circuit further comprises: the third equalizer is connected with the last equalizing coupling unit in a cascade way; the first input end of the third equalizer is respectively connected with the first output end of the second equalizer and the input end of the first low-pass filter in the cascaded equalizing coupling unit; and a second input end of the third equalizer is respectively connected with a second output end of a second equalizer in the cascaded equalizing coupling units and an input end of a second low-pass filter.
10. A signal processing circuit board comprising a multi-stage equalization circuit as claimed in any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210249965.9A CN114337597B (en) | 2022-03-15 | 2022-03-15 | Multistage equalization circuit and signal processing circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210249965.9A CN114337597B (en) | 2022-03-15 | 2022-03-15 | Multistage equalization circuit and signal processing circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114337597A true CN114337597A (en) | 2022-04-12 |
| CN114337597B CN114337597B (en) | 2022-05-27 |
Family
ID=81033597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210249965.9A Active CN114337597B (en) | 2022-03-15 | 2022-03-15 | Multistage equalization circuit and signal processing circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114337597B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117591065A (en) * | 2023-11-24 | 2024-02-23 | 北京国科天迅科技股份有限公司 | Signal processing circuit, signal processing method and signal processing chip |
| CN118041260A (en) * | 2024-04-11 | 2024-05-14 | 芯耀辉科技有限公司 | Signal processing method for front-end circuit and front-end circuit |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6104236A (en) * | 1998-04-17 | 2000-08-15 | Advanced Micro Devices, Inc. | Apparatus and method for equalizing received network signals using a transconductance controlled biquadratic equalizer |
| CN101459632A (en) * | 2007-12-12 | 2009-06-17 | 林武 | Adaptive equalizing circuit and method |
| CN201797511U (en) * | 2009-08-27 | 2011-04-13 | 中兴通讯股份有限公司 | Adaptive equalizer |
| CN102480271A (en) * | 2010-11-24 | 2012-05-30 | 阿尔特拉公司 | Offset cancellation for continuous-time circuits |
| CN106209709A (en) * | 2016-07-15 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of linear equalizer being applicable to HSSI High-Speed Serial Interface |
| CN108141189A (en) * | 2015-10-12 | 2018-06-08 | 高通股份有限公司 | The device and method being combined for the electric current to the passive equalizer in sensing amplifier |
| CN111131101A (en) * | 2019-12-28 | 2020-05-08 | 苏州芯动科技有限公司 | Feedback equalization circuit |
| CN113422586A (en) * | 2021-07-07 | 2021-09-21 | 南方科技大学 | High-energy-efficiency equalizer architecture |
-
2022
- 2022-03-15 CN CN202210249965.9A patent/CN114337597B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6104236A (en) * | 1998-04-17 | 2000-08-15 | Advanced Micro Devices, Inc. | Apparatus and method for equalizing received network signals using a transconductance controlled biquadratic equalizer |
| CN101459632A (en) * | 2007-12-12 | 2009-06-17 | 林武 | Adaptive equalizing circuit and method |
| CN201797511U (en) * | 2009-08-27 | 2011-04-13 | 中兴通讯股份有限公司 | Adaptive equalizer |
| CN102480271A (en) * | 2010-11-24 | 2012-05-30 | 阿尔特拉公司 | Offset cancellation for continuous-time circuits |
| CN108141189A (en) * | 2015-10-12 | 2018-06-08 | 高通股份有限公司 | The device and method being combined for the electric current to the passive equalizer in sensing amplifier |
| CN106209709A (en) * | 2016-07-15 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of linear equalizer being applicable to HSSI High-Speed Serial Interface |
| CN111131101A (en) * | 2019-12-28 | 2020-05-08 | 苏州芯动科技有限公司 | Feedback equalization circuit |
| CN113422586A (en) * | 2021-07-07 | 2021-09-21 | 南方科技大学 | High-energy-efficiency equalizer architecture |
Non-Patent Citations (1)
| Title |
|---|
| 周振宇等: "一种适用于高速接口电路的新型均衡电路", 《微电子学与计算机》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117591065A (en) * | 2023-11-24 | 2024-02-23 | 北京国科天迅科技股份有限公司 | Signal processing circuit, signal processing method and signal processing chip |
| CN118041260A (en) * | 2024-04-11 | 2024-05-14 | 芯耀辉科技有限公司 | Signal processing method for front-end circuit and front-end circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114337597B (en) | 2022-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8117249B1 (en) | Equalizer systems and methods utilizing analog delay elements | |
| US20060001504A1 (en) | High bandwidth high gain receiver equalizer | |
| CN114337597B (en) | Multistage equalization circuit and signal processing circuit board | |
| Machha Krishna et al. | Widely tunable low‐pass gm− C filter for biomedical applications | |
| Reddy | Operational-amplifier circuits with variable phase shift and their application to high-Q active RC-filters and RC-oscillators | |
| GB2243966A (en) | Active filters | |
| US7180939B2 (en) | Active filter circuit with dynamically modifiable internal gain | |
| El-Gamal et al. | LC ladder-based synthesis of log-domain bandpass filters | |
| Mahmoud et al. | Digitally programmable second generation current conveyor‐based FPAA | |
| CN110233600B (en) | Amplifier circuit and compensation circuit | |
| US20190097845A1 (en) | Continuous time linear equalizer | |
| Fukada | Optimum filters of even orders with monotonic response | |
| US8183921B1 (en) | Offset cancellation for continuous-time circuits | |
| EP0744829B1 (en) | A high-pass filter, particularly for cancelling out the offset in a chain of amplifiers | |
| US6313687B1 (en) | Variable impedance circuit | |
| Khateb et al. | 0.5 v universal filter based on multiple-input FDDAs | |
| US20060088086A1 (en) | Reverse scaling for improved bandwidth in equalizers | |
| El-Gamal et al. | Balanced log-domain filters for VHF applications | |
| Akbari et al. | Multi-path class AB operational amplifier with high performance for SC circuits | |
| Hegde et al. | Series-cascade nonlinear adaptive filters | |
| US11177984B1 (en) | CMOS analog circuits having a triode-based active load | |
| JP4945350B2 (en) | Electric dispersion compensation equalization circuit | |
| JP3953540B2 (en) | High pass filter | |
| Mulder et al. | A generalized class of dynamic translinear circuits | |
| KR100213240B1 (en) | Filter with dual input mutual conductance amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 701, 7th Floor, Building 6, Courtyard 8, Kegu 1st Street, Beijing Economic and Technological Development Zone, Daxing District, Beijing, 100176 Patentee after: Beijing Tasson Technology Ltd. Address before: Room 701, 7 / F, building 6, courtyard 8, KEGU 1st Street, Beijing Economic and Technological Development Zone, Daxing District, Beijing 100176 Patentee before: BEIJING TASSON TECHNOLOGY Ltd. |
|
| CP03 | Change of name, title or address |