CN111131101A - Feedback equalization circuit - Google Patents
Feedback equalization circuit Download PDFInfo
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- CN111131101A CN111131101A CN201911382754.7A CN201911382754A CN111131101A CN 111131101 A CN111131101 A CN 111131101A CN 201911382754 A CN201911382754 A CN 201911382754A CN 111131101 A CN111131101 A CN 111131101A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03178—Arrangements involving sequence estimation techniques
- H04L25/03248—Arrangements for operating in conjunction with other apparatus
- H04L25/03254—Operation with other circuitry for removing intersymbol interference
- H04L25/03267—Operation with other circuitry for removing intersymbol interference with decision feedback equalisers
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Abstract
The invention discloses a feedback equalization circuit which comprises a subtraction circuit, a comparison circuit, a level conversion circuit, a filter circuit and a gain adjustment circuit. The subtracting circuit subtracts the feedback signal from the input signal to obtain an equalized signal. The comparison circuit compares the equalized signals to obtain data signals. The level conversion circuit converts the data signal from a digital signal into a low-swing analog signal, the signal is filtered by the filter circuit, and then the gain is adjusted by the gain adjustment circuit to obtain a feedback signal. The invention provides a low-cost feedback equalization circuit which can perform frequency compensation on a high-speed signal attenuated by a channel and is suitable for a receiver circuit of a high-speed interface.
Description
Technical Field
The invention belongs to the technical field of equalizers, and particularly relates to a feedback equalization circuit.
Background
High-speed interface circuits are widely used for interconnection of various electronic devices and data communication. With the continuous development of the fields of communication, internet, multimedia and the like, the requirement on the channel bandwidth of a high-speed interface is higher and higher, and the signal speed is higher and higher.
The high-speed interface circuit is divided into a transmitting end circuit and a receiving end circuit which are connected through a channel, and comprises a board-level connecting wire, a cable and the like. The channel has certain attenuation to high-speed signals, the degree of signal attenuation of different frequencies is different, and the higher the frequency is, the greater the signal attenuation is. When a high-speed signal transmitted by a transmitting end reaches a receiving end after being attenuated by a channel, the signal quality is deteriorated, and the receiving end needs to perform frequency compensation on the received signal by adopting an equalizer circuit, so that the attenuation of a high-frequency signal is compensated, and the signal quality is improved, so that data can be correctly recovered.
The receiving end equalizer circuit mainly comprises a continuous time domain linear equalizer (CTLE), a Decision Feedback Equalizer (DFE), a finite impulse response equalizer and the like. The receiving end can select an equalizer or adopt the combined mode of several equalizers to compensate the signal attenuation according to the channel attenuation degree. Among them, the decision feedback equalizer usually works in a discrete time domain, and needs a plurality of taps to be combined, and one tap compensates for one feedback interference (post-cursor ISI). Thus, the greater the attenuation, the more taps are needed, the more feedback loops, and the greater the circuit cost.
Disclosure of Invention
In view of the above drawbacks and needs of the prior art, the present invention provides a feedback equalizer circuit, which operates in a continuous time domain, and only uses one feedback loop to compensate for all feedback interferences, and can replace the conventional decision feedback equalizer circuit with low circuit cost.
To achieve the above object, according to one aspect of the present invention, there is provided a feedback equalization circuit including a subtraction circuit, a comparison circuit, a level conversion circuit, a filter circuit, and a gain adjustment circuit; the first input end of the subtraction circuit is used for receiving an input signal of the feedback equalization circuit, the output end of the subtraction circuit is connected with the input end of the comparison circuit, and the output end of the comparison circuit is used for outputting an output signal of the feedback equalization circuit; the level conversion circuit is used for performing level conversion on an output signal of the feedback equalization circuit, generating a conversion signal and outputting the conversion signal to the filter circuit, the filter circuit is used for filtering the conversion signal, generating a filter signal and outputting the filter signal to the gain adjustment circuit, the gain adjustment circuit is used for performing gain adjustment on the filter signal, generating a feedback signal and outputting the feedback signal to the second input end of the subtraction circuit, the subtraction circuit is used for generating an equalization signal according to an input signal and a feedback signal of the feedback equalization circuit and outputting the equalization signal to the comparison circuit, and the comparison circuit is used for comparing the equalization signal, generating an output signal of the feedback equalization circuit and outputting the output signal.
In some embodiments, the level shift circuit is configured to perform level shift on an output signal of the feedback equalization circuit, generate a shift signal, and output the shift signal to the filter circuit, specifically: the level conversion circuit processes the output signal of the feedback equalization circuit, converts the output signal from a digital level signal into an analog level signal, and outputs the analog level signal as a conversion signal to adapt to the voltage input range of the filter circuit.
In some embodiments, the order or coefficient of the filter circuit is adjustable, and the frequency response of the filter circuit is adjusted by adjusting the order or coefficient of the filter circuit.
In some embodiments, the frequency response of the feedback equalization circuit is adjusted by adjusting the frequency response of the filter circuit.
In some embodiments, the order or coefficient of the filter circuit is adjusted according to different operating frequency requirements, so that the feedback equalization circuit operates in an optimal frequency response state.
In some embodiments, the gain adjustment circuit varies the voltage amplitude of the feedback signal by adjusting the gain of the filtered signal.
In some embodiments, the gain adjustment circuit adjusts the gain of the filtered signal according to different channel attenuation requirements.
In some embodiments, the subtracting circuit is configured to generate an equalized signal according to the input signal and the feedback signal of the feedback equalizing circuit, and output the equalized signal to the comparing circuit specifically includes: the subtracting circuit subtracts the feedback signal from the input signal of the feedback equalizing circuit in the time domain, and realizes frequency compensation of the input signal of the feedback equalizing circuit according to the feedback signal in the frequency domain to generate an equalizing signal.
In some embodiments, the subtraction circuit, the level conversion circuit and the gain adjustment circuit are implemented using a current mode logic circuit design, and the filter circuit is implemented using a first-order low-pass filter design.
In some embodiments, the subtraction circuit and the gain adjustment circuit share a circuit node.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects: and only one feedback loop is adopted, so that the compensation of all feedback interference is realized, and the circuit cost is low. The frequency response of the filter circuit can be adjusted by adjusting the order or coefficient of the filter circuit, so that the frequency response of the whole feedback equalization circuit can be adjusted to adapt to different working frequency requirements. The amplitude of frequency compensation can be adjusted by adjusting the gain of the gain adjusting circuit, and different channel attenuation amplitude requirements can be met.
Drawings
Fig. 1 is a schematic structural diagram of a feedback equalization circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a frequency domain model of a feedback equalization circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of the frequency response of the feedback equalization circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1, the feedback equalization circuit of the embodiment of the present invention includes a subtraction circuit, a comparison circuit, and a feedback circuit. The first input end of the subtraction circuit is used for receiving an input signal of the feedback equalization circuit, the output end of the subtraction circuit is connected with the input end of the comparison circuit, the output end of the comparison circuit is used for outputting an output signal of the feedback equalization circuit, the output end of the comparison circuit is further connected with the input end of the feedback circuit, and the output end of the feedback circuit is connected with the second input end of the subtraction circuit.
The feedback circuit is used for processing the output signal of the feedback equalization circuit, generating a feedback signal and outputting the feedback signal to the subtraction circuit.
In some embodiments, the feedback circuit includes a level shift circuit, a filtering circuit, and a gain adjustment circuit. The input end of the level conversion circuit forms the input end of the feedback circuit, the output end of the level conversion circuit is connected with the input end of the filter circuit, the output end of the filter circuit is connected with the input end of the gain adjustment circuit, and the output end of the gain adjustment circuit forms the output end of the feedback circuit.
The level conversion circuit is used for carrying out level conversion on the output signal of the feedback equalization circuit and outputting the conversion signal to the filter circuit. In some embodiments, the level shift circuit processes the output signal of the feedback equalization circuit to convert the output signal from a digital level signal into a low swing analog level signal, and outputs the analog level signal as a shift signal to adapt to the voltage input range of the filter circuit.
The filter circuit is used for filtering the conversion signal output by the level conversion circuit and outputting a filter signal to the gain adjustment circuit. In some embodiments, the order or coefficient of the filter circuit is adjustable, and the frequency response of the filter circuit is adjusted by adjusting the order or coefficient of the filter circuit. In some embodiments, the frequency response of the feedback equalization circuit is adjusted by adjusting the frequency response of the filter circuit. In some embodiments, the order or coefficient of the filter circuit is adjusted according to different operating frequency requirements, so that the feedback equalization circuit operates in an optimal frequency response state.
The gain adjusting circuit is used for carrying out gain adjustment on the filtering signal output by the filtering circuit and outputting a feedback signal to the second input end of the subtraction circuit. In some embodiments, the gain adjustment circuit varies the voltage magnitude of the feedback signal output by the filter circuit by adjusting the gain of the filtered signal. In some embodiments, the gain adjustment circuit adjusts the gain of the filtered signal output by the filtering circuit according to different channel attenuation requirements.
The subtracting circuit is used for generating an equalizing signal according to the input signal of the feedback equalizing circuit and the feedback signal output by the feedback circuit and outputting the equalizing signal to the comparing circuit. In some embodiments, the subtraction circuit subtracts the feedback signal from the input signal in the time domain, and performs frequency compensation on the input signal based on the feedback signal in the frequency domain to generate the equalized signal.
The comparison circuit is used for comparing the equalization signals output by the subtraction circuit, generating output signals of the feedback equalization circuit and outputting the output signals.
The frequency domain model of the feedback equalization circuit in connection with the embodiment of the present invention is explained below.
As shown in FIG. 2, the frequency domain model of the feedback equalization circuit of the embodiment of the present invention includes a subtraction circuit transfer function AS(s) comparing the circuit transfer function ACLevel shift circuit transfer function AL(s) Filter Circuit transfer function AF(s) and gain adjustment circuit transfer function AG(s). The transfer function of the feedback equalization circuit is:
further, to simplify the analysis, in some embodiments, the subtraction circuit, the level shift circuit, and the gain adjustment circuit in the feedback equalization circuit are implemented by using a CML (Current Mode Logic) circuit design, and the filter circuit is implemented by using a first-order low-pass filter design. Taking the above conditions as an example, the transfer function of the subtraction circuit, the transfer function of the level conversion circuit, the transfer function of the gain adjustment circuit, and the transfer function of the filter circuit are all first-order systems, and only one pole exists in the transfer functions, so that the transfer function of the feedback equalization circuit is:
further, to simplify the analysis, in some embodiments, the subtracting circuit and the gain adjusting circuit in the feedback equalization circuit share a circuit node, so that the poles in the two transfer functions are the same, and the magnitude of the pole of the level shifting circuit is the largest, and the influence of the pole of the level shifting circuit can be ignored. Taking the above conditions as an example, then ωL>ωS＝ωG>ωFTherefore, the transfer function of the feedback equalization circuit can be simplified as follows:
the simplified transfer function is a second-order system, 1 zero and two poles exist, and the approximate calculation is respectively as follows:
ωz＝ωF
ωp1≈(l+ACALAFAG)·ωF
ωp2＝ωS
taking the above conditions as an example, then ωp2>ωp1>ωzThe frequency response of the feedback equalization circuit is shown in fig. 3. The feedback equalization circuit responds to low-frequency signals as a direct-current gain and has frequency higher than omegazHas an amplifying effect on a high-frequency signal with a frequency greater than omegap2The signal of (2) starts to attenuate, the central frequency of the signal amplification frequency interval is at omegap1And ωp2In the meantime. Therefore, the feedback equalization circuit can compensate the attenuation of the high frequency signal by the channel. On one hand, the pole of the filter circuit can be adjusted according to the working frequency of the input signal, and then omega is adjustedzAnd ωp1And a signal amplification frequency interval of the feedback equalization circuit; on the other hand, the gain of the gain adjusting circuit to the signal can be adjusted according to the attenuation amplitude of the channel to the high-frequency signal, and then the signal gain of the feedback equalization circuit is adjusted.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A feedback equalization circuit is characterized by comprising a subtraction circuit, a comparison circuit, a level conversion circuit, a filter circuit and a gain adjustment circuit; the first input end of the subtraction circuit is used for receiving the input signal of the feedback equalization circuit, the output end of the subtraction circuit is connected with the input end of the comparison circuit, and the output end of the comparison circuit is used for outputting the output signal of the feedback equalization circuit; the level conversion circuit is configured to perform level conversion on an output signal of the feedback equalization circuit, generate a conversion signal, and output the conversion signal to the filter circuit, the filter circuit is configured to filter the conversion signal, generate a filter signal, and output the filter signal to the gain adjustment circuit, the gain adjustment circuit is configured to perform gain adjustment on the filter signal, generate a feedback signal, and output the feedback signal to a second input end of the subtraction circuit, the subtraction circuit is configured to generate an equalization signal according to an input signal of the feedback equalization circuit and the feedback signal, and output the equalization signal to the comparison circuit, and the comparison circuit is configured to compare the equalization signal, generate an output signal of the feedback equalization circuit, and output the output signal.
2. The feedback equalization circuit according to claim 1, wherein the level shift circuit is configured to shift a level of the output signal of the feedback equalization circuit, generate a shift signal, and output the shift signal to the filter circuit, specifically: the level conversion circuit processes the output signal of the feedback equalization circuit, converts the output signal from a digital level signal into an analog level signal, and outputs the analog level signal as a conversion signal to adapt to the voltage input range of the filter circuit.
3. The feedback equalization circuit of claim 1 wherein the order or coefficient of the filtering circuit is adjustable, and wherein the frequency response of the filtering circuit is adjusted by adjusting the order or coefficient of the filtering circuit.
4. The feedback equalization circuit of claim 3 wherein the frequency response of the feedback equalization circuit is adjusted by adjusting the frequency response of the filter circuit.
5. The feedback equalization circuit of claim 4 wherein the order or coefficient of the filter circuit is adjusted to operate the feedback equalization circuit in an optimal frequency response based on different operating frequency requirements.
6. The feedback equalization circuit of any of claims 1-5 wherein the gain adjustment circuit varies the voltage magnitude of the feedback signal by adjusting the gain of the filtered signal.
7. The feedback equalization circuit of claim 6 wherein the gain adjustment circuit adjusts the gain of the filtered signal according to different channel attenuation requirements.
8. The feedback equalization circuit according to any one of claims 1 to 5, wherein the subtraction circuit is configured to generate an equalized signal from the input signal of the feedback equalization circuit and the feedback signal, and output the equalized signal to the comparison circuit specifically: the subtracting circuit subtracts the feedback signal from the input signal of the feedback equalizing circuit in the time domain, and implements frequency compensation on the input signal of the feedback equalizing circuit according to the feedback signal in the frequency domain to generate the equalized signal.
9. The feedback equalization circuit of any of claims 1-8 wherein the subtraction circuit, the level shift circuit, and the gain adjustment circuit are implemented using a current mode logic circuit design, and the filtering circuit is implemented using a first order low pass filter design.
10. The feedback equalization circuit of claim 9 wherein said subtraction circuit and said gain adjustment circuit share a circuit node.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113595946A (en) * | 2021-07-07 | 2021-11-02 | 苏州瀚宸科技有限公司 | Compensation method and device for real pole of any left half plane |
| CN114070683A (en) * | 2022-01-11 | 2022-02-18 | 长芯盛（武汉）科技有限公司 | Method for realizing adaptive equalization and adaptive equalizer |
| CN114337597A (en) * | 2022-03-15 | 2022-04-12 | 北京国科天迅科技有限公司 | Multistage equalization circuit and signal processing circuit board |
| CN117539817A (en) * | 2024-01-09 | 2024-02-09 | 上海韬润半导体有限公司 | Serial signal transmission adjusting circuit, device and adjusting method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1669282A (en) * | 2002-07-18 | 2005-09-14 | 高通股份有限公司 | Method and apparatus for hybrid decision feedback equalization |
| CN101826848A (en) * | 2010-04-15 | 2010-09-08 | 复旦大学 | Automatic gain control system in orthogonal frequency division multiplexing receiver and method |
| CN106877820A (en) * | 2017-01-12 | 2017-06-20 | 广州市迪声音响有限公司 | A kind of dynamic changes the equalizing system and method for EQ Gain |
| US20180048494A1 (en) * | 2016-08-10 | 2018-02-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | DeSerializer DC Offset Adaptation Based On Decision Feedback Equalizer Adaptation |
-
2019
- 2019-12-28 CN CN201911382754.7A patent/CN111131101B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1669282A (en) * | 2002-07-18 | 2005-09-14 | 高通股份有限公司 | Method and apparatus for hybrid decision feedback equalization |
| CN101826848A (en) * | 2010-04-15 | 2010-09-08 | 复旦大学 | Automatic gain control system in orthogonal frequency division multiplexing receiver and method |
| US20180048494A1 (en) * | 2016-08-10 | 2018-02-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | DeSerializer DC Offset Adaptation Based On Decision Feedback Equalizer Adaptation |
| CN106877820A (en) * | 2017-01-12 | 2017-06-20 | 广州市迪声音响有限公司 | A kind of dynamic changes the equalizing system and method for EQ Gain |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113595946A (en) * | 2021-07-07 | 2021-11-02 | 苏州瀚宸科技有限公司 | Compensation method and device for real pole of any left half plane |
| CN113595946B (en) * | 2021-07-07 | 2024-01-30 | 苏州瀚宸科技有限公司 | Compensation method and device for real pole of arbitrary left half plane |
| CN114070683A (en) * | 2022-01-11 | 2022-02-18 | 长芯盛（武汉）科技有限公司 | Method for realizing adaptive equalization and adaptive equalizer |
| US11792053B2 (en) | 2022-01-11 | 2023-10-17 | EverPro Technologies Company Limited | Method of realization of adaptive equalization and adaptive equalizer |
| CN114337597A (en) * | 2022-03-15 | 2022-04-12 | 北京国科天迅科技有限公司 | Multistage equalization circuit and signal processing circuit board |
| CN117539817A (en) * | 2024-01-09 | 2024-02-09 | 上海韬润半导体有限公司 | Serial signal transmission adjusting circuit, device and adjusting method |
| CN117539817B (en) * | 2024-01-09 | 2024-04-05 | 上海韬润半导体有限公司 | Serial signal transmission adjusting circuit, device and adjusting method |
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