CN114323083A - Hall sensing device and electronic equipment - Google Patents
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Abstract
The application discloses hall sensing device and electronic equipment, hall sensing device includes: the all-polar Hall sensing module is used for detecting an external magnetic field, comparing the external magnetic field with a south-pole magnetic field threshold and a north-pole magnetic field threshold respectively, and outputting a corresponding south-pole comparison signal and a corresponding north-pole comparison signal; the switching module is connected to the all-polarity Hall sensing module and used for receiving the south pole comparison signal and the north pole comparison signal and sequentially and alternately outputting the south pole comparison signal and the north pole comparison signal; and the noise reduction logic module is connected to the output end of the switching module and is used for outputting a control signal after carrying out noise reduction processing on the south pole comparison signal and the north pole comparison signal which are sequentially received. The sensitivity of the Hall sensing device is improved, and stable and reliable signal output can be realized.
Description
Technical Field
The application relates to the technical field of Hall sensing, in particular to a Hall sensing device and electronic equipment.
Background
The Hall device is a magnetic sensor manufactured based on the Hall effect principle, the Hall effect is one of electromagnetic effects, when current passes through a conductor in a direction perpendicular to an external magnetic field, an additional electric field is generated in the conductor in a direction perpendicular to the current and the magnetic field, so that a potential difference is generated at two ends of the conductor, the phenomenon is the Hall effect, and the potential difference is called as Hall potential difference.
The Hall sensor is integrated with the Hall device, has the characteristics of low power consumption, high sensitivity, high input and output isolation and the like, and is widely applied to the fields of industry, communication, instrument manufacturing and the like. The Hall sensor switch circuit is widely applied to the fields of industry, communication, instrument manufacturing and the like. Please refer to fig. 1, which is a functional diagram of a bipolar hall switch. And when the magnetic field intensity on the chip surface is greater than the south magnetic field threshold value BOPS or the north magnetic field BOPN, the output of the Hall switch is changed from high level to low level.
In the prior art, the sensitivity of the hall switch needs to be further improved.
Disclosure of Invention
In view of this, the present application provides a hall sensing device and an electronic apparatus to improve the sensitivity of the hall sensing device.
The application provides a hall sensing device includes: the all-polar Hall sensing module is used for detecting an external magnetic field, comparing the external magnetic field with a south-pole magnetic field threshold and a north-pole magnetic field threshold respectively, and outputting a corresponding south-pole comparison signal and a corresponding north-pole comparison signal; the switching module is connected to the all-polarity Hall sensing module and used for receiving the south pole comparison signal and the north pole comparison signal and sequentially and alternately outputting the south pole comparison signal and the north pole comparison signal; and the noise reduction logic module is connected to the output end of the switching module and is used for outputting a control signal after carrying out noise reduction processing on the south pole comparison signal and the north pole comparison signal which are sequentially received.
Optionally, the noise reduction logic module includes a noise reduction unit, and the noise reduction unit is configured to output the south pole comparison signal when N1 consecutive south pole comparison signals are the same, and output the north pole comparison signal when N2 consecutive north pole comparison signals are the same.
Optionally, the noise reduction unit includes an (N1+ N2) shift register and a comparison unit connected to each output terminal of the shift register; the (N1+ N2) bit shift register is used for outputting the N1 south pole comparison signals and the N2 north pole comparison signals which are sequentially and alternately output by the switching module as (N1+ N2) bit comparison signals in parallel under the control of a first clock signal; the comparison unit is used for outputting high level as a clock signal when N1-bit south pole comparison signals and N2-bit north pole comparison signals output by the shift register are the same.
Optionally, the shift register includes (N1+ N2) flip-flops, an output end and an input end of which are sequentially connected, wherein an input end of a leading flip-flop is connected to an output end of the all-polarity hall sensing module, and output ends of the two flip-flops are further respectively connected to two input ends of the logic operation unit, and are used for respectively outputting a south pole comparison signal and a north pole comparison signal.
Optionally, the comparing unit includes two sub-comparing units and a clock signal generating sub-unit; one sub-comparison unit is connected to the output end of the south pole comparison signal of the shift register and used for comparing whether the south pole comparison signals are the same or not, and the other sub-comparison unit is connected to the output end of the north pole comparison signal of the shift register and used for comparing whether the north pole comparison signals are the same or not; the clock signal generating subunit is connected to the output ends of the two sub-comparison units, and is configured to perform and operation on the output signals of the two sub-comparison units, and output an operation result as a third clock signal.
Optionally, the sub-comparison unit includes an or gate, a first nand gate, and a second nand gate, wherein the input ends of the or gate and the first nand gate are both connected to the output end of the corresponding comparison signal of the shift register, and the output ends of the or gate and the first nand gate are both connected to the input end of the second nand gate.
Optionally, the clock signal generating sub-unit includes an and gate, the and gate is connected to an output end of a second nand gate of the two sub-comparison units, and performs and operation on signals output by the two sub-comparison units under the control of a second clock signal, and outputs an operation result as a third clock signal.
Optionally, the rising edge time of the second clock signal is located between every (N1+ N2) rising edges of the first clock signal.
Optionally, the noise reduction logic module further includes a logic operation unit, and the logic operation unit is connected to the output end of the noise reduction unit, and is configured to perform logic operation on the south pole comparison signal and the north pole comparison signal output by the noise reduction unit; wherein N1 and N2 are both integers of 2 or more.
Optionally, the logic operation is an exclusive nor operation, and when the level of any received comparison signal is inverted, the level of the control signal is inverted.
Optionally, the logical operation unit includes: two flip-flops and an exclusive-nor gate; the input ends of the two triggers are respectively connected to the two output ends of the noise reduction unit, the output ends of the two triggers are respectively connected to the input ends of the exclusive OR gate, the two triggers are used for respectively receiving the south pole comparison signal and the north pole comparison signal output by the noise reduction unit, and the exclusive OR gate outputs the control signal after exclusive OR operation.
Optionally, the all-polar hall sensing module includes a south-pole hall sensing unit and a north-pole hall sensing unit; the south pole Hall sensing unit is used for outputting a south pole comparison signal of an external magnetic field and a south pole magnetic field threshold, and the north pole Hall sensing unit is used for outputting a north pole comparison signal of the external magnetic field and a north pole magnetic field threshold.
Optionally, the switching module includes two switches, one of the switches is connected to a connection path between the south pole hall sensing unit and the input end of the noise reduction logic module, and the other switch is connected to a connection path between the north pole hall sensing unit and the input end of the noise reduction logic module.
The present application further provides an electronic device, comprising: the hall sensing device of any preceding claim.
The Hall sensing device can perform noise reduction logic processing on the south pole comparison signal and the north pole comparison signal output by the Hall sensing module, improves sensitivity, solves the problem that the magnetic field threshold is unstable due to external magnetic field jitter, and outputs stable and reliable control signals.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a functional schematic of a prior art all-polarity Hall sensor switch;
FIG. 2 is a schematic diagram of the noise of the Hall voltage caused by the external magnetic field jitter;
FIG. 3 is a schematic structural diagram of a Hall sensing device according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a Hall sensing device according to an embodiment of the present application;
FIG. 5 is a diagram showing the distribution of noise of Hall voltage caused by the jitter of external magnetic field;
fig. 6 is a schematic structural diagram of an all-polar hall sensing module of a hall sensing device according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a partial circuit structure of a Hall sensing device according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a partial circuit structure of a Hall sensing device according to an embodiment of the present application;
fig. 9 is a timing diagram of respective switch control signals and clock signals of a hall sensing device according to an embodiment of the present application.
Detailed Description
As described in the background art, the sensitivity of the existing hall sensor device is to be further improved.
Hall element output Hall voltage VHThe reference voltage Vref is a Hall voltage V corresponding to the magnetic field threshold valueHThe value is obtained. When the external magnetic field of the Hall sensor switch is the magnetic field threshold value, A.VH-Vref-0, a is the amplification of the hall voltage.
In practice, it is necessary to consider the image due to the magnetic field fluctuationLoud sounds, A.VH-Vref+Vnoise＝0，VnoiseA noise signal of the hall voltage generated by the amount of magnetic field dither. Since the magnetic field jitter is a random process, the noise V of the Hall voltage is generatednoiseThe amplitude of the comparator is positive or negative (please refer to fig. 2), when the hall sensor is in the threshold magnetic field, the flip point of the comparator is uncertain due to the existence of noise, and the accuracy of the switch is influenced. Under the conditions of low voltage and high temperature, the sensitivity of the Hall is reduced, the circuit noise is increased, and the effective Hall voltage VHReduction of noise VnoiseBecoming larger makes the problem of uncertainty in the flip point of the comparator worse.
The invention provides a novel Hall sensing device which can filter noise caused by shaking of a part of magnetic field, ensure stable and reliable switching and improve sensitivity.
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Fig. 3 is a schematic structural diagram of a hall sensor device according to an embodiment of the invention.
The hall sensing device includes a full-polarity hall sensing module 110, a switching module 130, and a noise reduction logic module 120.
The all-polar hall sensing module 110 is configured to detect an external magnetic field, compare the external magnetic field with a south-pole magnetic field threshold and a north-pole magnetic field threshold, and output a corresponding south-pole comparison signal Vo1 and a corresponding north-pole comparison signal Vo 2. When the external magnetic field reaches the corresponding magnetic field threshold, the output comparison signal is inverted, the comparison signal is 0 (low) or1 (high level), and the inversion of the comparison signal includes the inversion from 0 to 1 or the inversion from 1 to 0.
The south and north magnetic fields refer to only two oppositely directed magnetic fields, and the south and north poles do not necessarily correspond exactly to the geographical north and south poles.
The all-polar hall sensing module 110 includes hall elements, and can generate corresponding hall voltages according to the variation of an external magnetic field. In this embodiment, the hall element is a hall disk, the hall element is a square hall disk, and the two pairs of signal ends are at two sets of opposite vertex angles, respectively. The magnetic field sensor is provided with two pairs of signal terminals, wherein one pair of signal terminals are used as two control terminals, are connected to a control voltage terminal and are used for inputting control voltage, and the other pair of signal terminals are used as two output terminals and are used for outputting sensing signals related to an external magnetic field. In an embodiment of the present invention, the all-polar hall sensing module 110 includes two hall elements, which are respectively used for sensing a south magnetic field and a north magnetic field, so as to respectively generate a hall voltage corresponding to the south magnetic field and a hall voltage generated by the north magnetic field, and compare the hall voltages with corresponding threshold voltages, thereby outputting corresponding comparison signals. In this embodiment, the two control terminals and the two output terminals are respectively located at two opposite vertex angles of the square hall disk, and the phase difference between the control current direction between the control terminals and the induced current phase between the output terminals is 90 °.
The switching module 130 is connected to the output end of the all-polar hall sensing module 110, and is configured to receive the south pole comparison signal and the north pole comparison signal, and output the south pole comparison signal and the north pole comparison signal in sequence and alternately.
The noise reduction logic module 120 is connected to the output end of the switching module 130, and is configured to perform noise reduction processing on the south pole comparison signal Vo1 and the north pole comparison signal Vo2 received in sequence, and output a control signal. The noise reduction processing may include denoising, and further logic processing.
By reducing noise, part of noise caused by magnetic field jitter can be filtered, so that the sensitivity of the Hall sensing device is improved, and the stability of an output signal is improved.
Fig. 4 is a schematic structural diagram of a hall sensor device according to an embodiment of the invention.
In this embodiment, the all-polar hall sensing module 110 includes a south-pole hall sensing unit 111 and a north-pole hall sensing unit 112, where the south-pole hall sensing unit 111 is configured to sense a south-pole magnetic field, compare the south-pole magnetic field with a south-pole magnetic field threshold, and output a south-pole comparison signal Vo 1; the north hall sensor unit 112 is configured to sense a north magnetic field, compare the sensed north magnetic field with a threshold north magnetic field, and output a north comparison signal Vo 2.
The switching module 130 includes a switch S1 and a switch S2, the switch S1 is connected to a connection path between the output terminal of the south hall sensor unit 111 and the input terminal of the noise reduction logic module 120, and the switch S2 is connected to a path between the north hall sensor unit 112 and the input terminal of the noise reduction logic module 120. By sequentially switching the on-off states of the switch S1 and the switch S2, the south pole comparison signal Vo1 and the north pole comparison signal Vo2 are alternately output in sequence.
The noise reduction logic module 120 includes a noise reduction unit 121, where the noise reduction unit 121 is configured to output the south pole comparison signal when N1 consecutive south pole comparison signals are the same, and output the north pole comparison signal when N2 consecutive north pole comparison signals are the same.
The noise reduction logic module 120 further includes a logic operation unit 122, where the logic operation unit 122 is connected to the output end of the noise reduction unit 121, and is configured to perform logic operation on the noise-reduced south and north pole comparison signals output by the noise reduction unit 121, and output a control signal VO; wherein N1 and N2 are both integers of 2 or more.
Since the noise distribution in the circuit conforms to the normal distribution, as shown in fig. 5. The standard deviation σ in a normal distribution is:
effective value of noise UN_rmsComprises the following steps:
wherein Y (i) is n sample values obtained by noise sampling, and Y is an average value of the n sample values. It can be found that when the sampling point n is large:
σ≈UN_rms。
from the above formula and the confidence interval distribution based on the normal distribution, when the number of the sampling points is 3, when the amplitude of the noise Vnoise is Vn ≦ 2 σ, the maximum occurrence probability is P1 ≦ 68.2%, and the maximum occurrence probability is P13 ≦ 31.7% when the effective value Vn of the noise is to be continued three times ≦ 2 σ. When the amplitude of the noise is Vn less than or equal to 4 sigma, the maximum occurrence probability is P2-95.4%, and the maximum occurrence probability is P23-86.8% when the effective value Vn of the noise is less than or equal to 4 sigma for three consecutive times. When the amplitude of the noise is Vn less than or equal to 6 sigma, the maximum occurrence probability is 99.6% for P3, the effective value Vn less than or equal to 6 sigma for three consecutive times, and the maximum occurrence probability is 98.9% for P33, it can be seen from the above analysis that when the noise is large, the probability of continuously generating noise is high, which may cause the comparison signal to be unstable for a plurality of consecutive times; when the noise is small, the probability of continuously generating the noise is small, and the comparison signal is stable after being continuously repeated. Therefore, when the comparison signal is the same for a plurality of consecutive times, the noise is relatively small in probability, and the noise in the output comparison signal is usually relatively small, so that the noise can be filtered.
The higher the number of times of the signals are continuously the same, the lower the noise is, in some embodiments, N1 is more than or equal to 3, and N2 is more than or equal to 3, so as to obtain higher noise reduction effect. Further, in order to achieve the same noise reduction effect on the south and north magnetic fields, N1 is N2. In this embodiment, N1 ═ N3 ═ 3.
The logical operation unit 122 is configured to perform an exclusive nor operation, that is: when the external magnetic field is smaller than the south magnetic field threshold and the north magnetic field threshold at the same time, VO is 1 (high level), otherwise, the external magnetic field is larger than any one of the magnetic field thresholds, and VO is 0 (low level), thereby implementing the switching signal function as shown in fig. 1.
The logic operation can be various logic operation forms such as exclusive nor operation, latch logic operation and the like, and the skilled person can carry out reasonable design according to actual needs.
Because the signal operated by the logic operation unit 122 has smaller noise and larger effective signal ratio, the hall sensing device has higher sensing sensitivity to the external effective magnetic field signal, the switching point of the output control signal is more accurate, and the signal is more stable.
Fig. 6 is a schematic structural diagram of an all-polarity hall sensing module in a hall sensing device according to an embodiment of the present invention.
The hall sensing module 110 includes a south hall sensing unit 111 and a north hall sensing unit 112.
Specifically, the south pole hall sensing unit 111 includes: hall disk 1, amplifier AMP1, comparator CMP 1. Two opposite signal terminals H1 and H3 of the Hall disc 1 are used as signal control terminals, the signal terminal H1 is connected to a power supply VDD, and the signal terminal H2 is grounded; two other signal terminals H2, H4 are used as signal output terminals, wherein the signal terminal H4 is connected to the positive input terminal of the amplifier AMP1, the signal terminal H2 is connected to the negative input terminal of the amplifier AMP1, and the amplifier AMP1 is configured to amplify and output the hall voltage VH output by the hall disk 1. An output terminal of the amplifier AMP1 is connected to a positive input terminal of the comparator CMP1, and a negative input terminal of the comparator CMP1 is connected to a reference voltage Vref for comparing the hall voltage with the reference voltage and outputting a comparison signal Vo 1. The reference voltage Vref corresponds to the Hall voltage which can be generated by the Hall plate 1 under the south magnetic field threshold BOPS.
Accordingly, the north hall sensor unit 112 includes the hall disk 2, an amplifier AMP2, and a comparator CMP 2. Two opposite signal terminals H2 and H4 of the Hall disc 1 are used as signal control terminals, the signal terminal H2 is connected to a power supply VDD, and the signal terminal H4 is grounded; the other two signal terminals H1, H3 are used as signal output terminals, wherein the signal terminal H3 is connected to the positive input terminal of the amplifier AMP2, the signal terminal H1 is connected to the negative input terminal of the amplifier AMP1, and the amplifier AMP2 is used for amplifying and outputting the hall voltage-VH (opposite to the hall voltage generated by the hall disk 1) output by the hall disk 2. An output terminal of the amplifier AMP2 is connected to a positive input terminal of the comparator CMP2, and a negative input terminal of the comparator CMP2 is connected to a reference voltage Vref for comparing the hall voltage with the reference voltage and outputting a comparison signal Vo 2. The reference voltage Vref corresponds to a hall voltage that can be generated by the hall disk 2 at a north magnetic field threshold BOPN. The control current direction between the two control ends of the Hall disc 1 and the Hall disc 2 forms 90 degrees for inducing two magnetic fields which are vertical to each other.
In this embodiment, the north magnetic field threshold BOPN and the south magnetic field threshold BOPS have the same absolute value and opposite directions, and therefore correspond to the same reference voltage Vref. In other embodiments, the north magnetic field threshold BOPN and the south magnetic field threshold BOPS may have different absolute values, and the comparator CMP1 and the comparator CMP2 are respectively connected to reference voltages with different magnitudes.
Fig. 7 is a schematic structural diagram of a noise reduction logic module of a hall sensor device according to an embodiment of the present invention.
In this embodiment, the noise reduction logic module 120 includes a noise reduction unit 121 and a logic operation unit 122.
The noise reduction unit 121 includes an (N1+ N2) shift register and a comparison unit connected to respective output terminals of the shift register; the (N1+ N2) shift register is configured to output, in parallel, N1 south pole comparison signals and N2 north pole comparison signals, which are sequentially output in series by the all-polar hall sensing module 110, as (N1+ N2) bit comparison signals under the control of a first clock signal; the comparison unit is used for outputting high level as a clock signal when N1-bit south pole comparison signals and N2-bit north pole comparison signals output by the shift register are the same.
In this embodiment, N1 ═ N2 ═ 3 is taken as an example. The noise reduction unit 121 includes a 6-bit shift register, the shift register includes 6 flip-flops, i.e., flip-flops T1 to T6, in which an input end D1 of the first flip-flop T1 is connected to the output end of the all-polarity hall sensing module 110, and an output end of the flip-flop T1 is connected to an input end D2 of the last flip-flop T2, and the flip-flops are connected in sequence. The clock terminals C1 to C6 of the flip-flops T1 to T6 are all connected to a first clock signal CK1, and each flip-flop outputs an input terminal signal when the first clock signal CK1 rises.
Referring to fig. 9, a timing diagram of the control signals and the clock signals of the switches of the hall sensor device is shown.
The high level of each switch control signal corresponds to the switch being on and the low level corresponds to the switch being off. Specifically, the switches S1 and S2 sequentially switch the switch states to sequentially output the south pole comparison signal and the north pole comparison signal to the noise reduction logic module 120.
During each on time of the switch S1 and the switch S2 of the switching module 130, the first clock signal CK1 generates a rising edge, the switch S1 and the switch S2 are sequentially turned on 3 times, and the three south pole comparison signal Vo1 and the three north pole comparison signal Vo2 are output to the noise reduction unit 121 in total, and at the sixth rising edge of the first clock signal CK1, the 6 flip-flops in the six-bit shift register simultaneously output the 6 comparison signals in parallel. Taking the timing chart in fig. 9 as an example, at the sixth rising edge of the first clock signal CK1, the flip-flops T6, T4, T2 output the south pole comparison signal Vo1, and the flip-flops T5, T3, T1 output the north pole comparison signal Vo 2.
The noise reduction unit 121 further includes a comparison unit, where the comparison unit includes two sub-comparison units and a clock signal generation sub-unit, and the two sub-comparison units are respectively used to be connected to the south pole comparison signal and the north pole comparison signal output ends of the shift register.
The two sub-comparison units are respectively a first sub-comparison unit and a second sub-comparison unit, the first sub-comparison unit is used for comparing whether the comparison signals of each north pole are the same, and the second sub-comparison unit is used for comparing whether the comparison signals of each south pole are the same.
Specifically, in this embodiment, the first sub-comparing unit includes an OR gate OR1, a NAND gate NAND1, and a NAND gate NAND2, and the inputs of the OR gate OR1 and the NAND gate NAND1 are connected to the output of the corresponding comparison signal of the shift register. In this embodiment, the inputs of the OR gate OR1 and the NAND gate NAND1 are connected to the outputs of the flip-flops T1, T3 and T5, respectively, for receiving the north pole comparison signal Vo 2; the outputs of the OR gate OR1 and NAND gate NAND1 are both connected to the input of the NAND gate NAND 2. The output signals of the flip-flops T1, T3 and T5 are Q1, Q3 and Q5 respectively, the output signal of the NAND2 is Y1,
the truth table for Y1 is as follows:
| Q1 | Q3 | Q5 | Y1 |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
only when Q1, Q3, Q5 are simultaneously 0 or1, Y1 is 1. Q1, Q3, and Q5 are north pole comparison signals which are three consecutive times, and if there is an influence of noise at the time of the north pole magnetic field threshold BOPN comparison, the values of Q1, Q3, and Q5 are not continuously equal. Therefore, when the values of Q1, Q3, and Q5 are the same, the noise is small.
Similarly, the second sub-comparison unit comprises an OR gate OR2, a NAND gate NAND3 and a NAND gate NAND4, and the inputs of the OR gate OR2 and the NAND gate NAND3 are connected to the output of the corresponding comparison signal of the shift register. In this embodiment, the inputs of the OR gate OR2 and the NAND gate NAND3 are connected to the outputs of the flip-flops T2, T4 and T6, respectively, for receiving the south pole comparison signal Vo 1; the outputs of the OR gate OR2 and NAND gate NAND3 are both connected to the input of the NAND gate NAND 4. The output signals of the flip-flops T2, T4 and T6 are Q2, Q4 and Q6 respectively, the output signal of the NAND4 is Y2,
the truth table for Y2 is as follows:
| Q2 | Q4 | Q6 | Y2 |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
only when Q2, Q4, Q6 are simultaneously 0 or1, Y2 is 1. Only when Q2, Q4, Q5 are simultaneously 0 or1, Y2 is 1. Q2, Q4, Q5 are three consecutive south pole comparison signals, and if there is a noise effect when compared to the south pole field threshold BOPS, the values of Q2, Q4 and Q6 are not continuously equal. Therefore, when the values of Q2, Q4, and Q6 are the same, the noise is small.
The clock signal generating subunit is connected to the output ends of the two sub-comparison units, and is configured to perform and operation on the output signals of the two sub-comparison units, and output an operation result as a third clock signal. In this embodiment, the clock signal generating sub-unit includes an AND gate AND1, the AND gate AND1 is connected to the output terminals of the NAND gates NAND2 AND NAND4 of the two sub-comparing units, AND the AND operation is performed on the signals Y1 AND Y2 output by the two sub-comparing units under the control of the second clock signal CK2, AND a third clock signal Y, Y-CK 2-Y is output1·Y2。
The truth table for Y is as follows:
| CK2 | Y1 | Y2 | Y |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
when both Y1 and Y2 are 1, Y is 1 when CK2 rises. In this embodiment, the rising edge time of the second clock signal CK2 is located between every (N1+ N2) rising edges of the first clock signal CK1, and the rising edge time of the second clock signal CK2 is located between every 6 rising edges of the first clock signal CK1 (please refer to fig. 8), so as to obtain a final comparison result.
The output ends of the two flip-flops in the shift register are further connected to the two input ends of the logic operation unit 122, respectively, and are used for outputting a south pole comparison signal and a north pole comparison signal, respectively. In this embodiment, the flip-flop T5 and the flip-flop T6 are used as outputs to output comparison signals Q5 and Q6 to the logical operation unit 122, respectively.
The logical operation unit 122 is configured to perform an exclusive nor operation, and when the level of any one of the received comparison signals is inverted, the level of the control signal is inverted. In this embodiment, only when the two comparison signals are the same, the high level is output. In other embodiments, the logic operation unit 122 can also be used to perform other forms of logic operations to meet the requirements of practical applications. Specifically, the logical operation unit 122 includes: flip-flop T7, flip-flop T8, and exclusive-or gate 1221; the input ends of the flip-flops T7 and T8 are respectively connected to two output ends of the noise reduction unit 121, the output ends of the flip-flops are respectively connected to the input end of the exclusive-or gate 1221, the two flip-flops are configured to respectively receive the south pole comparison signal and the north pole comparison signal output by the noise reduction unit 121, and the exclusive-or gate 1221 performs exclusive-or operation to output the control signal.
An input end D7 of the flip-flop T7 is connected to an output end of a flip-flop T5 in the comparison unit 121, an input end D8 of the flip-flop T8 is connected to an output end of a flip-flop T6 in the comparison unit 121, AND clock ends C7 AND C8 of the flip-flop T3578 AND the flip-flop T1 are both connected to output ends of the AND gate AND1 AND controlled by a third clock signal Y. The exclusive or gate 1221 outputs a control signal VO,
please refer to fig. 8, which is a schematic partial structure diagram of a hall sensor according to another embodiment of the present application.
In this embodiment, the noise reduction logic module 120 is further connected to the output module 130, and configured to output the control signal VO output by the noise reduction logic module 120 as the control signal VOUT after inverting and amplifying the control signal VO. The output module 130 includes a transistor M and a resistor R, in this embodiment, the transistor M is an NMOS transistor. One end of the resistor R is connected to a power voltage VDD, the other end of the resistor R is connected to the source of the transistor M, the gate of the transistor M is connected to the output end of the noise reduction logic module 120, the drain of the transistor M is grounded, and the source of the transistor M is used as the output end for outputting the control signal VOUT. When VO is at high level, the transistor M is conducted, and VOUT is at low level; when VO is low, transistor M is off and VOUT is high.
When the rising edge of the Y signal comes, an
When B < BOPN < BOPS, Q7 ═ 0, Q8 ═ 0, VO ═ 1, VOUT ═ 0;
when BOPN < B < BOPS, Q7 ═ 1, Q8 ═ 0, VO ═ 0, VOUT ═ 1;
when BOPN < BOPS < B, Q7 ═ 1, Q8 ═ 1, VO ═ 1, VOUT ═ 0;
the control signal VO drives the output module 130 to obtain the functional diagram of the all-pole hall switch shown in fig. 1.
Due to the diversity of digital logic operation, in other embodiments, the noise reduction logic module 120 may also adopt other functional module structures or other operation logics as long as the noise reduction and the required logic operation functions can be finally realized.
In other embodiments, the output module 130 may have other structures.
The Hall sensing device of the embodiment can be used for comparing signals with south poles and north poles to reduce noise, and the sensitivity of the Hall sensing device and the stability of output signals are improved.
In an embodiment of the present invention, there is also provided an electronic device, including: the hall sensing device according to any one of the above embodiments, which is capable of outputting a stable and reliable control signal.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.
Claims (14)
1. A hall sensing device, comprising:
the all-polar Hall sensing module is used for detecting an external magnetic field, comparing the external magnetic field with a south-pole magnetic field threshold and a north-pole magnetic field threshold respectively, and outputting a corresponding south-pole comparison signal and a corresponding north-pole comparison signal;
the switching module is connected to the all-polarity Hall sensing module and used for receiving the south pole comparison signal and the north pole comparison signal and sequentially and alternately outputting the south pole comparison signal and the north pole comparison signal;
and the noise reduction logic module is connected to the output end of the switching module and is used for outputting a control signal after carrying out noise reduction processing on the south pole comparison signal and the north pole comparison signal which are sequentially received.
2. The Hall sensing device according to claim 1, wherein the noise reduction logic module comprises a noise reduction unit configured to output the south comparison signal when N1 consecutive south comparison signals are the same and output the north comparison signal when N2 consecutive north comparison signals are the same.
3. The hall sensor device of claim 2 wherein the noise reduction unit comprises an (N1+ N2) shift register and a comparison unit connected to respective output terminals of the shift register; the (N1+ N2) bit shift register is used for outputting the N1 south pole comparison signals and the N2 north pole comparison signals which are sequentially and alternately output by the switching module as (N1+ N2) bit comparison signals in parallel under the control of a first clock signal; the comparison unit is used for outputting high level as a clock signal when N1-bit south pole comparison signals and N2-bit north pole comparison signals output by the shift register are the same.
4. The Hall sensing device according to claim 3, wherein the shift register comprises (N1+ N2) flip-flops having outputs and inputs connected in series, wherein the input of the leading flip-flop is connected to the output of the all-polarity Hall sensing module, and wherein the outputs of the two flip-flops are further connected to the two inputs of the logic operation unit, respectively, for outputting a south pole comparison signal and a north pole comparison signal, respectively.
5. The Hall sensing device according to claim 3, wherein the comparing unit comprises two sub-comparing units and a clock signal generating sub-unit; one sub-comparison unit is connected to the output end of the south pole comparison signal of the shift register and used for comparing whether the south pole comparison signals are the same or not, and the other sub-comparison unit is connected to the output end of the north pole comparison signal of the shift register and used for comparing whether the north pole comparison signals are the same or not; the clock signal generating subunit is connected to the output ends of the two sub-comparison units, and is configured to perform and operation on the output signals of the two sub-comparison units, and output an operation result as a third clock signal.
6. The Hall sensing device according to claim 5, wherein the sub-comparison unit comprises an OR gate, a first NAND gate, and a second NAND gate, wherein the inputs of the OR gate and the first NAND gate are connected to the output of the corresponding comparison signal of the shift register, and the outputs of the OR gate and the first NAND gate are connected to the input of the second NAND gate.
7. The Hall sensing device according to claim 5, wherein the clock signal generating sub-unit comprises an AND gate connected to an output of the second NAND gate of the two sub-comparing units, and under the control of the second clock signal, AND-operates the signals output by the two sub-comparing units and outputs the result of the operation as a third clock signal.
8. The Hall sensing device of claim 7, wherein a rising edge time of the second clock signal is located between every (N1+ N2) rising edges of the first clock signal.
9. The Hall sensing device according to claim 2, wherein the noise reduction logic module further comprises a logic operation unit, the logic operation unit is connected to the output end of the noise reduction unit and is configured to perform logic operation on the south pole comparison signal and the north pole comparison signal output by the noise reduction unit; wherein N1 and N2 are both integers of 2 or more.
10. The hall sensor device of claim 9 wherein the logical operation is an exclusive or operation, and wherein the level of the control signal is inverted when the level of any one of the received comparison signals is inverted.
11. The hall sensing device of claim 9 wherein the logic operation unit comprises: two flip-flops and an exclusive-nor gate; the input ends of the two triggers are respectively connected to the two output ends of the noise reduction unit, the output ends of the two triggers are respectively connected to the input ends of the exclusive OR gate, the two triggers are used for respectively receiving the south pole comparison signal and the north pole comparison signal output by the noise reduction unit, and the exclusive OR gate outputs the control signal after exclusive OR operation.
12. The hall sensing device of claim 1 wherein the all-polar hall sensing module comprises a south pole hall sensing unit and a north pole hall sensing unit; the south pole Hall sensing unit is used for outputting a south pole comparison signal of an external magnetic field and a south pole magnetic field threshold, and the north pole Hall sensing unit is used for outputting a north pole comparison signal of the external magnetic field and a north pole magnetic field threshold.
13. The hall sensor device of claim 12 wherein the switching module comprises two switches, one of which is connected to the connection path between the south hall sensor unit and the input of the noise reduction logic module and the other of which is connected to the connection path between the north hall sensor unit and the input of the noise reduction logic module.
14. An electronic device, comprising: the hall sensing device of any one of claims 1 to 13.
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Citations (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4435678A1 (en) * | 1993-10-08 | 1995-04-13 | Honeywell Inc | Magnetic field sensor |
| US5789915A (en) * | 1989-02-17 | 1998-08-04 | Nartron Corporation | Magnetic field energy responsive position sensing apparatus and method |
| CN1501093A (en) * | 2002-11-13 | 2004-06-02 | ���µ�����ҵ��ʽ���� | Magnetic field sensor ,magnetic field detection device and method |
| CN2844989Y (en) * | 2005-09-02 | 2006-12-06 | 上海鲍麦克斯电子科技有限公司 | Non-contact linear positioning sensor |
| CN101777901A (en) * | 2009-01-14 | 2010-07-14 | 易亨电子股份有限公司 | Precise control device capable of inducing bilateral magnetic field induction |
| CN101825690A (en) * | 2010-05-13 | 2010-09-08 | 上海欣磁电子科技有限公司 | Detection method for all-polarity magnetic field |
| CN102332857A (en) * | 2011-09-26 | 2012-01-25 | 东华大学 | Method for detecting position of hub motor of PET-CT (Positron Emission Tomography-Computed Tomography) machine on basis of magnetic ring and Hall sensor |
| CN103063232A (en) * | 2011-10-21 | 2013-04-24 | 上海腾怡半导体有限公司 | One-chip latch type Hall sensor |
| CN103326702A (en) * | 2013-05-31 | 2013-09-25 | 北京经纬恒润科技有限公司 | Hall switch circuit |
| CN103557782A (en) * | 2013-10-16 | 2014-02-05 | 清华大学 | Linear motor positioning method based on switch Hall sensor sequential coding |
| CN103843243A (en) * | 2012-03-12 | 2014-06-04 | 松下电器产业株式会社 | Motor drive method and motor drive device |
| CN104949696A (en) * | 2014-03-25 | 2015-09-30 | 精工电子有限公司 | Sensor device |
| US20160313143A1 (en) * | 2015-04-23 | 2016-10-27 | SKF Magnetic Bearings, a Unit of SKF Canada Limited | Combined radial position and speed sensor assembly |
| CN106405454A (en) * | 2015-09-16 | 2017-02-15 | 成都芯源***有限公司 | Magnetic angle sensor, system thereof and method for detecting angular position of radial magnetized magnet |
| CN107314782A (en) * | 2017-05-18 | 2017-11-03 | 重庆神缘智能科技有限公司 | A kind of Hall counting device |
| CN107402322A (en) * | 2016-05-20 | 2017-11-28 | 精工半导体有限公司 | Zero hands over detection circuit and sensor device |
| CN107783065A (en) * | 2016-08-26 | 2018-03-09 | 精工半导体有限公司 | Sensor circuit |
| CN108592956A (en) * | 2017-02-14 | 2018-09-28 | 日本电产三协株式会社 | Rotary encoder and its absolute angular position detection method |
| CN109828224A (en) * | 2019-03-26 | 2019-05-31 | 深圳市晶丰弘实业有限公司 | A kind of application method of linear Hall integrated circuit in weak magnetic detection sensor |
| CN209088915U (en) * | 2018-12-25 | 2019-07-09 | 东莞市中昊自动化科技有限公司 | Enhanced bipolarity proximity Hall switch |
| CN110120803A (en) * | 2018-02-06 | 2019-08-13 | 意瑞半导体（上海）有限公司 | A kind of full pole Hall switch circuit |
| CN210157170U (en) * | 2019-06-26 | 2020-03-17 | 乐清市合盈电子有限公司 | Coding type Hall key switch and mechanical keyboard |
| CN111897391A (en) * | 2020-08-17 | 2020-11-06 | 上海艾为电子技术股份有限公司 | Current mirror circuit, bias circuit structure, integrated circuit, and electronic device |
| CN112630707A (en) * | 2020-12-21 | 2021-04-09 | 广电计量检测（西安）有限公司 | Magnetic field detector |
| CN113411074A (en) * | 2021-07-13 | 2021-09-17 | 上海艾为电子技术股份有限公司 | Hall sensor switch and electronic equipment |
-
2021
- 2021-12-17 CN CN202111550084.2A patent/CN114323083A/en active Pending
Patent Citations (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789915A (en) * | 1989-02-17 | 1998-08-04 | Nartron Corporation | Magnetic field energy responsive position sensing apparatus and method |
| DE4435678A1 (en) * | 1993-10-08 | 1995-04-13 | Honeywell Inc | Magnetic field sensor |
| CN1501093A (en) * | 2002-11-13 | 2004-06-02 | ���µ�����ҵ��ʽ���� | Magnetic field sensor ,magnetic field detection device and method |
| CN2844989Y (en) * | 2005-09-02 | 2006-12-06 | 上海鲍麦克斯电子科技有限公司 | Non-contact linear positioning sensor |
| CN101777901A (en) * | 2009-01-14 | 2010-07-14 | 易亨电子股份有限公司 | Precise control device capable of inducing bilateral magnetic field induction |
| CN101825690A (en) * | 2010-05-13 | 2010-09-08 | 上海欣磁电子科技有限公司 | Detection method for all-polarity magnetic field |
| CN102332857A (en) * | 2011-09-26 | 2012-01-25 | 东华大学 | Method for detecting position of hub motor of PET-CT (Positron Emission Tomography-Computed Tomography) machine on basis of magnetic ring and Hall sensor |
| CN103063232A (en) * | 2011-10-21 | 2013-04-24 | 上海腾怡半导体有限公司 | One-chip latch type Hall sensor |
| CN103843243A (en) * | 2012-03-12 | 2014-06-04 | 松下电器产业株式会社 | Motor drive method and motor drive device |
| CN103326702A (en) * | 2013-05-31 | 2013-09-25 | 北京经纬恒润科技有限公司 | Hall switch circuit |
| CN103557782A (en) * | 2013-10-16 | 2014-02-05 | 清华大学 | Linear motor positioning method based on switch Hall sensor sequential coding |
| CN104949696A (en) * | 2014-03-25 | 2015-09-30 | 精工电子有限公司 | Sensor device |
| US20160313143A1 (en) * | 2015-04-23 | 2016-10-27 | SKF Magnetic Bearings, a Unit of SKF Canada Limited | Combined radial position and speed sensor assembly |
| CN106405454A (en) * | 2015-09-16 | 2017-02-15 | 成都芯源***有限公司 | Magnetic angle sensor, system thereof and method for detecting angular position of radial magnetized magnet |
| CN107402322A (en) * | 2016-05-20 | 2017-11-28 | 精工半导体有限公司 | Zero hands over detection circuit and sensor device |
| CN107783065A (en) * | 2016-08-26 | 2018-03-09 | 精工半导体有限公司 | Sensor circuit |
| CN108592956A (en) * | 2017-02-14 | 2018-09-28 | 日本电产三协株式会社 | Rotary encoder and its absolute angular position detection method |
| CN107314782A (en) * | 2017-05-18 | 2017-11-03 | 重庆神缘智能科技有限公司 | A kind of Hall counting device |
| CN110120803A (en) * | 2018-02-06 | 2019-08-13 | 意瑞半导体（上海）有限公司 | A kind of full pole Hall switch circuit |
| CN209088915U (en) * | 2018-12-25 | 2019-07-09 | 东莞市中昊自动化科技有限公司 | Enhanced bipolarity proximity Hall switch |
| CN109828224A (en) * | 2019-03-26 | 2019-05-31 | 深圳市晶丰弘实业有限公司 | A kind of application method of linear Hall integrated circuit in weak magnetic detection sensor |
| CN210157170U (en) * | 2019-06-26 | 2020-03-17 | 乐清市合盈电子有限公司 | Coding type Hall key switch and mechanical keyboard |
| CN111897391A (en) * | 2020-08-17 | 2020-11-06 | 上海艾为电子技术股份有限公司 | Current mirror circuit, bias circuit structure, integrated circuit, and electronic device |
| CN112630707A (en) * | 2020-12-21 | 2021-04-09 | 广电计量检测（西安）有限公司 | Magnetic field detector |
| CN113411074A (en) * | 2021-07-13 | 2021-09-17 | 上海艾为电子技术股份有限公司 | Hall sensor switch and electronic equipment |
Non-Patent Citations (1)
| Title |
|---|
| 梁珊珊，何志伟: "《基于霍尔效应的磁场测量方法的研究》", 《电测与仪表》, 31 December 2013 (2013-12-31) * |
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