CN111628731B - Noise detection circuit - Google Patents
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- CN111628731B CN111628731B CN202010504344.1A CN202010504344A CN111628731B CN 111628731 B CN111628731 B CN 111628731B CN 202010504344 A CN202010504344 A CN 202010504344A CN 111628731 B CN111628731 B CN 111628731B
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Abstract
A detection circuit detects whether a differential signal including a positive phase signal and a negative phase signal is noise or not, and includes a high threshold trigger, a low threshold trigger and a logic circuit. When the voltage of the positive phase signal is changed from being smaller than a first negative threshold value to being larger than a first positive threshold value, the first control signal output by the high threshold trigger is changed from a first level to a second level; when the voltage of the positive phase signal is changed from being greater than the first positive threshold value to being smaller than the first negative threshold value, the first control signal is changed from the second level to the first level. The second control signal output by the low threshold trigger is changed from the second level to the first level when the negative phase signal is changed from greater than the second positive threshold to less than the second negative threshold, and is changed from the first level to the second level when the voltage of the negative phase signal is changed from less than the second negative threshold to greater than the second positive threshold. The logic circuit indicates whether the differential signal is noise or not according to the first control signal and the second control signal.
Description
Technical Field
The present invention relates to a detection circuit, and more particularly, to a detection circuit for noise detection.
Background
In general, in order to detect noise in differential signals and filter the noise, a differential amplifier (Differential Difference Amplifier: DDA) is often used to firstly subtract a reference signal from the differential signal to obtain a differential value therebetween, amplify the differential value, and then a comparator is used to determine whether the differential signal is noise according to the amplified differential value. In this case, the comparator has only a single threshold value, and therefore when an input signal having a noise component is input to the comparator, the output signal of the comparator repeatedly swings between a low level and a high level when the input signal is in the vicinity of the threshold value due to the influence of noise. Moreover, because the differential difference amplifier and the comparator are required to be configured at the same time, the circuit is complex, the occupied area is large, and the power consumption is large.
Disclosure of Invention
According to an embodiment of the invention, a detection circuit is configured to detect whether a differential signal is noise, wherein the differential signal includes a positive phase signal and a negative phase signal, and the detection circuit includes a high threshold trigger, a low threshold trigger and a logic circuit. The high threshold trigger receives positive phase signals, and when the positive phase signals are changed from being smaller than a first negative threshold to being larger than a first positive threshold, a first control signal output by the high threshold trigger is changed from a first level to a second level; when the voltage of the positive phase signal is changed from being larger than a first positive threshold value to be the first negative threshold value, the first control signal is changed from a second level to be a first level. The low threshold trigger receives a negative phase signal, and when the negative phase signal is changed from being larger than a second positive threshold to be smaller than a second negative threshold, a second control signal output by the low threshold trigger is changed from a second level to a first level; when the voltage of the negative phase signal is changed from being smaller than the second negative threshold value to being larger than the second positive threshold value, the second control signal is changed from the first level to the second level. The logic circuit is connected with the high threshold trigger to receive a first control signal, is coupled with the low threshold trigger to receive a second control signal, and indicates whether the differential signal is noise or not according to the first control signal and the second control signal, wherein the first positive threshold is larger than the first negative threshold, the first negative threshold is larger than the second positive threshold, and the second positive threshold is larger than the second negative threshold.
The detection circuit further includes a second low threshold flip-flop and a second high threshold flip-flop. The second low threshold trigger receives a positive phase signal, and when the positive phase signal is changed from being larger than a second positive threshold to be smaller than a second negative threshold, a third control signal output by the second low threshold trigger is changed from a second level to a first level; when the voltage of the positive phase signal is changed from being smaller than the second negative threshold value to being larger than the second positive threshold value, the third control signal is changed from the first level to the second level. The second high threshold trigger receives a negative phase signal, and when the negative phase signal is changed from being smaller than a first negative threshold to being larger than a first positive threshold, a fourth control signal output by the second high threshold trigger is changed from a first level to a second level; when the negative phase signal changes from being larger than the first positive threshold value to being smaller than the first negative threshold value, the fourth control signal changes from the second level to the first level. The logic circuit is further coupled to the second low threshold trigger to receive the third control signal, coupled to the second high threshold trigger to receive the fourth control signal, and indicates whether the differential signal is noise according to the first control signal, the second control signal, the third control signal and the fourth control signal.
Drawings
FIG. 1 is a diagram of waveforms of input and output of a comparator and a Schmitt trigger;
fig. 2 is a circuit diagram of a detection circuit 200 according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating the input/output of the flip-flop of the detection circuit 200 of FIG. 2 according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of another detection circuit 400 according to an embodiment of the invention;
FIG. 5 is a circuit diagram of the high threshold flip-flop 202, 404 of FIG. 4 according to the embodiment of the present invention shown in FIG. 2;
FIG. 6 is a circuit diagram of the low threshold flip-flops 204, 402 of FIG. 4 according to an embodiment of the present invention shown in FIG. 2; and
fig. 7 is a circuit diagram of the first voltage level shifter 208 and the second voltage level shifter 210 of fig. 4 according to the embodiment of the present invention shown in fig. 2.
Detailed Description
Fig. 1 is a schematic diagram of the input and output of a comparator and Schmitt Trigger (Schmitt Trigger). As shown in fig. 1 (a), since the comparator has only a single threshold V ref Thus when the input signal V has a noise component in When input to the comparator, due to noise effect, the input signal V in At threshold V ref In the vicinity, the output signal V out Will appear at low level V OL High level V OH And the case of repeated swinging. As shown in fig. 1 (b), since the schmitt trigger has a high threshold valueLow thresholdGenerating hysteresis effect on the output signal Vout, the output signal V can be avoided out The situation of repeated swinging occurs.
Fig. 2 is a circuit diagram of a detection circuit 200 according to an embodiment of the invention. As shown in fig. 2, the detection circuit 200 includes a high threshold flip-flop 202, a low threshold flip-flop 204, a logic circuit 206, a first voltage level shifter 208, and a second voltage level shifter 210. The detection circuit 200 is configured to detect noise in a pair of differential signals, i.e. to receive the pair of differential signals and determine whether the pair of differential signals is noise, wherein the pair of differential signals includes a positive phase signal Inp and a negative phase signal Inn.
The first voltage level shifter 208 is coupled to the positive phase signal Inp, adjusts the dc voltage of the positive phase signal Inp to the threshold midpoint voltage VM, and outputs the adjusted positive phase signal Inp, i.e., the positive phase signal Inp', to the high threshold trigger 202. The second voltage level shifter 210 is coupled to the negative phase signal Inn, adjusts the dc voltage of the negative phase signal Inn to the threshold midpoint voltage VM, and outputs the adjusted negative phase signal Inn, i.e. the negative phase signal Inn', to the low threshold trigger 204.
The high threshold flip-flop 202 takes the positive phase signal Inp 'as an input signal, and the high threshold flip-flop 202 detects the high level of the positive phase signal Inp'. Specifically, when the voltage of the positive phase signal Inp' is smaller than the first negative-going threshold VL H Becomes greater than the first forward threshold VH H In this case, the first control signal C1 outputted from the high threshold flip-flop 202 is changed from a first level, for example, a low level, to a second level, for example, a high level. When the voltage of the normal phase signal Inp' is greater than the first normal threshold VH H Becomes smaller than the first negative threshold VL H In this case, the first control signal C1 outputted from the high threshold flip-flop 202 is changed from the second level to the first level. Wherein the first forward threshold value VH H Greater than a first negative threshold VL H 。
The low threshold flip-flop 204 takes the negative phase signal Inn 'as an input signal, and the low threshold flip-flop 204 detects a low level of the negative phase signal Inn'. Specifically, when the negative phase signal Inn' is greater than the second positive threshold VH L Becomes smaller than the second negative threshold VL L The second control signal C2 output from the low threshold flip-flop 204 changes from a second level, for example, a high level, to a first level, for example, a low level. When the negative phase signal Inn' is smaller than the second negative threshold VL L Becomes greater than the second forward threshold VH L The second control signal C2 output from the low threshold flip-flop 204 changes from the first level to a second level, for example, a high level. Wherein the second forward threshold VL H Greater than a second negative threshold VL L 。
The logic circuit 206 is coupled to the high threshold flip-flop 202 and the low threshold flip-flop 204 to receive the first control signal C1 and the second control signal C2, respectively. Logic circuit 206 controls the second controlThe signal C2 is processed in reverse phase to obtain a second reverse phase control signalWhen the first control signal C1 and the second inverted control signal +>At a second level, such as a high level, the logic circuit 206 outputs an output signal OUT having the second level. When the first control signal C1 and the second inverted control signal +>The logic circuit 206 outputs the output signal OUT having the first level when both are at the first level, e.g., low level.
Logic circuit 206 includes inverter 212, n-type transistor 214, n-type transistor 216, pull-up resistor 218, capacitor 220, and inverter 222. As shown in fig. 2, the inverter 212 is coupled to the low threshold flip-flop 204 to receive the second control signal C2, and the inverter 212 inverts the second control signal C2 to obtain a second inverted control signalThe drain of the N-type transistor 214 is coupled to the drain of the N-type transistor 216, and the gate of the N-type transistor 214 is coupled to the output terminal of the inverter 212 for receiving the second inversion control signal +>The source of the N-type transistor 214 is coupled to the ground voltage GND. The drain of the N-type transistor 216 is coupled to the first node 1, the gate of the N-type transistor 216 is coupled to the output terminal of the high threshold trigger 202, and the source of the N-type transistor 216 is coupled to the ground voltage GND. One end of the pull-up resistor 218 is coupled to the power voltage VDD, and the other end of the pull-up resistor 218 is coupled to the first node 1. One end of the capacitor 220 is coupled to the first node 1, and the other end of the capacitor 220 is coupled to the ground voltage GND. The input of the inverter 222 is coupled to the first node 1, and the output of the inverter 222 is the output of the logic circuit 206And a terminal for outputting an output signal OUT. When the first control signal C1 and the second inverted control signal +>Both are at a first level, e.g., low level, the N-type transistors 214 and 216 are turned off, and the voltage at the first node 1 is at a second level, e.g., high level, so that the output signal OUT is at the first level, indicating that the positive phase signal Inp 'and the negative phase signal Inn' are noise. When the first control signal C1 and the second inverted control signal +>At least one of the N-type transistor 214 and the N-type transistor 216 is turned on when at least one of them is at the second level, and the voltage of the first node 1 is at the first level, so that the output signal OUT is at the second level, indicating that the positive phase signal Inp 'and the negative phase signal Inn' are not noise. Logic 206 may be an alternative to the or gate logic shown in fig. 2 in accordance with an embodiment of the present invention. According to another embodiment of the present invention, the inverter 222 may be replaced with a schmitt trigger to filter out the noise of the first node 1.
Fig. 3 is a schematic diagram of the input/output of the high threshold flip-flop 202 and the low threshold flip-flop 204 of fig. 2. Referring to line 1 of FIG. 3, when the positive phase signal Inp' is less than the first negative threshold VL H Becomes greater than the first forward threshold VH H In this case, the first control signal C1 outputted from the high threshold trigger 202 is changed from a first level, for example, a low level, to a second level, for example, a high level. As shown in line 2 of FIG. 3, when the normal phase signal Inp' is greater than the first normal threshold VH H Becomes smaller than the first negative threshold VL H In this case, the first control signal C1 outputted from the high threshold flip-flop 202 changes from the second level to the first level. Wherein the first forward threshold value VH H Greater than a first negative threshold VL H . As shown in line 3 of FIG. 3, when the negative phase signal Inn' is smaller than the second negative threshold VL L Becomes greater than the second forward threshold VH L At this time, the first control signal C2 output from the low threshold flip-flop 204 changes from the first level to the second level. As shown by line 4 in FIG. 3, when negatively believedNumber Inn' is greater than the second negative threshold VH L Becomes smaller than the second negative threshold VL L At this time, the second control signal C2 output from the low threshold flip-flop 204 changes from the second level to the first level. Wherein the second forward threshold value VH L Greater than a second negative threshold VL L And a first negative threshold VL H Greater than a second forward threshold VH L . According to an embodiment of the present invention, when the positive phase signal Inp 'is located in the hysteresis window between the line segments 1 and 2, or the negative phase signal Inn' is located in the hysteresis window between the line segments 3 and 4, the first control signal C1 or the second control signal C2 is in an uncertain state. According to an embodiment of the present invention, the threshold midpoint voltage VM shown in FIG. 3 is equal to the first forward threshold VH H Second negative threshold VL L Average Value (VH) H +VL L )/2。
Fig. 4 is a circuit diagram of another detection circuit 400 according to an embodiment of the invention. As shown in fig. 4, the detection circuit 400 includes a low threshold flip-flop 402 and a high threshold flip-flop 404 in addition to all components of the detection circuit 200 of fig. 2. The high and low levels of the positive phase signal Inp' are detected by the high threshold flip-flop 202 and the low threshold flip-flop 402, respectively. The high and low levels of the negative phase signal Inn' are detected by the high threshold flip-flop 404 and the low threshold flip-flop 204, respectively.
The low threshold flip-flop 402 has as an input signal a positive phase signal Inp' which is formed by a signal greater than the second positive threshold VH L Becomes smaller than the second negative threshold VL L At this time, the third control signal C3 outputted from the low threshold trigger 402 is changed from the second level, for example, the high level, to the first level, for example, the low level. When the voltage of the positive phase signal Inp' is smaller than the second negative threshold VL L Becomes greater than the second forward threshold VH L In this case, the third control signal C3 outputted from the low threshold flip-flop 402 is changed from the first level to the second level.
The high threshold flip-flop 404 takes the negative phase signal Inn 'as an input signal when the voltage of the negative phase signal Inn' is smaller than the first negative threshold VL H Becomes greater than the first forward threshold VH H Fourth control of high threshold flip-flop 404 outputThe control signal C4 changes from the first level to the second level. When the voltage of the negative phase signal Inn' is greater than the first positive threshold value VH H Varying to be less than a first negative threshold VL H At this time, the fourth control signal C4 outputted from the high threshold flip-flop 404 changes from the second level to the first level.
As shown in fig. 4, the logic circuit 406 is further coupled to the third control signal C3 and the fourth control signal C4. The logic circuit 406 inverts the third control signal C3 to obtain a third inverted control signalWhen the first control signal C1, the second inverted control signal +.>Third inverting control Signal->And at least one of the fourth control signals C4 is at a second level, such as a high level, the logic circuit 406 outputs the output signal OUT having the second level. When the first control signal C1, the second inverted control signal +.>Third inverting control Signal->And the fourth control signal C4 is at a first level, for example, a low level, the logic circuit 406 outputs the output signal OUT having the first level.
The logic circuit 406 includes an inverter 412, an N-type transistor 408, and an N-type transistor 410 in addition to all components of the logic circuit 206 of fig. 2. The inverter 412 is coupled to the low threshold flip-flop 402 to receive the third control signal C3, and the inverter 412 inverts the third control signal C3 to obtain a third inverted control signalN-type transistor 216, NThe gates of the transistors 214, 410, 408 are respectively coupled to the output of the high threshold flip-flop 202, the output of the inverter 212, the output of the inverter 412, and the output of the high threshold flip-flop 404 to receive the first control signal C1 and the second inversion control signal +.>Third inverting control Signal->A fourth control signal C4; sources of the N-type transistors 216, 214, 410, 408 are coupled to each other and commonly coupled to the ground voltage GND; the drains of the N-type transistors 216, 214, 410, 408 are coupled to each other and commonly coupled to the first node 1. When the first control signal C1, the second inverted control signal +.>Third inverting control Signal->And the fourth control signal C4 is at a first level, such as a low level, the N-type transistor 216, the N-type transistor 214, the N-type transistor 410, and the N-type transistor 408 are turned off, and the voltage at the first node 1 is at a second level, such as a high level, so that the output signal OUT is at the first level, indicating that the positive phase signal Inp 'and the negative phase signal Inn' are noise. When the first control signal C1, the second inverted control signal +.>Third inverting control Signal->) And at least one of the fourth control signals C4 is at the second level, at least one of the N-type transistor 216, the N-type transistor 214, the N-type transistor 410, the N-type transistor 408 is turned on, the voltage of the first node 1 is the first powerThe output signal OUT is made flat to be at the second level, indicating that the positive phase signal Inp 'and the negative phase signal Inn' are not noise. Logic 406 may be an alternative to the or gate logic shown in fig. 4, in accordance with an embodiment of the present invention.
Fig. 5 is a circuit diagram of the high threshold flip-flop 202 of fig. 2 or the high threshold flip-flop 404 of fig. 4 according to an embodiment of the present invention. As shown in fig. 5, high threshold flip-flop 202 or high threshold flip-flop 404 includes resistor 500, resistor 502, resistor 504, P-type transistor 506, P-type transistor 508, P-type transistor 510, N-type transistor 512, N-type transistor 514, inverter 516, inverter 518, and inverter 520. One end of the resistor 500 is coupled to the power voltage VDD, and the other end of the resistor 500 is coupled to the source of the P-type transistor 506. The second node 2 receives. The gate of the P-type transistor 506 is coupled to the second node 2, and the drain of the P-type transistor 506 is coupled to the third node 3. The gate of the P-type transistor 508 is coupled to the second node 2, the source of the P-type transistor 508 is coupled to the third node 3, and the drain of the P-type transistor 508 is coupled to the fourth node 4. The gate of the N-type transistor 514 is coupled to the second node 2, the source of the N-type transistor 514 is coupled to the drain of the N-type effect transistor 512, and the drain of the N-type transistor 514 is coupled to the fourth node 4. The gate of the N-type transistor 512 is coupled to the second node 2, and the source of the N-type transistor 512 is coupled to one end of the resistor 502. The other end of the resistor 502 is coupled to the ground voltage GND. One end of the resistor 504 is coupled to the power voltage VDD, and the other end of the resistor 504 is coupled to the source of the P-type transistor 510. The gate of the P-type transistor 510 is coupled to the fifth node 5, and the drain of the P-type transistor 510 is coupled to the third node 3. An input of the inverter 516 is coupled to the fourth node 4, and an output of the inverter 516 is coupled to the fifth node 5. The input terminal of the inverter 518 is coupled to the fifth node 5, the output terminal of the inverter 518 is coupled to the input terminal of the inverter 520, and the output terminal of the inverter 520 is the output terminal of the high threshold flip-flop 202 or the high threshold flip-flop 404 for outputting the first control signal C1 or the fourth control signal C4.
First forward threshold VH H First negative threshold VL H Can be expressed as:
wherein I is d At the threshold voltage Vthn or Vthp, current flows through the P-type transistor 506, the P-type transistor 508, the N-type transistor 512, and the N-type transistor 514; r is R 1 A resistance of the resistor 500; r is R 2 A resistance which is resistance 502; r is R 3 A resistance which is resistance 504; VDD is the power supply voltage VDD; v (V) thn The threshold voltages of the N-type transistors 512 and 514; v (V) thp Is the threshold voltage of the P-type transistor 506, the P-type transistor 508, and the P-type transistor 510.
By adjusting the values of resistor 500, resistor 502, and resistor 504, the first forward threshold VH of high threshold flip-flop 202 or high threshold flip-flop 404 can be directly adjusted H First negative threshold VL H Is of a size of (a) and (b).
First forward threshold VH H First negative threshold VL H I.e. the hysteresis voltage VH between the high threshold flip-flop 202 and the high threshold flip-flop 404 H -VL H The method comprises the following steps:
fig. 6 is a circuit diagram of the low threshold flip-flop 204 or the low threshold flip-flop 402 of fig. 4 according to the embodiment of the present invention shown in fig. 2. As shown in fig. 6, low threshold flip-flop 204 or low threshold flip-flop 402 includes resistor 600, resistor 602, resistor 604, N-type transistor 606, N-type transistor 608, N-type transistor 610, P-type transistor 612, P-type transistor 614, inverter 616, inverter 618, and inverter 620. One end of the resistor 602 is coupled to the power voltage VDD, and the other end of the resistor 602 is coupled to the source of the P-type transistor 612. The sixth node 6 receives either the positive phase signal Inp 'or the negative phase signal Inn'. The gate of the P-type transistor 612 is coupled to the sixth node 6, and the drain of the P-type transistor 612 is coupled to the source of the P-type transistor 614. The gate of the P-type transistor 614 is coupled to the sixth node 6, and the drain of the P-type transistor 614 is coupled to the eighth node 8. The gate of the N-type transistor 608 is coupled to the sixth node 6, the source of the N-type transistor 608 is coupled to the seventh node 7, and the drain of the N-type transistor 608 is coupled to the eighth node 8. The gate of the N-type transistor 606 is coupled to the sixth node 6, the drain of the N-type transistor 606 is coupled to the seventh node 7, and the source of the N-type transistor 606 is coupled to one end of the resistor 600. The other end of the resistor 600 is coupled to the ground voltage GND. An input of the inverter 616 is coupled to the eighth node 8, and an output of the inverter 616 is coupled to the ninth node 9. The gate of the N-type transistor 610 is coupled to the ninth node 9,N, the drain of the N-type transistor 610 is coupled to the seventh node 7, and the source of the N-type transistor 610 is coupled to one end of the resistor 604. The other end of the resistor 604 is coupled to the ground voltage GND. An input of the inverter 618 is coupled to the ninth node 9. The input terminal of the inverter 620 is coupled to the output terminal of the inverter 618, and the output terminal of the inverter 620 is the output terminal of the low threshold flip-flop 204 or the low threshold flip-flop 402, and is configured to output the second control signal C2 or the third control signal C3.
Second negative threshold VL L Second forward threshold VH L Can be expressed as:
wherein Id is the voltage of the N-type transistor or the P-type transistor at the critical voltage V thn Or V thp During this time, current flows through P-type transistor 612, P-type transistor 614, and N-type transistor 608; r4 is the resistance of resistor 600; r5 is the resistance of resistor 602; r6 is the resistance of resistor 604; VDD is the power supply voltage VDD; vthn is the threshold voltage of N-type transistor 606, N-type transistor 608, N-type transistor 610; vthp is the threshold voltage of P-type transistor 612 and P-type transistor 614.
By adjusting the values of resistor 600, resistor 602, and resistor 604, the magnitudes of the second negative threshold VLL and the second positive threshold VHL of low threshold flip-flop 204 or low threshold flip-flop 402 can be directly adjusted.
Second negative threshold VL L Second forward threshold VH L I.e. hysteresis voltage VH between low threshold flip-flop 204 or low threshold flip-flop 402 L -VL L Can be expressed as;
according to these formulas, the designer can properly adjust the resistance values of the resistors 500, 502, 504, 600, 602, 604 according to the amplitudes of the positive phase signal Inp and the negative phase signal Inn to obtain the first forward threshold VH according with the circuit design requirement H First negative threshold VL H Second negative threshold VL L And a second forward threshold VH L 。
Fig. 7 is a circuit diagram of the first voltage level shifter 208 of fig. 2 or the second voltage level shifter 210 of fig. 4 according to an embodiment of the present invention. As shown in fig. 7, the first voltage level shifter 208 or the second voltage level shifter 210 includes a capacitor 700, a resistor 702, a resistor 704, a P-type transistor 706, a P-type transistor 708, an N-type transistor 710, and an N-type transistor 712. One end of the capacitor 700 is coupled to the positive phase signal Inp or the negative phase signal Inn, and the other end of the capacitor 700 is coupled to the tenth node 10. One end of the resistor 702 is coupled to the power voltage VDD, and the other end of the resistor 702 is coupled to the source of the P-type transistor 706. The gate of the P-type transistor 706 is coupled to the tenth node 10, and the drain of the P-type transistor 706 is coupled to the source of the P-type transistor 708. The gate and drain of the P-type transistor 708 are coupled to the tenth node 10. The gate and drain of the N-type transistor 712 are coupled to the tenth node 10, and the source of the N-type transistor 712 is coupled to the drain of the N-type transistor 710. The gate of the N-type transistor 710 is coupled to the tenth node 10, and the source of the N-type transistor 710 is coupled to one end of the resistor 704. The other end of the resistor 704 is coupled to the ground voltage GND. The tenth node 10 is used as an output terminal of the first voltage level shifter 208 or the second voltage level shifter 210 for outputting a positive phase signal Inp 'or a negative phase signal Inn' with a regulated dc voltage.
The dc voltage VCM of the positive phase signal Inp or the negative phase signal Inn can be expressed as:
wherein R is 7 A resistance which is resistance 702; r is R 8 A resistance which is a resistance 704; VDD is the power supply voltage VDD; v (V) thn Is the threshold voltage of the N-type mosfet 710, 712; v (V) thp Is the threshold voltage of the pmos 706, 708.
By adjusting the resistance values of the resistor 702 and the resistor 704, the dc level VCM of the positive phase signal Inp or the negative phase signal Inn outputted by the first voltage level converter 208 or the second voltage level converter 210 can be changed.
According to the aforementioned VH H VL (VL) L As can be seen from the equation, the threshold midpoint voltage VM, i.e., VM shown in fig. 3, can be expressed as:
comparing VCM and VM, when the resistance R of the resistor 702 is equal to 7 Resistance value R equal to resistance 704 8 The dc level VCM will be equal to the threshold midpoint voltage VM, so the first voltage level shifter 208 or the second voltage level shifter 210 can accurately track the threshold window (VH) formed by the high threshold flip-flops 202 and 404 and the low threshold flip-flops 204 and 402 H -VL L ) Is set to a threshold midpoint voltage VM.
When the amplitude of the positive phase signal Inp or the negative phase signal Inn received by the detection circuit 200, 400 of the present invention is smaller than the first positive threshold VH H Second negative threshold VL L Is the difference of VH (V) H -VL L When the output signal OUT of the logic circuits 206, 406 is at a first level, e.g. a low level, the positive phase signal Inp or the negative phase signal Inn is regarded as noise. When the amplitude of the positive phase signal Inp or the negative phase signal Inn is greater than the first positive threshold VH H Second negative threshold VL L Is the difference of VH (V) H -VL L When the output signal OUT of the logic circuits 206, 406 is at a second level, such as a high level, the positive phase signal Inp or the negative phase signal Inn is regarded as a normal signal.
The detection circuit 200 detects the high level of the positive phase signal Inp by using the high threshold trigger 202, and detects the low level of the negative phase signal Inn by using the low threshold trigger 204, so as to achieve the purpose of amplitude detection, and the detection circuit 200 has the effects of small area and low power consumption, and is suitable for an environment in which the frequency of the input differential signals, namely the positive phase signal Inp and the negative phase signal Inn, is relatively fixed. The detection circuit 400 uses the high threshold trigger 202, the low threshold trigger 402 to detect the high level and the low level of the positive phase signal Inp, and the low threshold trigger 204 uses the high threshold trigger 402 to detect the high level and the low level of the negative phase signal Inn, so that the detection circuit 400 has the advantages of high detection precision and wide coverage frequency range, and is suitable for the environments with complex and changeable frequency of the input differential signals, namely the positive phase signal Inp and the negative phase signal Inn.
While embodiments of the present invention have been described above, it should be understood that the foregoing is presented by way of example only, and not limitation. Many variations of the above-described exemplary embodiments according to the present embodiment can be implemented without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Rather, the scope of the invention should be defined in the following claims and their equivalents.
Claims (14)
1. A detection circuit for receiving and determining whether a differential signal is noise, wherein the differential signal includes a positive phase signal and a negative phase signal, the detection circuit comprising:
a high threshold trigger, which receives the positive phase signal, and when the voltage of the positive phase signal is changed from being smaller than a first negative threshold to being larger than a first positive threshold, the first control signal output by the high threshold trigger is changed from a first level to a second level; when the voltage of the positive phase signal is changed from being greater than the first positive threshold value to being less than the first negative threshold value, the first control signal is changed from the second level to the first level;
a low threshold trigger, which receives the negative phase signal, and when the voltage of the negative phase signal is changed from being greater than a second positive threshold to being smaller than a second negative threshold, the second control signal output by the low threshold trigger is changed from the second level to the first level; when the voltage of the negative phase signal is changed from being smaller than the second negative threshold value to being larger than the second positive threshold value, the second control signal is changed from the first level to the second level; and
logic coupled to the high threshold trigger to receive the first control signal, coupled to the low threshold trigger to receive the second control signal, the logic indicating whether the differential signal is noise according to the first control signal and the second control signal,
wherein the first positive threshold is greater than the first negative threshold, the first negative threshold is greater than the second positive threshold, and the second positive threshold is greater than the second negative threshold.
2. The detection circuit of claim 1, wherein the logic circuit inverts the second control signal to obtain a second inverted control signal;
when at least one of the first control signal and the second inverted control signal is at the second level, an output signal output by the logic circuit has the second level, indicating that the differential signal is not noise; and
when the first control signal and the second inverted control signal are both at the first level, the output signal has the first level, indicating that the differential signal is noise.
3. The detection circuit of claim 2, wherein the logic circuit comprises:
a first inverter coupled to the low threshold flip-flop to receive the second control signal, the first inverter inverting the second control signal to obtain the second inverted control signal;
a first transistor, wherein a grid electrode of the first transistor receives the first control signal, a source electrode of the first transistor is grounded, and a drain electrode of the first transistor is coupled with a first node;
a second transistor, a gate of which receives the second inverted control signal, a source of which is grounded, and a drain of which is coupled to the first node;
one end of the pull-up resistor is coupled with a power supply, and the other end of the pull-up resistor is coupled with the first node;
one end of the capacitor is coupled with the first node, and the other end of the capacitor is grounded; and
the input end of the second inverter is coupled with the first node, and the output end of the second inverter is the output end of the logic circuit and is used for outputting the output signal; wherein,,
when the first control signal and the second inverted control signal are at the first level, the first transistor and the second transistor are turned off, so that the voltage of the first node is at the second level, and the output signal is at the first level; and
when at least one of the first control signal and the second inverted control signal is at the second level, at least one of the first transistor and the second transistor is turned on, so that the voltage of the first node is at the first level, and the output signal is at the second level.
4. The detection circuit of claim 1, further comprising a second low threshold flip-flop and a second high threshold flip-flop;
the second low threshold trigger receives the positive phase signal, and when the voltage of the positive phase signal is changed from being larger than the second positive threshold to smaller than the second negative threshold, the third control signal output by the second low threshold trigger is changed from the second level to the first level; when the voltage of the positive phase signal is changed from being smaller than the second negative threshold value to being larger than the second positive threshold value, the third control signal is changed from the first level to the second level;
the second high threshold trigger receives the negative phase signal, and when the voltage of the negative phase signal is changed from being smaller than the first negative threshold to being larger than the first positive threshold, the fourth control signal output by the second high threshold trigger is changed from the first level to the second level; when the voltage of the negative phase signal changes from being greater than the first positive threshold value to being less than the first negative threshold value, the fourth control signal changes from the second level to the first level; and
the logic circuit is further coupled to the second low threshold trigger to receive the third control signal, coupled to the second high threshold trigger to receive the fourth control signal, and the logic circuit indicates whether the differential signal is noise according to the first control signal, the second control signal, the third control signal, and the fourth control signal.
5. The detection circuit of claim 4, wherein the high threshold flip-flop or the second high threshold flip-flop comprises:
a first resistor, a first end of which is coupled with a power supply, and a second end of which is coupled with a source electrode of the first transistor;
the grid electrode of the first transistor is coupled with a second node, the drain electrode of the first transistor is coupled with a third node, and the second node receives the positive phase signal or the negative phase signal;
a second resistor, a first end of which is coupled to the power supply, and a second end of which is coupled to the source of the second transistor;
the grid electrode of the second transistor is coupled with a fifth node, and the drain electrode of the second transistor is coupled with the third node;
a third transistor, a gate of the third transistor is coupled to the second node, a source of the third transistor is coupled to the third node, and a drain of the third transistor is coupled to a fourth node;
the input end of the first inverter is coupled with the fourth node, and the output end of the first inverter is coupled with the fifth node;
a second inverter, an input terminal of which is coupled to the fifth node;
the input end of the third inverter is coupled with the output end of the second inverter, and the output end of the third inverter is the output end of the high threshold trigger or the second high threshold trigger and is used for outputting the first control signal or the fourth control signal;
a fourth transistor, a gate of the fourth transistor is coupled to the second node, a drain of the fourth transistor is coupled to the fourth node, and a source of the fourth transistor is coupled to a drain of the fifth transistor;
the grid electrode of the fifth transistor is coupled with the second node, and the drain electrode of the fifth transistor is coupled with the first end of the third resistor; and
the second resistor is grounded at the second end of the second resistor.
6. The detection circuit of claim 5, wherein the first positive threshold and the first negative threshold may be adjusted by adjusting the first resistance or the second resistance or the third resistance.
7. The detection circuit of claim 4, wherein the logic circuit inverts the third control signal to obtain a third inverted control signal;
when at least one of the first control signal, a second inverted control signal, the third inverted control signal and the fourth control signal is at the second level, the output signal has the second level, indicating that the differential signal is not noise, the second inverted control signal being generated by the logic circuit inverting the second control signal; and
when the first control signal, the second inverted control signal, the third inverted control signal and the fourth control signal are both at the first level, the output signal has the first level, indicating that the differential signal is noise.
8. The detection circuit of claim 7, wherein the logic circuit comprises:
a first inverter coupled to the low threshold flip-flop to receive the second control signal, the first inverter inverting the second control signal to obtain the second inverted control signal;
a second inverter coupled to the second low threshold flip-flop to receive the third control signal, the second inverter inverting the third control signal to obtain the third inverted control signal;
a first transistor, a gate of which receives the first control signal, a source of which is grounded, and a drain of which is coupled to a first node;
a second transistor, a gate of which receives the second inverted control signal, a source of which is grounded, and a drain of which is coupled to the first node;
a third transistor, a gate of which receives the third inversion control signal, a source of which is grounded, and a drain of which is coupled to the first node;
a fourth transistor having a gate receiving the fourth control signal, a source grounded, and a drain coupled to the first node;
one end of the pull-up resistor is coupled with a power supply, and the other end of the pull-up resistor is coupled with the first node;
one end of the capacitor is coupled with the first node, and the other end of the capacitor is grounded; and
the input end of the third inverter is coupled with the first node, and the output end of the third inverter is the output end of the logic circuit and is used for outputting the output signal; wherein,,
when the first control signal, the second inverted control signal, the third inverted control signal, and the fourth control signal are both at the first level, the first transistor, the second transistor, the third transistor, and the fourth transistor are turned off, so that the voltage of the first node is at the second level, and the output signal is at the first level; and
when at least one of the first control signal, the second inverted control signal, the third inverted control signal and the fourth control signal is at the second level, the first transistor, the second transistor, the third transistor and at least one of the fourth transistor are turned on, so that the voltage of the first node is at the first level, and the output signal is at the second level.
9. The detection circuit of claim 4, further comprising a first voltage level shifter and a second voltage level shifter;
the first voltage level converter receives a prepositive positive phase signal, adjusts the direct current level of the prepositive positive phase signal to a specific voltage, and outputs the positive phase signal to the high threshold trigger and the second low threshold trigger; and
the second voltage level converter receives a pre-negative phase signal, adjusts the direct current level of the pre-negative phase signal to the specific voltage, outputs the negative phase signal to the low threshold trigger and the second high threshold trigger,
wherein the specific voltage is equal to an average of the first positive-going threshold and the second negative-going threshold.
10. The detection circuit of claim 4, wherein the low threshold flip-flop or the second low threshold flip-flop comprises:
a fourth resistor, a first end of which is coupled to the power supply, and a second end of which is coupled to the source of the sixth transistor;
the grid electrode of the sixth transistor is coupled with a sixth node, the drain electrode of the sixth transistor is coupled with the source electrode of a seventh transistor, and the sixth node receives the positive phase signal or the negative phase signal;
the gate of the seventh transistor is coupled to the sixth node, and the drain of the seventh transistor is coupled to the eighth node;
the input end of the fourth inverter is coupled with the eighth node, and the output end of the fourth inverter is coupled with the ninth node;
a fifth inverter, an input terminal of which is coupled to the ninth node;
the input end of the sixth inverter is coupled with the output end of the fifth inverter, and the output end of the sixth inverter is the output end of the low threshold trigger or the second low threshold trigger and is used for outputting the second control signal or the third control signal;
an eighth transistor having a gate coupled to the sixth node, a source coupled to a seventh node, and a drain coupled to the eighth node;
a ninth transistor, a gate of which is coupled to the sixth node, a source of which is coupled to a first end of a fifth resistor, and a drain of which is coupled to the seventh node;
the second end of the fifth resistor is grounded;
a tenth transistor, a gate of the tenth transistor is coupled to the ninth node, a source of the tenth transistor is coupled to a first end of a sixth resistor, and a drain of the tenth transistor is coupled to the seventh node; and
the second end of the sixth resistor is grounded.
11. The detection circuit of claim 10, wherein the second positive threshold or the second negative threshold may be adjusted by adjusting the fourth resistance or the fifth resistance or the sixth resistance.
12. The detection circuit of claim 1, further comprising a first voltage level shifter and a second voltage level shifter;
the first voltage level converter receives a prepositive positive phase signal, adjusts the direct current level of the prepositive positive phase signal to a specific voltage, and outputs the positive phase signal to the high threshold trigger; and
the second voltage level converter receives the prepositive negative phase signal, adjusts the direct current level of the prepositive negative phase signal to the specific voltage so as to output the negative phase signal to the low threshold trigger,
wherein the specific voltage is equal to an average of the first positive-going threshold and the second negative-going threshold.
13. The detection circuit of claim 12, wherein the first voltage level shifter or the second voltage level shifter comprises:
a second capacitor, wherein a first end of the second capacitor receives the prepositive positive phase signal or the prepositive negative phase signal, and a second end of the second capacitor is coupled to a tenth node;
a seventh resistor, a first end of which is coupled to the power supply, and a second end of which is coupled to the source of the eleventh transistor;
the eleventh transistor has a gate coupled to the tenth node and a drain coupled to a source of the twelfth transistor;
the twelfth transistor has a gate coupled to the tenth node and a drain coupled to the tenth node;
a thirteenth transistor having a gate coupled to the tenth node, a source coupled to a drain of the fourteenth transistor, and a drain coupled to the tenth node;
the fourteenth transistor has a gate coupled to the tenth node and a source coupled to the first end of the eighth resistor; and
the second end of the eighth resistor is grounded,
the tenth node is an output end of the first voltage level converter or the second voltage level converter, and is configured to output the positive phase signal or the negative phase signal.
14. The detection circuit of claim 13, wherein a dc voltage of the positive phase signal or the negative phase signal can be adjusted by adjusting the seventh resistor or the eighth resistor.
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| CN1691509A (en) * | 2004-04-28 | 2005-11-02 | 精工爱普生株式会社 | Differential current mode phase/frequency detector circuit |
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