CN114300939A - VCSEL structure with high beam quality and preparation method - Google Patents

Abstract

The invention discloses a VCSEL structure with high beam quality and a preparation method thereof.A VCSEL chip epitaxial structure comprises a P-type DBR layer, an oxidation layer, a P-type waveguide layer, a semiconductor multi-quantum well layer, an N-type waveguide layer, an N-type DBR layer and a substrate layer which are sequentially arranged from top to bottom; the upper surface of the P-type DBR layer is etched to form a photonic crystal structure, the side surface of the P-type DBR layer is formed with an ion implantation current inhibition area through ion implantation, and the middle part of the oxide layer is formed with an oxidation hole; the top or the bottom of the epitaxial structure of the VCSEL chip is provided with an optical resonant external cavity. The invention firstly decouples the current limiting effect (oxidized hole + ion injection current suppression region) and the optical limiting effect (photonic crystal structure) in the VCSEL device, establishes the determined phase relation among the light-emitting units by adding the optical resonance external cavity, improves the laser beam quality, and finally outputs the narrow-linewidth high-beam-quality laser.

Description

VCSEL structure with high beam quality and preparation method

Technical Field

The invention relates to the technical field of semiconductor laser, in particular to a VCSEL structure with high beam quality and a preparation method thereof.

Background

Vertical Cavity Surface Emitting Lasers (VCSELs) have the advantages of good monochromaticity, single longitudinal mode lasing, low threshold current, low power consumption, easiness in two-dimensional integration, round light spots, easiness in coupling with optical fibers, on-chip detection, low cost and the like, and are widely applied to the fields of laser printing, 3D sensing, optical communication, optical storage and the like.

In practical applications, most fields require VCSELs with high beam quality, especially to maintain high output power; however, the conventional VCSEL has the problems of low output power, large divergence angle, poor beam quality, and high-order transverse mode.

The photonic crystal structure is an effective way for improving the VCSEL working mode, is similar to the traditional step type optical fiber, introduces a periodic air hole structure with the refractive index smaller than that of a central defect at the outer layer of the defect, and utilizes the total internal reflection principle to restrain a transverse optical field.

The conventional photonic crystal VCSEL adopts an oxidation limiting structure to control the injection current, but the oxidation aperture of the conventional photonic crystal VCSEL is generally much larger than the light-emitting aperture of the conventional photonic crystal VCSEL, and the threshold current is larger. The ion implantation method is also an ideal method for confining current, and can accurately control the size of the current aperture by accurately controlling the impurity content (implantation dose) and the penetration depth (implantation energy).

For a traditional array type VCSEL, the operation states of all light emitting units are mutually independent, emergent light is mutually incoherent or partially coherent, and no determined phase relation exists, so that the far field distribution space characteristic of a VCSEL chip is poor, and energy distribution is dispersed; therefore, spatial phase locking is important.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a VCSEL structure with high beam quality and a preparation method thereof, and laser output with high beam quality is realized.

The invention discloses a VCSEL structure with high beam quality, which comprises: a VCSEL chip epitaxial structure and an optical resonance external cavity;

the VCSEL chip epitaxial structure comprises a P-type DBR layer, an oxidation layer, a P-type waveguide layer, a semiconductor multi-quantum well layer, an N-type waveguide layer, an N-type DBR layer and a substrate layer which are sequentially arranged from top to bottom;

after the upper surface of the P-type DBR layer is etched, metal is filled in the air hole to form a photonic crystal structure for optical confinement;

the oxidation layer is oxidized from the side surface to form an oxidation hole in the middle; implanting ions into the P-type DBR layer from the side to form an ion implantation current suppression region to form an electric implantation region in the middle; performing current limiting based on the oxidized pores and the electrical injection region;

the optical resonant external cavity comprises an optical mode loss layer and a semi-reflecting and semi-transmitting layer, wherein the optical mode loss layer is formed on the lower surface of the substrate layer, the semi-reflecting and semi-transmitting layer is formed on the lower surface of the optical mode loss layer, or an external cavity mirror is placed at the top of the VCSEL chip epitaxial structure, the optical mode loss layer is formed on the upper surface of the external cavity mirror, and the semi-reflecting and semi-transmitting layer is formed on the upper surface of the optical mode loss layer.

As a further improvement of the invention, the VCSEL chip is a single-tube type VCSEL chip or an array type VCSEL chip, and the structure of the VCSEL chip is a top emission structure or a bottom emission structure.

As a further improvement of the present invention, the ions implanted to form the ion implantation current suppression region are hydrogen ions.

As a further improvement of the invention, the distance between the ion implantation current confinement region and the semiconductor multi-quantum well layer is 1.5-2.5 μm.

As a further improvement of the invention, the pore diameter of the oxidation pore is larger than the radial diameter of the electric injection region.

As a further improvement of the present invention, the photonic crystal structure is a hexagonal structure defined by air hole diameter and lattice period, and the photonic crystal structure is prepared by electron beam exposure and ICP etching.

As a further improvement of the invention, one or more air holes are removed from the center of the photonic crystal structure to form a central defect, namely a light-emitting window is formed; and heat-conducting metal is filled in the air holes to form a metal filling layer.

As a further improvement of the invention, the optical mode loss layer is a convex-concave structure of an infrared transmitting optical material, the infrared transmitting optical material forms a refractive index difference with metal filled in the photonic crystal structure, and the infrared transmitting optical material comprises SiO₂And Si₃N₄One kind of (1).

As a further improvement of the invention, the reflectivity of the semi-reflecting and semi-transmitting layer to laser is 50-90%.

The invention also discloses a preparation method of the VCSEL structure with high beam quality, which comprises the following steps:

step 1, growing a VCSEL chip epitaxial structure; the VCSEL chip epitaxial structure comprises a P-type DBR layer, an oxidation layer, a P-type waveguide layer, a semiconductor multi-quantum well layer, an N-type waveguide layer, an N-type DBR layer and a substrate layer which are sequentially arranged from top to bottom;

step 2, performing ion implantation on the P-type DBR layer to form an ion implantation current suppression area;

step 3, manufacturing a table top from top to bottom to the upper surface of the N-type DBR layer;

step 4, carrying out outer side oxidation on the oxide layer to manufacture an oxidation hole;

step 5, manufacturing a P electrode on the P-type DBR layer, and manufacturing an N electrode on the N-type DBR layer;

step 6, etching and filling metal on the upper surface of the P-type DBR layer to form a photonic crystal structure for optical confinement;

step 7, preparing an optical resonance external cavity at the top or the bottom of the VCSEL chip epitaxial structure;

and 8, cleavage and packaging.

Compared with the prior art, the invention has the beneficial effects that:

the method comprises the steps of firstly decoupling a current limiting effect and an optical limiting effect in a VCSEL device, wherein the current limiting effect is realized by combining selective oxidation and ion implantation, an oxidation hole introduced by an oxidation layer can play a role in reducing transverse optical loss and leakage current, and the optical limiting effect is realized by a photonic crystal structure; based on the method, the problems that the traditional VCSEL is large in divergence angle, a transverse mode is generally a high-order mode and the like are solved; secondly, the phase relation determined among the light-emitting units can be established by adding the optical resonant external cavity, the laser beam quality is improved, the problems of poor far-field distribution space characteristic, very dispersed energy distribution, poor beam quality and the like of the traditional array semiconductor laser are solved, and finally the narrow-linewidth high-beam-quality laser is output.

Drawings

FIG. 1 is a schematic diagram of a high beam quality VCSEL structure according to an embodiment of the present invention;

FIG. 2 is a schematic view of a single-defect photonic crystal structure according to an embodiment of the present invention;

FIG. 3 is a flow chart of a method for fabricating a high beam quality VCSEL structure according to an embodiment of the present invention;

fig. 4 is a schematic diagram of the fabrication of a VCSEL structure with high beam quality disclosed in embodiment 1 of the present invention;

fig. 5 is a schematic diagram of a VCSEL structure with high beam quality according to embodiment 2 of the present invention.

In the figure:

1. a P-type DBR layer; 2. a photonic crystal structure; 3. an ion implantation current suppression region; 4. an oxide layer; 5. a P-type waveguide layer; 6. a semiconductor multi-quantum well layer; 7. an N-type waveguide layer; 8. an N-type DBR layer; 9. a substrate layer; 10. an optical mode loss layer; 11. a semi-reflective and semi-transparent layer; 12. and a metal filling layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

The invention is described in further detail below with reference to the attached drawing figures:

as shown in fig. 1, the present invention provides a high beam quality VCSEL structure, comprising: a VCSEL chip epitaxial structure and an optical resonance external cavity; wherein the content of the first and second substances,

the VCSEL chip epitaxial structure comprises a P-type DBR layer 1, an oxidation layer 4, a P-type waveguide layer 5, a semiconductor multi-quantum well layer 6, an N-type waveguide layer 7, an N-type DBR layer 8 and a substrate layer 9 which are sequentially arranged from top to bottom; the upper surface of the P-type DBR layer 1 is etched and filled with heat conducting metal to form a photonic crystal structure 2 for optical confinement, the photonic crystal structure 2 provides transverse optical confinement by utilizing a total internal reflection light guiding principle, and the heat conducting metal is filled to realize efficient heat dissipation; the oxidation layer 4 is oxidized from the side surface to form an oxidation hole in the middle; the P-type DBR layer 1 is implanted with ions from the side to form an ion implantation current suppression region (electrical insulation region) 3, an electrical implantation region in the middle is formed based on the confinement of the ion implantation current suppression region 3, current limitation is performed based on the oxidized hole and the electrical implantation region, the ion implantation current suppression region provides a current limiting function, and the oxidized layer 4 introduces an oxidized hole diameter to reduce lateral optical loss and leakage current.

Furthermore, the VCSEL chip is a single-tube VCSEL chip or an array VCSEL chip, and the structure of the VCSEL chip is a top emission structure or a bottom emission structure; the ions injected to form the ion injection current inhibition region 3 are hydrogen ions, and the distance between the maximum concentration position in the ion injection current constraint region 3 or the ion concentration distribution and the semiconductor multi-quantum well layer 6 is 1.5-2.5 μm, preferably 2 μm; the diameter of the oxidized pore is larger than the radial diameter of the electric injection region, that is, the oxidation depth of the oxidized layer 4 is smaller than the radial diameter of the ion injection current suppression region (electric insulation region) 3.

Further, as shown in fig. 2, the photonic crystal structure 2 is a hexagonal structure defined by the air hole diameter b and the lattice period Λ, one or more air holes are removed from the center of the photonic crystal structure to form a central defect, that is, a light-emitting window is formed; the air holes are filled with heat-conducting metal to form a metal filling layer 12; the photonic crystal structure is prepared by electron beam exposure and ICP etching, and the central defect can be a single defect, a seven defect or a nineteen defect and other structures.

The optical resonant external cavity comprises an optical mode loss layer 10 and a semi-reflecting and semi-transmitting layer 11, namely the optical mode loss layer 10 is positioned at the inner side of the semi-reflecting and semi-transmitting layer 11, the optical mode loss layer 10 is a convex-concave structure of an infrared transmitting optical material, the infrared transmitting optical material and metal filled in a photonic crystal structure form refractive index difference, and the infrared transmitting optical material comprises SiO₂And Si₃N₄And the reflectivity of the semi-reflecting and semi-transmitting layer 11 to laser is 50-90%. That is, the optical mode loss layer 10 is formed on the lower surface of the substrate layer 9 and the semi-reflective and semi-transparent layer 11Formed on the lower surface of the optical mode loss layer 10 to constitute a bottom emission VCSEL; or, an external cavity mirror is placed on the top of the epitaxial structure of the VCSEL chip, the optical mode loss layer 10 is formed on the upper surface of the external cavity mirror, and the semi-reflecting and semi-transmitting layer 11 is formed on the upper surface of the optical mode loss layer 10 to form a top-emitting VCSEL.

As shown in fig. 3, the present invention provides a method for manufacturing a VCSEL structure with high beam quality, which includes:

step 1, growing a VCSEL chip epitaxial structure; the VCSEL chip epitaxial structure comprises a P-type DBR layer 1, an oxidation layer 4, a P-type waveguide layer 5, a semiconductor multi-quantum well layer 6, an N-type waveguide layer 7, an N-type DBR layer 8 and a substrate layer 9 which are sequentially arranged from top to bottom;

step 2, performing ion implantation on the P-type DBR layer 1 to form an ion implantation current suppression region 3;

step 3, manufacturing a table top from top to bottom to the upper surface of the N-type DBR layer 8;

step 4, carrying out outer side oxidation on the oxide layer 4 to manufacture an oxidation hole;

step 5, manufacturing a P electrode on the P-type DBR layer 1, and manufacturing an N electrode on the N-type DBR layer 8;

step 6, etching and filling metal on the upper surface of the P-type DBR layer 1 to form a photonic crystal structure 2 for optical confinement;

step 7, preparing an optical resonance external cavity at the top or the bottom of the VCSEL chip epitaxial structure;

and 8, cleavage and packaging.

Example 1:

as shown in fig. 4, the present invention provides a VCSEL structure with high beam quality and a method for fabricating the same, comprising:

step a, growing an epitaxial structure

Sequentially epitaxially growing an N-type DBR layer, an N-type waveguide layer, a semiconductor multi-quantum well layer, a P-type waveguide layer, an oxide layer and a P-type DBR layer on the surface of the GaAs substrate;

step b, ion implantation

After the epitaxial wafer is cleaned, the epitaxial wafer is blown dry by high-purity nitrogen protection and is heated and dried, and firstly, PECVD is adopted to deposit SiO with certain thickness₂Or Si₃N₄And protecting the surface of the implanted region of the epitaxial wafer from being damaged by ion implantation, and after photoetching development, overlapping a thick photoresist on the non-implanted region to prevent ion implantation. Selecting proper implantation energy and dosage to place the epitaxial wafer into an ion implanter to complete hydrogen ion implantation, and forming an ion implantation current confinement region at a position about 2 microns above the semiconductor multi-quantum well layer;

step c, manufacturing the table top

Firstly, a mesa structure is manufactured on an epitaxial wafer to be processed by adopting methods such as wet etching or dry etching. If an etching method is adopted, Cl is etched₂/BCl₃The gas flow ratio is 1: and 3, etching with the power of 500W to expose the oxide layer. Secondly, the redundant SiO on the chip is etched away by a wet method₂Cleaning the chip; finally, after cleaning, drying the epitaxial wafer to be processed by using high-purity nitrogen, and after ensuring cleanness, heating and drying the wafer for later use;

step d, manufacturing an oxidation hole

And oxidizing the oxide layer in the table top of the epitaxial wafer to be processed from the outer side by using a wet selective oxidation technology to form an oxide aperture. And (3) wet selective oxidation process: heating the oxidation furnace to 430 ℃, setting the water temperature at 100 ℃, and introducing a trace amount of N₂The flow rate is 1L/min, the stability is 20min, and the redundant air in the oxidation furnace is removed. After 20min, start to feed N₂The flow rate is 9L/min, and the stability is 30 min. After stabilizing for 30min, the epitaxial wafer is put into an oxidation furnace for oxidation, and the oxidation time is determined according to the oxidation aperture required to be oxidized. After the oxidation is finished, waiting for the furnace temperature to be reduced to 80 ℃, and taking out the epitaxial wafer for later use;

step e, manufacturing a metal N electrode and a metal P electrode

Coating SU-8 negative photoresist on an epitaxial wafer to be processed, manufacturing an N electrode pattern through photoetching and developing, and then growing an N electrode metal material through metal processes such as magnetron sputtering technology sputtering and the like;

soaking the epitaxial wafer on which the N electrode metal grows in an acetone solution for 4-6 hours, then carrying out a metal stripping process to strip the metal of the non-N electrode and manufacturing a metal N electrode;

coating an L300 negative photoresist on an epitaxial wafer to be processed, manufacturing a pattern of a P electrode through photoetching and developing, and then growing a P electrode metal material through metal processes such as magnetron sputtering technology sputtering and the like;

soaking the epitaxial wafer on which the P electrode metal grows in an acetone solution for 4-6 hours, then carrying out a metal stripping process to strip the metal of the non-P electrode and manufacturing a metal P electrode;

step f, preparing a photonic crystal structure

Firstly, preparing a layer of SiO₂The layer is used as a mask for etching the photonic crystal structure, then a pattern is made by electron beam exposure, and SiO is etched by RIE₂Mask transfers pattern to SiO₂After the layer is formed, etching the epitaxial wafer through ICP to obtain a photonic crystal hole, and filling metal into the photonic crystal hole;

step g, preparing an optical resonant external cavity

Thinning a substrate layer on the back of the epitaxial wafer, photoetching and developing by using a double-sided overlay process, and depositing SiO with a convex-concave structure in a region overlapped with a light outlet hole₂Or Si₃N₄The iso-infrared transmitting optical material forms an optical mode loss layer. The optical mode loss layer can be calculated according to mode coupling theory or external cavity phase-locking theory such as Talbot effect; the external cavity phase lock is characterized in that a certain device or device is adopted outside a VCSEL chip, so that a certain fixed relation is established between phases of emergent light of all light emitting units of the VCSEL chip, the phase lock operation is realized, and the beam quality of the device is improved;

and (3) cleaving the manufactured chip by using a cleaving dicing saw, completing welding with an electrode of an external power supply system by adopting a mode of thermocompression bonding and the like, and completing chip packaging.

Example 2:

as shown in fig. 5, the present invention provides a VCSEL structure with high beam quality and a method for fabricating the same, comprising:

step a, growing an epitaxial structure

Sequentially epitaxially growing an N-type DBR layer, an N-type waveguide layer, a semiconductor multi-quantum well layer, a P-type waveguide layer, an oxide layer and a P-type DBR layer on the surface of the GaAs substrate;

step b, ion implantation

After the epitaxial wafer is cleaned, the epitaxial wafer is blown dry by high-purity nitrogen protection and is heated and dried, and firstly, PECVD is adopted to deposit SiO with certain thickness₂Or Si₃N₄And protecting the surface of the implanted region of the epitaxial wafer from being damaged by ion implantation, and after photoetching development, overlapping a thick photoresist on the non-implanted region to prevent ion implantation. Selecting proper implantation energy and dosage to place the epitaxial wafer into an ion implanter to complete hydrogen ion implantation, and forming an ion implantation current confinement region at a position about 2 microns above the semiconductor multi-quantum well layer;

step c, manufacturing the table top

Firstly, a mesa structure is manufactured on an epitaxial wafer to be processed by adopting methods such as wet etching or dry etching. If an etching method is adopted, Cl is etched₂/BCl₃The gas flow ratio is 1: and 3, etching with the power of 500W to expose the oxide layer. Secondly, the redundant SiO on the chip is etched away by a wet method₂Cleaning the chip; finally, after cleaning, drying the epitaxial wafer to be processed by using high-purity nitrogen, and after ensuring cleanness, heating and drying the wafer for later use;

step d, manufacturing an oxidation hole

And oxidizing the oxide layer in the table top of the epitaxial wafer to be processed from the outer side by using a wet selective oxidation technology to form an oxide aperture. And (3) wet selective oxidation process: heating the oxidation furnace to 430 ℃, setting the water temperature at 100 ℃, and introducing a trace amount of N₂The flow rate is 1L/min, the stability is 20min, and the redundant air in the oxidation furnace is removed. After 20min, start to feed N₂The flow rate is 9L/min, and the stability is 30 min. After stabilizing for 30min, the epitaxial wafer is put into an oxidation furnace for oxidation, and the oxidation time is determined according to the oxidation aperture required to be oxidized. After the oxidation is finished, waiting for the furnace temperature to be reduced to 80 ℃, and taking out the epitaxial wafer for later use;

step e, manufacturing a metal N electrode and a metal P electrode

Coating SU-8 negative photoresist on an epitaxial wafer to be processed, manufacturing an N electrode pattern through photoetching and developing, and then growing an N electrode metal material through metal processes such as magnetron sputtering technology sputtering and the like;

soaking the epitaxial wafer on which the N electrode metal grows in an acetone solution for 4-6 hours, then carrying out a metal stripping process to strip the metal of the non-N electrode and manufacturing a metal N electrode;

coating an L300 negative photoresist on an epitaxial wafer to be processed, manufacturing a pattern of a P electrode through photoetching and developing, and then growing a P electrode metal material through metal processes such as magnetron sputtering technology sputtering and the like;

soaking the epitaxial wafer on which the P electrode metal grows in an acetone solution for 4-6 hours, then carrying out a metal stripping process to strip the metal of the non-P electrode and manufacturing a metal P electrode;

step f, preparing a photonic crystal structure

Firstly, preparing a layer of SiO₂The layer is used as a mask for etching the photonic crystal structure, then a pattern is made by electron beam exposure, and SiO is etched by RIE₂Mask transfers pattern to SiO₂After the layer is formed, etching the epitaxial wafer through ICP to obtain a photonic crystal hole, and filling metal into the photonic crystal hole;

step g, preparing an optical resonant external cavity

Placing an external cavity mirror on the surface of a light-emitting window of an epitaxial wafer and depositing SiO with a convex-concave structure₂Or Si₃N₄The optical mode loss layer is formed by the equal-transmission infrared optical material and can be calculated according to mode coupling theory or external cavity phase-locking theory such as Talbot effect;

and (3) cleaving the manufactured chip by using a cleaving dicing saw, completing welding with an electrode of an external power supply system by adopting a mode of thermocompression bonding and the like, and completing chip packaging.

The invention has the advantages that:

the method comprises the steps of firstly decoupling a current limiting effect and an optical limiting effect in a VCSEL device, wherein the current limiting effect is realized by combining selective oxidation and ion implantation, an oxidation hole introduced by an oxidation layer can play a role in reducing transverse optical loss and leakage current, and the optical limiting effect is realized by a photonic crystal structure; based on the method, the problems that the traditional VCSEL is large in divergence angle, a transverse mode is generally a high-order mode and the like are solved; secondly, the phase relation determined among the light-emitting units can be established by adding the optical resonant external cavity, the laser beam quality is improved, the problems of poor far-field distribution space characteristic, very dispersed energy distribution, poor beam quality and the like of the traditional array semiconductor laser are solved, and finally the narrow-linewidth high-beam-quality laser is output.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A high beam quality VCSEL structure, comprising: a VCSEL chip epitaxial structure and an optical resonance external cavity;

the VCSEL chip epitaxial structure comprises a P-type DBR layer, an oxidation layer, a P-type waveguide layer, a semiconductor multi-quantum well layer, an N-type waveguide layer, an N-type DBR layer and a substrate layer which are sequentially arranged from top to bottom;

after the upper surface of the P-type DBR layer is etched, metal is filled in the air hole to form a photonic crystal structure for optical confinement;

the oxidation layer is oxidized from the side surface to form an oxidation hole in the middle; implanting ions into the P-type DBR layer from the side to form an ion implantation current suppression region to form an electric implantation region in the middle; performing current limiting based on the oxidized pores and the electrical injection region;

the optical resonant external cavity comprises an optical mode loss layer and a semi-reflecting and semi-transmitting layer, wherein the optical mode loss layer is formed on the lower surface of the substrate layer, the semi-reflecting and semi-transmitting layer is formed on the lower surface of the optical mode loss layer, or an external cavity mirror is placed at the top of the VCSEL chip epitaxial structure, the optical mode loss layer is formed on the upper surface of the external cavity mirror, and the semi-reflecting and semi-transmitting layer is formed on the upper surface of the optical mode loss layer.

2. The high beam quality VCSEL structure of claim 1, wherein the VCSEL chip is a single-tube VCSEL chip or an array VCSEL chip, and the VCSEL structure is a top-emission structure or a bottom-emission structure.

3. The VCSEL structure of claim 1, wherein the ions implanted to form the ion implantation current suppression region are hydrogen ions.

4. The VCSEL structure of claim 3, wherein a distance between the ion implantation current confinement region and the semiconductor multiple quantum well layer is 1.5 to 2.5 μm.

5. The high beam quality VCSEL structure of claim 1, wherein an aperture of the oxidized aperture is larger than a radial diameter of the electrical implant region.

6. The high beam quality VCSEL structure of claim 1, wherein the photonic crystal structure is a hexagonal structure defined by air hole diameter and lattice period, the photonic crystal structure being fabricated by e-beam exposure and ICP etching.

7. The high beam quality VCSEL structure of claim 6, wherein one or more air holes are removed in the center of the photonic crystal structure to form a central defect, i.e., to form an exit window; and heat-conducting metal is filled in the air holes to form a metal filling layer.

8. The high beam quality VCSEL structure of claim 1, wherein the optical mode loss layer is a relief structure of an infrared transparent optical material forming a refractive index difference with a metal filled in the photonic crystal structure, the infrared transparent optical material comprising SiO₂And Si₃N₄One kind of (1).

9. The high beam quality VCSEL structure of claim 8, wherein said transflective layer has a reflectivity of 50% to 90% for laser light.

10. A method for fabricating a VCSEL structure with high beam quality according to any of claims 1 to 9, comprising:

step 1, growing a VCSEL chip epitaxial structure; the VCSEL chip epitaxial structure comprises a P-type DBR layer, an oxidation layer, a P-type waveguide layer, a semiconductor multi-quantum well layer, an N-type waveguide layer, an N-type DBR layer and a substrate layer which are sequentially arranged from top to bottom;

step 2, performing ion implantation on the P-type DBR layer to form an ion implantation current suppression area;

step 3, manufacturing a table top from top to bottom to the upper surface of the N-type DBR layer;

step 4, carrying out outer side oxidation on the oxide layer to manufacture an oxidation hole;

step 5, manufacturing a P electrode on the P-type DBR layer, and manufacturing an N electrode on the N-type DBR layer;

step 6, etching and filling metal on the upper surface of the P-type DBR layer to form a photonic crystal structure for optical confinement;

step 7, preparing an optical resonance external cavity at the top or the bottom of the VCSEL chip epitaxial structure;

and 8, cleavage and packaging.

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