CN114285514A - Clock synchronization method and device - Google Patents
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Abstract
The invention discloses a clock synchronization method and a clock synchronization device, wherein a specific embodiment comprises the steps of acquiring GPS time information and Beidou time information, inputting the GPS time information and the Beidou time information into an ARM main control processor, converting the GPS time information and the Beidou time information through a DA circuit, and adjusting the GPS time information and the ARM main control processor through an oscillator to generate local clock time information; the GPS time information, the Beidou time information and the local clock time information are input into the FPGA to inquire the time information stored by the sequential circuit, whether a plurality of pieces of valid GPS time information or a plurality of pieces of valid Beidou time information exist in a preset time period from the current time is judged, if yes, the input GPS time information or the Beidou time information is output as a clock source, and if not, the input local clock time information is output as a clock source. Therefore, the invention can solve the problems of limited application, high cost and poor reliability of the existing clock source.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a clock synchronization method and a clock synchronization device.
Background
The clock source is widely applied to various old-age care and medical scenes and used for synchronizing time service and data acquisition control of terminals of the Internet of things. The problem that various existing Internet of things devices are not unified in standard time, are mutually isolated and cannot be used comprehensively due to different data is solved.
In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art:
the existing clock source can ensure high precision to be an atomic clock and a time service workstation, but the existing clock source has the defects of large volume and high price and is difficult to be applied in communities and hospitals in large area. Although the prices of other clock sources in the market are still reasonable, the design schemes of the GPS and the Beidou are adopted, under the condition that the GPS and the Beidou satellite signals are poor, the output clock jumps and swings greatly, so that the clock offset of several seconds is large, the data is unreliable, and the reliability and the precision of time service are influenced.
Disclosure of Invention
In view of this, embodiments of the present invention provide a clock synchronization method and apparatus, which can solve the problems of limited application, high cost and poor reliability of the existing clock source.
In order to achieve the above object, according to an aspect of the embodiments of the present invention, there is provided a clock synchronization method, including obtaining GPS time information and beidou time information, inputting the GPS time information and beidou time information to an ARM master processor, so as to generate local clock time information through DA circuit conversion and oscillator adjustment; the GPS time information, the Beidou time information and the local clock time information are input into the FPGA to inquire the time information stored by the sequential circuit, whether a plurality of pieces of valid GPS time information or a plurality of pieces of valid Beidou time information exist in a preset time period from the current time is judged, if yes, the input GPS time information or the Beidou time information is output as a clock source, and if not, the input local clock time information is output as a clock source.
Optionally, the GPS time information includes a GPS second pulse signal and GPS serial port time data, and the beidou time information includes a beidou second pulse signal and beidou serial port time data;
according to the GPS serial port time data or the Beidou serial port time data, the inquiry time sequence circuit determines that a plurality of effective GPS serial port time data or a plurality of effective Beidou serial port time data exist in a preset time period away from the current time, and then the GPS second pulse signal or the Beidou second pulse signal is output as a clock source.
Optionally, the local clock time information includes a local clock-second pulse signal and a local clock universal time code;
and if the plurality of effective GPS time information or the plurality of effective Beidou time information do not exist within the preset time period from the current time, outputting a local clock second pulse signal, and outputting the local clock universal time code after the local clock universal time code is processed by a decoding and encoding circuit in the FPGA.
Optionally, the input is to an ARM master processor, including:
the method comprises the steps that received GPS serial port time data or Beidou serial port time data are obtained through a UART interface of an ARM main control processor, and GPS second pulse signals or Beidou second pulse signals are obtained through an input capture pin of the ARM main control processor; the GPS time information comprises a GPS second pulse signal and GPS serial port time data, and the Beidou time information comprises a Beidou second pulse signal and Beidou serial port time data.
Optionally, after generating the local clock time information, the method includes:
outputting a local clock second pulse signal through a matching output pin of the ARM main control processor, and outputting a local clock universal time code through a serial peripheral interface of the ARM main control processor; the local clock time information comprises a local clock second pulse signal and a local clock universal time code.
Optionally, the local clock time information is generated by DA circuit conversion and oscillator adjustment, including:
reading current GPS time information, judging whether an effective mark exists in the current GPS time information, and if so, calculating to obtain local clock time information according to the GPS time information in a preset time period including the current GPS time information; if not, reading current Beidou time information, judging whether an effective identifier exists in the current Beidou time information, and if so, calculating according to the Beidou time information in a preset time period including the current Beidou time information to obtain local clock time information; if not, calling a preset estimation model to obtain estimated Beidou time information, and further calculating according to the Beidou time information in a preset time period including the estimated Beidou time information to obtain local clock time information;
calculating a crystal oscillator error according to the local clock time information, judging whether the crystal oscillator error is larger than a preset error threshold value, if so, adjusting the numerical value of a DA circuit to obtain an output voltage, and adjusting the output frequency of an oscillator according to the output voltage to generate final local clock time information; and if not, taking the local clock time information as final local clock time information.
Optionally, inserting the current GPS time information into a preset GPS time information queue to obtain local clock time information by calculating an average value of the GPS time information within a preset time period; or
Inserting the current Beidou time information into a preset Beidou time information queue to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period; or
And inserting the estimated Beidou time information into a preset Beidou time information queue so as to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period.
In addition, the invention also provides a clock synchronization device, which comprises an acquisition module, a local clock synchronization module and a local clock synchronization module, wherein the acquisition module is used for acquiring the GPS time information and the Beidou time information, inputting the GPS time information and the Beidou time information into the ARM main control processor, and generating the local clock time information through DA circuit conversion and oscillator adjustment; and the processing module is used for inputting the GPS time information, the Beidou time information and the local clock time information into the FPGA to inquire the time information stored by the sequential circuit, judging whether a plurality of pieces of valid GPS time information or a plurality of pieces of valid Beidou time information exist in a preset time period away from the current time, outputting the input GPS time information or the Beidou time information as a clock source if the time information is valid, and outputting the input local clock time information as the clock source if the time information is not valid.
One embodiment of the above invention has the following advantages or benefits: the invention realizes a clock source with low cost, high precision and high stability by hardware circuit design, embedded software algorithm and FPGA logic design; the method has the advantages that stable standard time information is provided, time service of a plurality of nodes of the Internet of things can be realized, data have uniform time, the uniform analysis and processing can be provided for a system, different requirements are met, and a larger effect is achieved; and the method has the advantages of having the best cost performance, reducing the cost of purchasing similar products, reducing the operation cost and enabling the data time of the nodes of the Internet of things to be unified and comprehensively used.
Further effects of the above-mentioned non-conventional alternatives will be described below in connection with the embodiments.
Drawings
The drawings are included to provide a better understanding of the invention and are not to be construed as unduly limiting the invention. Wherein:
FIG. 1 is a schematic diagram of a main flow of a clock synchronization method according to an embodiment of the invention;
FIG. 2 is a block diagram of a hardware body according to an embodiment of the invention;
FIG. 3 is a schematic diagram of the main flow of an ARM host controller according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a main body frame of an ARM main controller according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the main flow of an FPGA according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a body frame of an FPGA according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the main blocks of a clock synchronization apparatus according to an embodiment of the present invention;
FIG. 8 is an exemplary device architecture diagram in which embodiments of the present invention may be employed;
fig. 9 is a schematic structural diagram of a computer apparatus of a terminal device or a server suitable for implementing an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention are described below with reference to the accompanying drawings, in which various details of embodiments of the invention are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Fig. 1 is a schematic diagram of a main flow of a clock synchronization method according to an embodiment of the present invention, the clock synchronization method including:
and S101, acquiring GPS time information and Beidou time information, inputting the GPS time information and the Beidou time information into an ARM main control processor, converting the GPS time information and the Beidou time information through a DA circuit, and adjusting the GPS time information and the ARM main control processor to generate local clock time information through an oscillator.
In an embodiment, as shown in fig. 2, the ARM serves as a master CPU processor, for example, a Linux operating system may be run as a core of the system, and functions such as data acquisition management, data storage, and data service are provided. Meanwhile, the input capture and output matching inside the ARM chip, the oscillator and the DA circuit realize the function of the local clock together. The oscillator adopts a voltage-controlled crystal oscillator (namely, a crystal oscillator) to provide clock pulses of the whole circuit. The crystal oscillator adopts a TCXO module with stability superior to 1ppm in Dapu T11A series, and has a voltage-controlled input end, so that the frequency of the crystal oscillator can be adjusted. The DA circuit can adopt a high-precision DA chip, and the purpose of adjusting the frequency of the crystal oscillator is achieved by controlling the voltage of the voltage-controlled crystal oscillator. That is, a high precision adjustable voltage controlled crystal oscillator on the circuit board provides an oscillating signal as a reference pulse. The 10-bit D/A converter and the voltage regulating circuit in the circuit can change the output frequency of the voltage-controlled crystal oscillator through voltage regulation. In addition, GPS can select UBOX company's GPS receiving module and supporting antenna, and big dipper can select UBOX company's big dipper receiving module and supporting antenna.
In some embodiments, the input to the ARM master processor includes: the GPS second pulse signal or the Beidou second pulse signal is obtained through an input capture pin of the ARM main control processor. The GPS time information comprises a GPS second pulse signal and GPS serial port time data, and the Beidou time information comprises a Beidou second pulse signal and Beidou serial port time data.
For example, ARM has 2 32-bit timers or counters inside it (i.e., 4 capture inputs and 4 match output channels). The crystal oscillation circuit supports the frequency of 1-30 MHz, the maximum micro-controller operation frequency of 60MHz can be realized through a PLL (phase-locked loop or phase-locked loop) in a crystal oscillation chip, and the stability time of the PLL is 100 mus.
Preferably, an LEA dual-mode chip is used as a GPS and Beidou signal receiving chip. And serial port time data and second pulse signals of the GPS module and the Beidou module are respectively obtained by externally connecting the GPS and the Beidou antenna. Thus, GPS standard time information can be obtained when GPS satellite synchronization is effective. And Beidou standard time information can be obtained when the Beidou satellite synchronization is effective. The GPS and Beidou dual-module design ensures that the satellite synchronization time can be obtained at the maximum probability.
As still other embodiments, the local clock time information is generated by DA circuit conversion and oscillator adjustment, and the specific implementation process includes: reading current GPS time information, judging whether an effective mark exists in the current GPS time information, and if so, calculating to obtain local clock time information according to the GPS time information in a preset time period including the current GPS time information. And if not, reading the current Beidou time information, judging whether an effective identifier exists in the current Beidou time information, and if so, calculating to obtain local clock time information according to the Beidou time information in a preset time period including the current Beidou time information. If not, calling a preset estimation model to obtain estimated Beidou time information, and further calculating according to the Beidou time information in the preset time period including the estimated Beidou time information to obtain local clock time information.
And calculating a crystal oscillator error according to the local clock time information, judging whether the crystal oscillator error is larger than a preset error threshold value, if so, adjusting the numerical value of the DA circuit to obtain an output voltage, and adjusting the output frequency of the oscillator according to the output voltage to generate final local clock time information. And if not, taking the local clock time information as final local clock time information.
In a preferred embodiment, when the local clock time information is calculated according to the GPS time information within the preset time period including the current GPS time information, the current GPS time information may be inserted into a preset GPS time information queue to obtain the local clock time information by calculating an average of the GPS time information within the preset time period.
The local clock time information is obtained through calculation according to the Beidou time information in the preset time period including the current Beidou time information, and the current Beidou time information can be inserted into a preset Beidou time information queue so as to obtain the local clock time information through calculating the mean value of the Beidou time information in the preset time period.
The local clock time information is obtained through calculation according to the Beidou time information in the preset time period including the estimated Beidou time information, and the estimated Beidou time information can be inserted into a preset Beidou time information queue so as to obtain the local clock time information through calculating the mean value of the Beidou time information in the preset time period.
Step S102, inputting the GPS time information, the Beidou time information and the local clock time information into the FPGA to inquire the time information stored by the sequential circuit, judging whether a plurality of valid GPS time information or a plurality of valid Beidou time information exist in a preset time period from the current time, if so, outputting the input GPS time information or the Beidou time information as a clock source, and if not, outputting the input local clock time information as the clock source.
In an embodiment, as shown in FIG. 2, an FPGA (i.e., a digital integrated circuit chip) carries various portions of hardware circuit data exchange and timing control functions. The FPGA circuit realizes selection, arbitration and switching of three types of time information on hardware. Preferably, a high-precision reference voltage source is selected to provide a stable reference voltage for the whole circuit to work.
In some embodiments, the GPS time information may include a GPS second pulse signal and GPS serial port time data, and the beidou time information includes a beidou second pulse signal and beidou serial port time data. Further, step S102 may query the timing circuit to determine that a plurality of valid GPS serial port time data or a plurality of valid beidou serial port time data exist within a preset time period from the current time according to the GPS serial port time data or the beidou serial port time data, and output the GPS second pulse signal or the beidou second pulse signal as a clock source.
In other embodiments, the local clock time information includes a local clock-second pulse signal and a local clock universal time code. Further, step S102 may determine that there are no valid pieces of GPS time information or valid pieces of beidou time information within a preset time period from the current time, output a local clock-second pulse signal, and output a local clock universal time code after processing by a decoding and encoding circuit in the FPGA.
Therefore, the clock source adopts GPS and Beidou dual-mode input, and simultaneously consists of an embedded processor, a high-precision controllable crystal oscillator and a DA circuit and dynamically maintains a high-precision local clock. And when the dual-mode satellite signals are out of step, the local clock signals are output, so that the reliability of output data can be still ensured. Meanwhile, the judgment, arbitration and switching of the outputs of the GPS, the Beidou and the local clock are realized by a hardware logic circuit of the FPGA, so that the output time deviation and fluctuation caused by software mode operation are solved, a high-precision clock signal is ensured to be output under all conditions, and time service is provided for all terminal nodes.
In summary, the present invention provides a low-cost and high-precision clock source implementation scheme, so that only 1000-ary cost devices obtain output stability similar to an atomic clock, which can be said to be an optimal cost performance scheme of a community clock source. Through system tests of a prototype, under various extreme conditions, even if GPS and Beidou step-out states occur, the time error of a clock source and a PPS reference point of a standard clock is less than 15ns, and the error between the clock source and an absolute time reference point is less than 30 ns. And moreover, terminal nodes of all the internet of things are unified under standard time and are not isolated points any more, the internet of things is connected, various data have unified standard time labels, unified application and analysis are facilitated, the illustrated aged-care smart room is used for time service for various terminal devices, and a hospital hall or a community hall is used for time service for various internet of things devices.
FIG. 3 is a schematic diagram of a main flow of an ARM main controller according to an embodiment of the present invention, including:
step S301, reading current GPS time information.
In an embodiment, as shown in fig. 4, the GPS time information may include a GPS second pulse signal PPS and GPS serial port time data EN, and the ARM receives the GPS second pulse signal PPS through the input capture pin and the GPS serial port time data EN through the UART interface.
For example, the ARM obtains a GPS time packet provided by the LEA receiver per second through the UART interface, and an input capture pin of the ARM timer is connected to the GPS second pulse signal PPS output by the LEA.
Step S302, determining whether the current GPS time information includes a valid identifier, if so, performing step S303, and if not, performing step S304.
Step S303, inserting the current GPS time information into a preset GPS time information queue to obtain local clock time information by calculating an average value of the GPS time information within a preset time period, and performing step S308.
And step S304, reading the current Beidou time information.
In the embodiment, as shown in fig. 4, the big dipper time information can include big dipper second pulse signal PPS and big dipper serial ports time data EN, and the ARM catches round pin through the input and receives big dipper second pulse signal PPS, receives big dipper serial ports time data EN through the UART interface.
Illustratively, the ARM obtains a Beidou time data packet provided by the LEA receiver every second through a UART interface, and an input capture pin of the ARM timer is connected with a Beidou second pulse signal PPS output by the LEA.
Step S305, determining whether an effective identifier exists in the current Beidou time information, if so, performing step S306, and if not, performing step S307.
Step S306, inserting the current Beidou time information into a preset Beidou time information queue to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period, and performing step S308.
Step S307, calling a preset estimation model to obtain estimated Beidou time information, inserting the estimated Beidou time information into a preset Beidou time information queue to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period, and performing step S308.
And step S308, calculating crystal oscillator errors according to the local clock time information.
Step S309, determining whether the crystal oscillator error is greater than a preset error threshold, if so, performing step S310, and otherwise, performing step S311.
Illustratively, according to the values in the queue, calculating the time of occurrence of the local clock-second pulse signal PPS, comparing the time with the standard frequency of 10M, calculating the error of the local second crystal oscillator (crystal oscillator error), preferably putting the local second crystal oscillator error into a 1-minute crystal oscillator error statistical queue, and when the total error is greater than a preset error threshold, indicating that the actual error of the crystal oscillator is too large, calculating parameters and adjusting DA output (step S310); the DA adjustment is ignored when the total error is less than the preset error threshold (step S311). And then writing the value of the local clock-second pulse signal PPS into a matching output register of the ARM to wait for output.
And step S310, adjusting the numerical value of the DA circuit to obtain output voltage, and generating final local clock time information according to the output frequency of the output voltage adjusting oscillator.
And step 311, taking the local clock time information as final local clock time information.
In the embodiment, a local clock second pulse signal PPS is output through a matching output pin of an ARM main control processor, a local clock universal time code (standard IRIG code) is output through a serial peripheral interface SPI of the ARM main control processor and is transmitted to an FPGA, and the output of the clock source PPS signal and the IRIG signal is realized through logic and a sequential circuit inside the FPGA. The local clock time information comprises a local clock second pulse signal and a local clock universal time code.
Illustratively, an ARM internal 32-bit timing counter T0 counts the frequency of a local crystal oscillator all the time, the frequency of the local crystal oscillator is continuously corrected according to a PPS signal, each time the PPS signal arrives, input capture interruption of a timer is triggered, the value of the local counter is recorded, the number of times of recording the local crystal oscillator in one second is calculated by using the difference between two continuous PPS capture values, statistics is carried out according to the number of times of measuring the local crystal oscillator in each second, the local crystal oscillator is calculated to be faster or slower, the output voltage of a 10-bit DA circuit is adjusted according to the result, and therefore the crystal oscillator is adjusted to be 10M standard. And adding one second to obtain the time data EN of the next second according to the GPS or Beidou serial port time data EN transmitted from the UART port, predicting and calculating the timer count value of the next-second Beidou second pulse signal PPS through the count value latched by the GPS or Beidou second pulse signal PPS, writing the timer count value into a matching output register of the timer, and matching and outputting to form a local clock-second pulse waveform.
It is worth explaining that when the GPS or Beidou signals are effective, the voltage can be controlled by continuously changing the DA value, so that the controllable crystal oscillator is stabilized at 10 MHz. When GPS and big dipper signals are invalid, the circuit can keep the high precision of the local clock within a certain time by utilizing the adjusted crystal oscillator and the internal input capture value, the error does not exceed 20ppm, and the second pulse and IRIG information of the local clock are output until the GPS or big dipper is synchronized again. Because the local crystal oscillator is continuously subjected to feedback correction, and the capture input and matching output functions of the ARM timer are utilized, the rising edge of each pulse per second signal PPS output by the local clock is strictly consistent with the GPS and the Beidou, and the high precision of the local clock is ensured.
Fig. 5 is a schematic diagram of a main flow of an FPGA according to an embodiment of the present invention, including:
step S501, GPS time information, Beidou time information and local clock time information are input into the FPGA.
For example, as shown in fig. 6, the FPGA circuit realizes selection, arbitration, and switching of three types of time information, i.e., GPS, beidou, and local clock, in hardware. The GPS antenna and the receiving chip provide GPS time information which comprises a GPS second pulse signal PPS and GPS serial port time data EN; the Beidou antenna and the receiving chip provide Beidou time information which comprises a Beidou second pulse signal PPS and Beidou serial port time data EN. The serial port data information can comprise data frames such as RMC, GGA, GSA and the like, and information such as available satellite number, signal-to-noise ratio, satellite azimuth, satellite elevation, longitude and latitude, elevation number, DOP factor and the like can be analyzed according to the data frames. When the satellite is synchronous, the number of the available satellites is unchanged or increased, other data are stable, and the fluctuation of the number of the available satellites is less than 5%. Before the signal variation satellite is out of step, the number of available satellites is reduced, and other data fluctuate greatly; therefore, the analytic data can reflect the satellite state and provide a basis for pre-judging the effective mark of the mark.
Step S502, a time sequence circuit is inquired, whether a plurality of valid GPS serial port time data or a plurality of valid Beidou serial port time data exist in a preset time period from the current time is judged, if yes, the step S503 is carried out, and if not, the step S504 is carried out.
And S503, outputting the GPS second pulse signal or the Beidou second pulse signal as a clock source.
Step S504, outputting the local clock pulse per second signal, and outputting the local clock universal time code (i.e. IRIG time code) after being processed by a decoding and encoding circuit in the FPGA, for use by external equipment (i.e. time service for each terminal node).
The example is that a time sequence circuit inside the FPGA stores the latest 20 seconds of GPS serial port time data EN (GPS _ EN) or Beidou serial port time data EN (Beidou _ EN), and only when the latest 20 seconds of GPS serial port time data EN (GPS _ EN) or Beidou serial port time data EN (Beidou _ EN) are all effective, the GPS second pulse signal PPS or the Beidou second pulse signal PPS of the GPS serial port time data EN (GPS _ EN) or the Beidou serial port time data EN (Beidou _ EN) can be selected to be output. When the GPS serial port time data EN (GPS _ EN) or the Beidou serial port time data EN do not meet the output condition, the local clock-second pulse signal PPS is selected to be output. Because the serial port data information of the chip arrives about 300 milliseconds before the PPS signal, the ARM and the FPGA have enough processing time, and the FPGA finishes the selection of three paths of signals and the switching of hardware channels 200 milliseconds before the PPS signal is output, the PPS signal cannot generate signal jitter when being output.
In addition, the IRIG information FPGA of the ARM is output through a decoding and encoding circuit, meanwhile, an FIFO (first-in first-out queue) module of the FPGA can perform FPGA data caching, and the data caching capacity of the FPGA is guaranteed. The frequency doubling module of the FPGA can provide time control precision. Wherein, the frequency multiplication is that the frequency of the generated output signal is an integral multiple of the frequency of the input signal.
Fig. 7 is a schematic diagram of main blocks of a clock synchronization apparatus according to an embodiment of the present invention, and as shown in fig. 7, the clock synchronization apparatus 700 includes an obtaining module 701 and a processing module 702. The acquisition module 701 acquires GPS time information and Beidou time information, and inputs the GPS time information and the Beidou time information to the ARM main control processor so as to generate local clock time information through DA circuit conversion and oscillator adjustment. The processing module 702 inputs the GPS time information, the beidou time information, and the local clock time information to the FPGA to query the time information stored by the timing circuit, and determines whether there are multiple pieces of valid GPS time information or multiple pieces of beidou time information within a preset time period from the current time, if so, the input GPS time information or the beidou time information is output as a clock source, otherwise, the input local clock time information is output as a clock source.
In some embodiments, the GPS time information includes a GPS second pulse signal and GPS serial port time data, and the beidou time information includes a beidou second pulse signal and beidou serial port time data;
the processing module 702 is further configured to query the timing circuit to determine that a plurality of valid GPS serial port time data or a plurality of valid beidou serial port time data exist within a preset time period from the current time according to the GPS serial port time data or the beidou serial port time data, and output the GPS second pulse signal or the beidou second pulse signal as a clock source.
In some embodiments, the local clock time information includes a local clock-second pulse signal and a local clock universal time code;
the processing module 702 is further configured to determine that there are no multiple valid GPS time information or multiple valid beidou time information within a preset time period from the current time, output a local clock-second pulse signal, and output a local clock universal time code after processing by a decoding and encoding circuit in the FPGA.
In some embodiments, the obtaining module 701 inputs to an ARM master processor, including:
the method comprises the steps that received GPS serial port time data or Beidou serial port time data are obtained through a UART interface of an ARM main control processor, and GPS second pulse signals or Beidou second pulse signals are obtained through an input capture pin of the ARM main control processor; the GPS time information comprises a GPS second pulse signal and GPS serial port time data, and the Beidou time information comprises a Beidou second pulse signal and Beidou serial port time data.
In some embodiments, after the obtaining module 701 generates the local clock time information, the obtaining module includes:
outputting a local clock second pulse signal through a matching output pin of the ARM main control processor, and outputting a local clock universal time code through a serial peripheral interface of the ARM main control processor; the local clock time information comprises a local clock second pulse signal and a local clock universal time code.
In some embodiments, the obtaining module 701 converts through DA circuitry and generates local clock time information via oscillator adjustment, including:
reading current GPS time information, judging whether an effective mark exists in the current GPS time information, and if so, calculating to obtain local clock time information according to the GPS time information in a preset time period including the current GPS time information; if not, reading current Beidou time information, judging whether an effective identifier exists in the current Beidou time information, and if so, calculating according to the Beidou time information in a preset time period including the current Beidou time information to obtain local clock time information; if not, calling a preset estimation model to obtain estimated Beidou time information, and further calculating according to the Beidou time information in a preset time period including the estimated Beidou time information to obtain local clock time information;
calculating a crystal oscillator error according to the local clock time information, judging whether the crystal oscillator error is larger than a preset error threshold value, if so, adjusting the numerical value of a DA circuit to obtain an output voltage, and adjusting the output frequency of an oscillator according to the output voltage to generate final local clock time information; and if not, taking the local clock time information as final local clock time information.
In some embodiments, the obtaining module 701 is further configured to:
inserting the current GPS time information into a preset GPS time information queue to obtain local clock time information by calculating the mean value of the GPS time information in a preset time period; or
Inserting the current Beidou time information into a preset Beidou time information queue to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period; or
And inserting the estimated Beidou time information into a preset Beidou time information queue so as to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period.
It should be noted that the clock synchronization method and the clock synchronization apparatus of the present invention have corresponding relation in specific implementation content, and therefore repeated content is not described again.
Fig. 8 shows an exemplary device architecture 800 to which the clock synchronization method or clock synchronization device of embodiments of the invention may be applied.
As shown in fig. 8, the apparatus architecture 800 may include terminal devices 801, 802, 803, a network 804 and a server 805. The network 804 serves to provide a medium for communication links between the terminal devices 801, 802, 803 and the server 805. Network 804 may include various types of connections, examples of which are wired, wireless communication links, or fiber optic cables, among others.
A user may use the terminal devices 801, 802, 803 to interact with a server 805 over a network 804 to receive or send messages or the like. The end devices 801, 802, 803 may have installed thereon various communication client applications, such as, for example, shopping applications, web browser applications, search applications, instant messaging tools, mailbox clients, social platform software, and the like (by way of example only).
The terminal devices 801, 802, 803 may be various electronic devices having a clock synchronization screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, desktop computers, and the like.
The server 805 may be a server that provides various services, an example background management server (for example only) that supports shopping-like websites browsed by users using the terminal devices 801, 802, 803. The background management server may analyze and perform other processing on the received data such as the product information query request, and feed back a processing result (the example target push information and the product information — only the example) to the terminal device.
It should be noted that the clock synchronization method provided by the embodiment of the present invention is generally executed by the server 805, and accordingly, the computing device is generally disposed in the server 805.
It should be understood that the number of terminal devices, networks, and servers in fig. 8 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.
Referring now to fig. 9, there is shown a schematic block diagram of a computer apparatus 900 suitable for use in implementing a terminal device of an embodiment of the invention. The terminal device shown in fig. 9 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present invention.
As shown in fig. 9, the computer apparatus 900 includes a Central Processing Unit (CPU)901 that can perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)902 or a program loaded from a storage section 908 into a Random Access Memory (RAM) 903. In the RAM903, various programs and data necessary for the operation of the computer device 900 are also stored. The CPU901, ROM902, and RAM903 are connected to each other via a bus 904. An input/output (I/O) interface 905 is also connected to bus 904.
The following components are connected to the I/O interface 905: an input portion 906 including a keyboard, a mouse, and the like; an output section 907 including components such as a Cathode Ray Tube (CRT), a liquid crystal clock synchronizer (LCD), and the like, and a speaker; a storage portion 908 including a hard disk and the like; and a communication section 909 including a network interface card such as a LAN card, a modem, or the like. The communication section 909 performs communication processing via a network such as the internet. The drive 910 is also connected to the I/O interface 905 as necessary. A removable medium 911 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 910 as necessary, so that a computer program read out therefrom is mounted into the storage section 908 as necessary.
In particular, according to the embodiments of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. The disclosed embodiments of the invention include, by way of example, a computer program product comprising a computer program embodied on a computer readable medium, the computer program containing program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 909, and/or installed from the removable medium 911. The above-described functions defined in the apparatus of the present invention are executed when the computer program is executed by a Central Processing Unit (CPU) 901.
It should be noted that the computer readable medium shown in the present invention can be a computer readable signal medium or a computer readable storage medium or any combination of the two. Examples of a computer readable storage medium may be, but are not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor device, apparatus, or a combination of any of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present invention, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution apparatus, device, or apparatus. In the present invention, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution apparatus, device, or apparatus. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. As an example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based apparatus that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules described in the embodiments of the present invention may be implemented by software or hardware. The described modules may also be provided in a processor, which may be described, for example, as: a processor includes an acquisition module and a processing module. Wherein the names of the modules do not in some cases constitute a limitation of the module itself.
As another aspect, the present invention also provides a computer-readable medium that may be contained in the apparatus described in the above embodiments; or may be separate and not incorporated into the device. The computer readable medium carries one or more programs, when the one or more programs are executed by the device, the device comprises a main control processor for acquiring GPS time information and Beidou time information, inputting the GPS time information and the Beidou time information into the ARM main control processor, and generating local clock time information through DA circuit conversion and oscillator adjustment; the GPS time information, the Beidou time information and the local clock time information are input into the FPGA to inquire the time information stored by the sequential circuit, whether a plurality of pieces of valid GPS time information or a plurality of pieces of valid Beidou time information exist in a preset time period from the current time is judged, if yes, the input GPS time information or the Beidou time information is output as a clock source, and if not, the input local clock time information is output as a clock source.
According to the technical scheme of the embodiment of the invention, the embodiment of the invention can solve the problems of limited application, high cost and poor reliability of the conventional clock source.
The above-described embodiments should not be construed as limiting the scope of the invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions can occur, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of clock synchronization, comprising:
acquiring GPS time information and Beidou time information, inputting the GPS time information and the Beidou time information into an ARM main control processor, converting the GPS time information and the Beidou time information through a DA circuit, and adjusting the GPS time information and the ARM main control processor through an oscillator to generate local clock time information;
the GPS time information, the Beidou time information and the local clock time information are input into the FPGA to inquire the time information stored by the sequential circuit, whether a plurality of pieces of valid GPS time information or a plurality of pieces of valid Beidou time information exist in a preset time period from the current time is judged, if yes, the input GPS time information or the Beidou time information is output as a clock source, and if not, the input local clock time information is output as a clock source.
2. The method of claim 1, comprising:
the GPS time information comprises a GPS second pulse signal and GPS serial port time data, and the Beidou time information comprises a Beidou second pulse signal and Beidou serial port time data;
according to the GPS serial port time data or the Beidou serial port time data, the inquiry time sequence circuit determines that a plurality of effective GPS serial port time data or a plurality of effective Beidou serial port time data exist in a preset time period away from the current time, and then the GPS second pulse signal or the Beidou second pulse signal is output as a clock source.
3. The method of claim 1, comprising:
the local clock time information comprises a local clock second pulse signal and a local clock universal time code;
and if the plurality of effective GPS time information or the plurality of effective Beidou time information do not exist within the preset time period from the current time, outputting a local clock second pulse signal, and outputting the local clock universal time code after the local clock universal time code is processed by a decoding and encoding circuit in the FPGA.
4. The method of claim 1, wherein inputting to an ARM master processor comprises:
the method comprises the steps that received GPS serial port time data or Beidou serial port time data are obtained through a UART interface of an ARM main control processor, and GPS second pulse signals or Beidou second pulse signals are obtained through an input capture pin of the ARM main control processor; the GPS time information comprises a GPS second pulse signal and GPS serial port time data, and the Beidou time information comprises a Beidou second pulse signal and Beidou serial port time data.
5. The method of claim 1, wherein generating local clock time information comprises:
outputting a local clock second pulse signal through a matching output pin of the ARM main control processor, and outputting a local clock universal time code through a serial peripheral interface of the ARM main control processor; the local clock time information comprises a local clock second pulse signal and a local clock universal time code.
6. The method of claim 1, wherein generating local clock time information by DA circuit conversion and oscillator adjustment comprises:
reading current GPS time information, judging whether an effective mark exists in the current GPS time information, and if so, calculating to obtain local clock time information according to the GPS time information in a preset time period including the current GPS time information; if not, reading current Beidou time information, judging whether an effective identifier exists in the current Beidou time information, and if so, calculating according to the Beidou time information in a preset time period including the current Beidou time information to obtain local clock time information; if not, calling a preset estimation model to obtain estimated Beidou time information, and further calculating according to the Beidou time information in a preset time period including the estimated Beidou time information to obtain local clock time information;
calculating a crystal oscillator error according to the local clock time information, judging whether the crystal oscillator error is larger than a preset error threshold value, if so, adjusting the numerical value of a DA circuit to obtain an output voltage, and adjusting the output frequency of an oscillator according to the output voltage to generate final local clock time information; and if not, taking the local clock time information as final local clock time information.
7. The method of claim 6, further comprising:
inserting the current GPS time information into a preset GPS time information queue to obtain local clock time information by calculating the mean value of the GPS time information in a preset time period; or
Inserting the current Beidou time information into a preset Beidou time information queue to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period; or
And inserting the estimated Beidou time information into a preset Beidou time information queue so as to obtain local clock time information by calculating the mean value of the Beidou time information in a preset time period.
8. A clock synchronization apparatus, comprising:
the acquisition module is used for acquiring GPS time information and Beidou time information, inputting the GPS time information and the Beidou time information into the ARM main control processor, and generating local clock time information through DA circuit conversion and oscillator adjustment;
and the processing module is used for inputting the GPS time information, the Beidou time information and the local clock time information into the FPGA to inquire the time information stored by the sequential circuit, judging whether a plurality of pieces of valid GPS time information or a plurality of pieces of valid Beidou time information exist in a preset time period away from the current time, outputting the input GPS time information or the Beidou time information as a clock source if the time information is valid, and outputting the input local clock time information as the clock source if the time information is not valid.
9. An electronic device, comprising:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1-7.
10. A computer-readable medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1-7.
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