CN115642978A

CN115642978A - System clock synchronization method, device, equipment and storage medium

Info

Publication number: CN115642978A
Application number: CN202211260952.8A
Authority: CN
Inventors: 卢笔伦; 汪顺利; 马思遥; 袁士琳; 吴玲玲
Original assignee: Shanghai Aircraft Manufacturing Co Ltd
Current assignee: Shangfei Intelligent Technology Co ltd
Priority date: 2022-10-14
Filing date: 2022-10-14
Publication date: 2023-01-24

Abstract

The invention discloses a system clock synchronization method, a system clock synchronization device, system clock synchronization equipment and a storage medium. The method comprises the following steps: acquiring a B-type serial time code IRIG-B analog signal sent by a 5G module; analyzing the IRIG-B analog signal by an auxiliary core to generate a time value; and time adjustment is carried out on the system clock through the main core according to the time value so as to realize time synchronization of the system on chip and the 5G module. The auxiliary core receives and analyzes the B-type serial time code sent by the 5G module, other hardware circuits are not needed for function assistance, resources are saved, codes executed in the auxiliary core are relatively single, so that the analysis mode completely completed by the auxiliary core is slightly interfered by the external environment and actual operation services, and the main core adjusts the time of the system clock according to the time value, so that the time synchronization of the system on chip and the 5G module is realized, the time precision is improved, the resources of the main core are saved, and the reliability of the system on chip is improved.

Description

System clock synchronization method, device, equipment and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a storage medium for synchronizing a system clock.

Background

At present, 5G network technology is gradually maturing, and its corresponding protocol standards and technologies are continuously developing and perfecting. The characteristics of large bandwidth, high reliability and low delay are favored by the industry. The time service signals in the 5G network make high-precision clock synchronization of the Internet of things equipment possible.

In the prior art, a scheme for a system on chip to time through a B-type serial time code is that a main core is adopted to directly obtain a time value from a communication module, an auxiliary core filters pulse per second, and finally a B-code time-setting signal is output.

In the prior art, the output time precision is low due to the combination of the pulse per second and the time information, and the workload of the master core is increased by acquiring the time value from the communication module through the master core, so that the system is overloaded.

Disclosure of Invention

The invention provides a system clock synchronization method, a device, equipment and a storage medium, which are used for realizing the time synchronization of a system on chip and a 5G module.

According to an aspect of the present invention, there is provided a system clock synchronization method, including:

acquiring a B-type serial time code IRIG-B analog signal sent by a 5G module;

analyzing the IRIG-B analog signal by an auxiliary core to generate a time value;

and the time of the system clock is adjusted by the main core according to the time value so as to realize the time synchronization of the system on chip and the 5G module.

Preferably, the acquiring the B-type serial time code IRIG-B analog signal sent by the 5G module includes: sending a connection request to a 5G module by a main core through a specified communication protocol so that the 5G module generates an IRIG-B analog signal according to the connection request, wherein the specified communication protocol comprises a Universal Serial Bus (USB) protocol and a high-speed serial computer expansion bus standard Peripheral Component Interface Express (PCIE) protocol; and receiving an IRIG-B analog signal sent by the 5G module through an input/output port through the auxiliary core.

Preferably, the analyzing the IRIG-B analog signal by the auxiliary core to generate the time value includes: analyzing the IRIG-B analog signal through the auxiliary core to obtain a rising edge and a falling edge of the IRIG-B analog signal; calculating a difference value of a rising edge and a falling edge, and taking the difference value as a pulse width of an IRIG-B analog signal, wherein the pulse width comprises a specific time bit and a parity bit; and taking a first numerical value corresponding to the specific time bit as a time value.

Preferably, before the first value corresponding to the specific time bit is taken as the time value, the method further includes: acquiring a second numerical value corresponding to the parity check bit; performing parity check on the IRIG-B analog signal according to the second numerical value to obtain a check result; and determining that the checking result is normal.

Preferably, after analyzing the IRIG-B analog signal by the auxiliary core to generate the time value, the method further includes: storing the time value into a specified shared memory address, and triggering to generate an interrupt signal according to the time value; an interrupt signal is sent to the primary core.

Preferably, the time adjustment of the system clock by the master core according to the time value includes: determining that the time value stored in the appointed shared memory address is read through the main core when the main core receives the interrupt signal; and writing the time value into the system clock to realize the time adjustment of the system clock.

Preferably, after the time adjustment is performed on the system clock according to the time value by the master core, the method further includes: acquiring an adjusted system clock; when the adjusted system clock is determined to be inconsistent with the time value, generating a time synchronization abnormal signal; and prompting according to the time synchronization abnormal signal.

According to another aspect of the present invention, there is provided a system clock synchronizing apparatus, including:

the analog signal acquisition module is used for acquiring a B-type serial time code IRIG-B analog signal sent by the 5G module;

the time value generating module is used for analyzing the IRIG-B analog signal through the auxiliary core to generate a time value;

and the time synchronization module is used for adjusting the time of the system clock through the main core according to the time value so as to realize the time synchronization of the system on chip and the 5G module.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,

the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform a system clock synchronization method according to any of the embodiments of the invention.

According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement a system clock synchronization method according to any one of the embodiments of the present invention when the computer instructions are executed.

According to the technical scheme of the embodiment of the invention, the auxiliary core receives and analyzes the B-type serial time code sent by the 5G module, no other hardware circuit is needed for function assistance, resources are saved, and the code executed in the auxiliary core is relatively single, so that the analysis is completely completed by the auxiliary core, the interference of the external environment and the actual operation service is small, and the main core performs time adjustment on the system clock according to the time value, so that the time synchronization of the system on chip and the 5G module is realized, the time precision is improved, the resources of the main core are also saved, and the reliability of the system on chip is improved.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a system clock synchronization method according to an embodiment of the present invention;

FIG. 2 is a flow chart of another method for synchronizing system clocks according to an embodiment of the present invention;

FIG. 3 is a flowchart of another system clock synchronization method according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a system clock synchronization apparatus according to a third embodiment of the present invention;

fig. 5 is a schematic structural diagram of an electronic device implementing the system clock synchronization method according to the embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example one

Fig. 1 is a flowchart of a system clock synchronization method according to an embodiment of the present invention, where the embodiment is applicable to a case where a system on chip performs time synchronization with a 5G module, and the method may be performed by a system clock synchronization apparatus, where the system clock synchronization apparatus may be implemented in a form of hardware and/or software, and the system clock synchronization apparatus may be configured in the system on chip. As shown in fig. 1, the method includes:

and S110, acquiring a B-type serial time code IRIG-B analog signal sent by the 5G module.

Among them, the fifth Generation Mobile Communication technology (5 th Generation Mobile Communication technology,5 g) is a new Generation broadband Mobile Communication technology with high speed, low latency and large connection characteristics, and is a network infrastructure for realizing man-machine interconnection. The System on Chip (SoC) can receive the B-type serial time code sent by the 5G module, and the SoC is a Chip of an integrated circuit, so that the development cost of electronic information System products can be effectively reduced; from a narrow sense, the SoC is the chip integration of the information system core, and is to integrate the key components of the system on one chip; in a broad sense, soC is a micro-miniature system, and if a Central Processing Unit (CPU) is a brain, soC is a system including the brain, the heart, the eyes, and the hands; the academic circles at home and abroad generally tend to define SoC as integrating a microprocessor, an analog Internet Protocol (IP) core, a digital IP core and a memory on a single chip. Type B Serial time code (IRIG-B) is a format of time code, which is a one frame per second time code.

Preferably, the acquiring the type B serial time code IRIG-B analog signal sent by the 5G module includes: sending a connection request to a 5G module by a main core by adopting a specified communication protocol so that the 5G module generates an IRIG-B analog signal according to the connection request, wherein the specified communication protocol comprises a Universal Serial Bus (USB) protocol and a high-speed serial computer expansion bus standard (PCIE) protocol; and receiving an IRIG-B analog signal sent by the 5G module through an input/output port through the auxiliary core.

The SoC comprises a main core, an auxiliary core and a system clock, wherein the main core mainly operates a communication function between the SoC and a host machine and a drive of system resources in the SoC, the host machine is a computer host machine which is connected with the SoC, the auxiliary core receives allocation of the main core, the main core uniformly receives an excitation instruction transmitted by the host machine and responds to the host machine by generating a response instruction from the operation of the auxiliary core through the operation and/or the allocation of the main core, namely the main core bears the main work of the SoC.

Specifically, the SoC sends a connection request to the 5G module through the main core by using a specified communication protocol, where the specified communication protocol includes a Universal Serial Bus (USB) protocol and a high-speed Serial computer extended Bus (PCIE) protocol, where the USB protocol is an external Bus standard and is also a technical specification of an input/output interface, and is widely applied to information communication products such as a personal computer and a mobile device, and the PCIE protocol belongs to high-speed Serial point-to-point dual-channel high-bandwidth transmission, and a connected device allocates an independent channel bandwidth and does not share a Bus bandwidth. After receiving the connection request, the 5G module generates an IRIG-B analog signal according to the connection request, the 5G module sends the IRIG-B analog signal to the auxiliary core, the auxiliary core dials to be connected to the network after being configured through a specified communication protocol, the 5G module outputs the IRIG-B analog signal on a function pin after being dialed to be connected to the network, and the SoC auxiliary core enables the on-chip function pin.

And S120, analyzing the IRIG-B analog signal through the auxiliary core to generate a time value.

Fig. 2 is a flowchart of a system clock synchronization method according to an embodiment of the present invention, where the step S120 mainly includes the following steps S121 to S123:

and S121, analyzing the IRIG-B analog signal through the auxiliary core to obtain a rising edge and a falling edge of the IRIG-B analog signal.

Specifically, after receiving the IRIG-B analog signal, the SoC auxiliary core analyzes the IRIG-B analog signal to obtain a rising edge and a falling edge of the IRIG-B analog signal, where the rising edge is an instantaneous signal at the moment of switching on, and is equivalent to a power-on signal; the falling edge is a transient signal at the moment of disconnection, and corresponds to a power-off signal.

And S122, calculating the difference value of the rising edge and the falling edge, and taking the difference value as the pulse width of the IRIG-B analog signal, wherein the pulse width comprises a specific time bit and a parity bit.

Specifically, the pulse width refers to a pulse width, that is, a duration of a high level, the SoC calculates a difference between a rising edge and a falling edge, and uses the difference as the pulse width of the IRIG-B analog signal, and since a process of obtaining the pulse width according to the rising edge and the falling edge is a prior art means, details are not repeated in this embodiment, where the pulse width includes a specific time bit and a parity bit, the specific time bit is located in a first half section of the pulse width and includes a specific time value, and the parity bit is used for performing parity check on the IRIG-B analog signal.

Parity check is generally used in data communication to ensure validity of data, and is mostly applied to error detection of computer hardware; a parity bit is a binary number indicating whether the number of 1's in a given number of bits is odd or even, and there are two types of parity bits: an even check bit and an odd check bit; if the number of 1's in a given set of data bits is odd, then the even parity bits are 1's, so that the total number of 1's is even. If the number of 1's in a given set of data bits is even, then the odd parity bits are 1's, so that the total number of 1's is odd.

Further, the SoC auxiliary core may obtain a second numerical value corresponding to the parity check bit, and perform parity check on the IRIG-B analog signal according to the second numerical value, when it is determined that the check result is normal, the SoC auxiliary core may extract a time value therein, and if the check result is abnormal, it indicates that an odd number of data bits including the parity check bit in the signal transmission process are changed, the parity check bit may also be in error, and at this time, the SoC auxiliary core may re-receive the IRIG-B analog signal sent by the 5G module to perform analysis, and does not perform subsequent processing on the current IRIG-B analog signal.

And S123, taking the first numerical value corresponding to the specific time bit as a time value.

Specifically, when the parity check result is determined to be normal, the SoC auxiliary core may use a first value corresponding to the specific time bit, where the first value is a specific time value, and the SoC auxiliary core may use the first value as a time value.

Preferably, after the generating the time value by analyzing the IRIG-B analog signal with the auxiliary core, the method further includes: storing the time value into a specified shared memory address, and triggering to generate an interrupt signal according to the time value; an interrupt signal is sent to the primary core.

Specifically, after the SoC auxiliary core analyzes the IRIG-B analog signal to generate a time value, the time value is stored into a specified shared memory address, wherein the specified shared memory address refers to a memory address that can be accessed by both the SoC main core and the auxiliary core, a user can set the time value in advance according to needs, the time value is mainly used for storing information such as a time value and a relevant mark in a clock synchronization process, and the user refers to a technician or a worker who performs system clock synchronization; and the SoC auxiliary core can trigger and generate an interrupt signal according to the time value and send the interrupt signal to the SoC main core.

And S130, adjusting the time of the system clock through the main core according to the time value so as to realize the time synchronization of the system on chip and the 5G module.

The time synchronization provides a uniform time scale for the distributed system, and all events of each system have the uniform time scale under the condition of the uniform time scale. For example, an unmanned aerial vehicle, a radar, other communication network devices, and the like have high requirements on time synchronization, taking the unmanned aerial vehicle as an example, at present, the clock design of each subsystem such as unmanned aerial vehicle flight control, sensing, image transmission, and the like generally uses respective local crystal oscillators as clock sources for each subsystem, and as small differences exist in frequency offset, clock jitter, and the like of different crystal oscillators, larger and larger deviations exist in accumulated local time of each subsystem as time goes on; to eliminate the skew, the system clocks of the subsystems need to be adjusted in time each time.

Specifically, after receiving the interrupt signal sent by the SoC auxiliary core, the SoC main core reads the time value stored in the specified shared memory address, and writes the time value into the system clock, so as to implement time adjustment of the system clock. Different from other schemes, the present embodiment adopts the auxiliary core of SoC to independently complete all tasks of receiving and analyzing the IRIG-B analog signal, and does not need other external counter circuits or Field Programmable Gate Array (FPGA) to implement, and does not need to consume computing power and time of the main core, thereby avoiding random errors caused by floating of the IRIG-B analog signal analysis speed due to actual operation service in the main core; the real-time performance of IRIG-B analog signal analysis is guaranteed, the design complexity of related circuits is reduced, and the reliability of the whole system is improved. The auxiliary core has a single task, the program for executing analysis is fixed, and the system error can be eliminated through calculation compensation, so that the accuracy of system time synchronization is ensured; compared with other time synchronization schemes, the method does not need to finish system time synchronization with higher precision by other external equipment, does not occupy computing resources of the main core to analyze the IRIG-B analog signal, reduces time synchronization precision errors caused by communication between equipment, improves time service accuracy and reduces interference of specific system services to time service precision.

Example two

Fig. 3 is a flowchart of a system clock synchronization method according to a second embodiment of the present invention, where a process of generating and prompting a time synchronization exception signal is added to the first embodiment of the present invention. The specific contents of steps S210-S230 are substantially the same as steps S110 to S130 in the first embodiment, and therefore are not described in detail in this embodiment. As shown in fig. 3, the method includes:

s210, acquiring a B-type serial time code IRIG-B analog signal sent by the 5G module.

Preferably, the acquiring the type B serial time code IRIG-B analog signal sent by the 5G module includes: sending a connection request to a 5G module by a main core through a specified communication protocol so that the 5G module generates an IRIG-B analog signal according to the connection request, wherein the specified communication protocol comprises a Universal Serial Bus (USB) protocol and a high-speed serial computer expansion bus standard Peripheral Component Interface Express (PCIE) protocol; and receiving IRIG-B analog signals sent by the 5G module through the input/output port through the auxiliary core.

And S220, analyzing the IRIG-B analog signal through the auxiliary core to generate a time value.

Preferably, the analyzing the IRIG-B analog signal by the auxiliary core to generate the time value includes: analyzing the IRIG-B analog signal through the auxiliary core to obtain a rising edge and a falling edge of the IRIG-B analog signal; calculating a difference value of a rising edge and a falling edge, and taking the difference value as a pulse width of an IRIG-B analog signal, wherein the pulse width comprises a specific time bit and a parity bit; and taking the first numerical value corresponding to the specific time bit as a time value.

And S230, performing time adjustment on the system clock through the main core according to the time value so as to realize time synchronization of the system on chip and the 5G module.

And S240, acquiring the adjusted system clock.

Specifically, after the SoC completes the time adjustment of the system clock, it may further determine whether the time adjustment is correct, and the purpose of determining the time adjustment is to ensure the accuracy of the time adjustment performed by the SoC on the system clock, and meanwhile, it may also be discovered in time when the adjustment is abnormal, and when it is determined whether the time adjustment is correct, the SoC may obtain the adjusted system clock.

And S250, when the adjusted system clock is determined to be inconsistent with the time value, generating a time synchronization abnormal signal.

Specifically, after the SoC acquires the adjusted system clock, it is determined whether the adjusted system clock is consistent with the time value, if so, it is verified that the adjusted system clock is correct, and when it is determined that the adjusted system clock is inconsistent with the time value, it is indicated that the adjustment process is abnormal, and at this time, the SoC generates a time synchronization abnormal signal.

And S260, prompting according to the time synchronization abnormal signal.

Specifically, the SoC may prompt according to the time synchronization abnormal signal, and the time synchronization abnormal prompt may be performed through a terminal connected to the SoC in a prompting manner, for example, the user may view the time synchronization abnormal prompt at the terminal, and the prompting content is as follows: the time synchronization is abnormal. The time synchronization abnormity prompting is carried out for the purpose that a user can timely master the abnormal condition of the time synchronization of the system clock, so that the user can conveniently check and process the time synchronization abnormity in time, and the accuracy of the time synchronization is further improved.

According to the technical scheme of the embodiment of the invention, the auxiliary core receives and analyzes the B-type serial time code sent by the 5G module, no other hardware circuit is needed for function assistance, resources are saved, and the code executed in the auxiliary core is relatively single, so that the analysis is completely completed by the auxiliary core and is slightly interfered by the external environment and the actual operation service, and the main core performs time adjustment on the system clock according to the time value to realize the time synchronization of the system on chip and the 5G module, so that the time precision is improved, the resources of the main core are saved, the reliability of the system on chip is improved, and when the adjusted system clock is determined to be inconsistent with the time value, a time synchronization abnormal signal is generated and prompted, a user can timely master the abnormal condition of the time synchronization of the system clock, the user can conveniently check and process in time, and the accuracy of the time synchronization is further improved.

EXAMPLE III

Fig. 4 is a schematic structural diagram of a system clock synchronization apparatus according to a third embodiment of the present invention. As shown in fig. 4, the apparatus includes: the analog signal acquisition module 310 is configured to acquire a B-type serial time code IRIG-B analog signal sent by the 5G module; the time value generating module 320 is configured to analyze the IRIG-B analog signal through the auxiliary core to generate a time value; and the time synchronization module 330 is configured to perform time adjustment on the system clock according to the time value through the master core, so as to implement time synchronization between the system on chip and the 5G module.

Preferably, the analog signal obtaining module 310 is specifically configured to: sending a connection request to the 5G module through the main core so that the 5G module generates an IRIG-B analog signal according to the connection request; and receiving IRIG-B analog signals sent by the 5G module through a specified communication protocol through the auxiliary core, wherein the specified communication protocol comprises a Universal Serial Bus (USB) protocol and a high-speed serial computer expansion bus standard Peripheral Component Interface Express (PCIE) protocol.

Preferably, the time value generating module 320 specifically includes: the analog signal analysis unit is used for analyzing the IRIG-B analog signal through the auxiliary core to obtain a rising edge and a falling edge of the IRIG-B analog signal; the analog signal pulse width acquisition unit is used for calculating a difference value of a rising edge and a falling edge and taking the difference value as the pulse width of the IRIG-B analog signal, wherein the pulse width comprises a specific time bit and a parity bit; and the time value acquisition subunit is used for taking the first numerical value corresponding to the specific time bit as the time value.

Preferably, the time value generating module 320 further includes: a parity check unit for acquiring a second value corresponding to a parity check bit; performing parity check on the IRIG-B analog signal according to the second numerical value to obtain a check result; and determining that the checking result is normal.

Preferably, the apparatus further comprises: the interrupt signal generation module is used for storing the time value into the appointed shared memory address and triggering and generating an interrupt signal according to the time value; an interrupt signal is sent to the primary core.

Preferably, the time synchronization module 330 is specifically configured to: determining that the time value stored in the appointed shared memory address is read through the main core when the main core receives the interrupt signal; and writing the time value into the system clock to realize the time adjustment of the system clock.

Preferably, the apparatus further comprises: the time synchronization abnormity prompting module is used for acquiring the adjusted system clock; when the adjusted system clock is determined to be inconsistent with the time value, generating a time synchronization abnormal signal; and prompting according to the time synchronization abnormal signal.

The system clock synchronization device provided by the embodiment of the invention can execute the system clock synchronization method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.

Example four

FIG. 5 illustrates a schematic diagram of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 5, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from a storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. Processor 11 performs the various methods and processes described above, such as a system clock synchronization method.

In some embodiments, a system clock synchronization method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When loaded into RAM 13 and executed by processor 11, the computer program may perform one or more of the steps of a system clock synchronization method described above. Alternatively, in other embodiments, the processor 11 may be configured to perform a system clock synchronization method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user may provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.

It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A system clock synchronization method is applied to a system on chip, wherein the system on chip comprises a main core, an auxiliary core and a system clock, and the method comprises the following steps:

acquiring a B-type serial time code IRIG-B analog signal sent by a 5G module;

analyzing the IRIG-B analog signal through the auxiliary core to generate a time value;

and performing time adjustment on the system clock through the main core according to the time value so as to realize time synchronization of the system on chip and the 5G module.

2. The method according to claim 1, wherein the acquiring the type B serial time code IRIG-B analog signal sent by the 5G module comprises:

sending a connection request to the 5G module by the main core by adopting a specified communication protocol so that the 5G module generates the IRIG-B analog signal according to the connection request, wherein the specified communication protocol comprises a Universal Serial Bus (USB) protocol and a high-speed serial computer expansion bus standard (PCIE) protocol;

and receiving the IRIG-B analog signal sent by the 5G module through an input/output port through the auxiliary core.

3. The method according to claim 1, wherein said parsing said IRIG-B analog signal by said auxiliary core to generate a time value comprises:

analyzing the IRIG-B analog signal through the auxiliary core to obtain a rising edge and a falling edge of the IRIG-B analog signal;

calculating a difference value of the rising edge and the falling edge, and taking the difference value as a pulse width of the IRIG-B analog signal, wherein the pulse width comprises a specific time bit and a parity bit;

and taking a first numerical value corresponding to the specific time bit as the time value.

4. The method of claim 3, wherein said prior to said determining the first value corresponding to said specific time bit as said time value, further comprising:

acquiring a second numerical value corresponding to the parity check bit;

performing parity check on the IRIG-B analog signal according to the second numerical value to obtain a check result;

and determining that the checking result is normal.

5. The method according to claim 3, wherein after the parsing the IRIG-B analog signal by the auxiliary core to generate a time value, further comprising:

storing the time value into a specified shared memory address, and triggering and generating an interrupt signal according to the time value;

and sending the interrupt signal to the main core.

6. The method of claim 5, wherein the time adjusting, by the master core, the system clock according to the time value comprises:

determining that the time value stored in the specified shared memory address is read by the master core when the master core receives the interrupt signal;

and writing the time value into the system clock to realize the time adjustment of the system clock.

7. The method of claim 4, wherein after the time adjusting the system clock according to the time value by the master core, further comprising:

acquiring an adjusted system clock;

when the adjusted system clock is determined to be inconsistent with the time value, generating a time synchronization abnormal signal;

and prompting according to the time synchronization abnormal signal.

8. A system clock synchronization apparatus, comprising:

9. An electronic device, characterized in that the electronic device comprises:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A computer storage medium, characterized in that the computer-readable storage medium stores computer instructions for causing a processor, when executed, to implement the method of any one of claims 1-7.