CN114257717B

CN114257717B - Electronic equipment

Info

Publication number: CN114257717B
Application number: CN202011027493.XA
Authority: CN
Inventors: 陈朝喜
Original assignee: Beijing Xiaomi Mobile Software Co Ltd
Current assignee: Beijing Xiaomi Mobile Software Co Ltd
Priority date: 2020-09-25
Filing date: 2020-09-25
Publication date: 2024-05-31
Anticipated expiration: 2040-09-25
Also published as: CN114257717A

Abstract

The present disclosure relates to an electronic device comprising a spatial attitude sensor, a processor, a microprocessor, and a camera module; the space attitude sensor comprises a first SPI interface and a second SPI interface; the camera module comprises at least two OIS controllers; the processor is connected with the space attitude sensor through the first SPI interface; the microprocessor is connected with the space attitude sensor through the second SPI interface; the microprocessor is used for transmitting the spatial attitude data acquired from the second SPI interface to the at least two OIS controllers. In this embodiment, the spatial attitude data may be transmitted to the OIS controllers without adding an SPI interface to the spatial attitude sensor, so as to implement a multi-OIS anti-shake function, which is beneficial to optimizing the shooting effect of the electronic device.

Description

Electronic equipment

Technical Field

The disclosure relates to the field of control technologies, and in particular, to an electronic device.

Background

Currently, most of camera modules of electronic devices are provided with an optical anti-shake function (OIS), and an OIS controller in the camera adjusts lens parameters by acquiring spatial pose data of the electronic device, so as to acquire high-quality video and images.

In practical application, the above spatial gesture data come from the acceleration sensor and the gyroscope sensor, and as the sensors share two paths of serial peripheral interfaces (SERIAL PERIPHERAL INTERFACE, SPI), one path provides spatial gesture data for a processor of the electronic device, and the other path provides spatial gesture data for one OIS controller. As the number of lenses in the camera module increases, the number of OIS controllers increases, and at this time, the SPI interface of the sensor cannot meet the requirement of providing spatial gesture data for a plurality of OIS controllers.

Disclosure of Invention

The present disclosure provides an electronic device to solve the deficiencies of the related art.

According to a first aspect of embodiments of the present disclosure, there is provided an electronic device comprising a spatial attitude sensor, a processor, a microprocessor, and a camera module; the space attitude sensor comprises a first SPI interface and a second SPI interface; the camera module comprises at least two OIS controllers; the processor is connected with the space attitude sensor through the first SPI interface; the microprocessor is connected with the space attitude sensor through the second SPI interface;

the microprocessor is used for transmitting the spatial attitude data acquired from the second SPI interface to the at least two OIS controllers.

Optionally, the at least two OIS controllers include a first OIS controller and a second OIS controller; the microprocessor comprises a first SPI bus interface, a second SPI interface and a third SPI interface;

the first SPI interface of the microprocessor is connected with the first OIS controller through an SPI bus;

the second SPI interface of the microprocessor is connected with the second SPI interface of the space attitude sensor through an SPI bus;

and a third SPI interface of the microprocessor is connected with the second OIS controller through an SPI bus.

Optionally, the microprocessor further comprises a first APB bus and a second APB bus;

The first SPI bus interface of the microprocessor is connected with the second APB bus;

And the second SPI bus interface and the third SPI bus interface of the microprocessor are respectively connected with the first APB bus.

Optionally, the priority of the first APB bus is higher than the priority of the second APB bus.

Optionally, the sampling period of the first OIS controller is smaller than the sampling period of the second OIS controller, and the sampling period of the first OIS controller is smaller than the reading period of the microprocessor reading data from the spatial attitude sensor.

Optionally, the microprocessor further comprises an advanced high performance bus, a first APB bridge, and a second APB bridge; the high-level high-performance bus is connected with the first APB bus through the first APB bridge, and the high-level high-performance bus is connected with the second APB bus through the second APB bridge.

Optionally, the microprocessor comprises a first memory common to the at least two OIS controllers, the first memory for storing spatial pose data from the spatial pose sensor and each OIS controller for reading spatial pose data from the first memory.

Optionally, the microprocessor further includes a second memory, where the second memory is configured to buffer the spatial pose data from the spatial pose sensor, and to transfer the spatial pose data to the first memory after the buffered spatial pose data meets a specified length.

Optionally, the microprocessor includes memories in one-to-one correspondence with the OIS controllers, each memory being for storing the spatial pose data from the spatial pose sensor and each OIS controller reading the spatial pose data from the memory corresponding thereto.

The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:

As can be seen from the above embodiments, the electronic device in the embodiments of the present disclosure may include a spatial gesture sensor, a processor, a microprocessor, and a camera module; the space attitude sensor comprises a first SPI interface and a second SPI interface; the camera module comprises at least two OIS controllers; the processor is connected with the space attitude sensor through the first SPI interface; the microprocessor is connected with the space attitude sensor through the second SPI interface; the microprocessor is used for transmitting the spatial attitude data acquired from the second SPI interface to the at least two OIS controllers, namely transmitting the spatial attitude data to the plurality of OIS controllers under the condition that the SPI interface is not added by the spatial attitude sensor, so that the multi-OIS anti-shake function is realized, and the shooting effect of the electronic equipment is optimized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a block diagram of an electronic device, according to an example embodiment.

Fig. 2 is a block diagram of another electronic device, shown in accordance with an exemplary embodiment.

FIG. 3 is a schematic diagram of a microprocessor architecture according to an exemplary embodiment.

Fig. 4 is a block diagram of another electronic device, shown in accordance with an exemplary embodiment.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described by way of example below are not representative of all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus consistent with some aspects of the disclosure as detailed in the accompanying claims.

To solve the above technical problem, an embodiment of the present disclosure provides an electronic device, referring to fig. 1, including a processor 10, a spatial attitude sensor 20, a microprocessor 30, and a camera module 40. The spatial attitude sensor 20 includes a first SPI interface SPI1 and a second SPI interface SPI2. The camera module 40 includes at least two OIS controllers (OIS controller 1, OIS controllers 2, … …, OIS controllers n, n being greater than or equal to 2).

The processor 10 is connected to the spatial attitude sensor 20 through a first SPI interface SPI1, i.e., the processor 10 may acquire spatial attitude data through the first SPI interface SPI 1. Microprocessor 30 is connected to spatial attitude sensor 20 via a second SPI interface SPI 2. Thus, the microprocessor 30 is configured to transmit the spatial attitude data acquired from the second SPI interface SPI2 to the OIS controllers 1 to n.

In this example, the manner in which the microprocessor 30 sends the spatial pose data to the OIS controllers may include:

In one example, a common memory is provided within microprocessor 30, which may store spatial pose data from spatial pose sensor 20. For example, the microprocessor 30 communicates with the spatial attitude sensor 20, and when the microprocessor 30 confirms that the memory can update data, transmits an update request to the spatial attitude sensor 20, and acquires the spatial attitude data transmitted from the spatial attitude sensor 20, and when a preset size is reached, the microprocessor 30 updates the spatial attitude data to the shared memory. The microprocessor 30 may then send a notification message to each OIS controller. After each OIS controller has obtained the notification message, a data request may be sent to the microprocessor 30. The microprocessor 30 may respond to the data request and send the spatial pose data in the memory to the OIS controller corresponding to the data request.

It should be noted that, each time the spatial pose data is updated, the microprocessor 30 may default that all OIS controllers need to transmit data, or may just respond to the OIS controller that transmits a data request. In practice, the microprocessor 30 may also set a period, for example, 1-5 seconds, for each update data, and after the period is exceeded, the microprocessor 30 defaults that all OIS controllers have acquired the spatial gesture data, and at this time, the content of the memory may be updated next time.

In another example, a plurality of memories are provided in the microprocessor 30, wherein the memories are in one-to-one correspondence with OIS controllers, i.e. one memory is provided for each OIS controller. Spatial pose data from the spatial pose sensor 20 may be stored in each memory and sent to the corresponding OIS controller. For example, the microprocessor 30 communicates with the spatial attitude sensor 20, and when the microprocessor 30 confirms that the memory can update data, sends an update request to the spatial attitude sensor 20, and acquires the spatial attitude data sent by the spatial attitude sensor 20, and when a preset size is reached, the microprocessor 30 updates the spatial attitude data to the respective memories, respectively. In this way, the OIS controller may read the spatial pose data directly from within the memory. When the set period is reached, the microprocessor 30 proceeds to next update the spatial pose data for each memory.

In this way, in this embodiment, the microprocessor 30 is configured to send the spatial attitude data of the second SPI interface to the OIS controllers 1-n, that is, one piece of spatial attitude data is divided into multiple pieces of spatial attitude data, so that the spatial attitude data is transmitted to the multiple OIS controllers without adding the SPI interface to the spatial attitude sensor, thereby implementing the multi-OIS anti-shake function, and being beneficial to optimizing the shooting effect of the electronic device.

To ensure reliable operation of the microprocessor, referring to fig. 2, the microprocessor 30 includes a power-up enable terminal Ldo to which the processor 10 is coupled for controlling the powering up or powering down of the microprocessor 30 via the power-up enable terminal Ldo. Thus, the processor 10 may control the microprocessor 30 to power up or power down to stop operation.

With continued reference to FIG. 2, the microprocessor 30 includes a communication bus, such as an I2C bus. The processor 10 may be connected to the microprocessor 30 via a communication bus I2C for updating the firmware of the microprocessor 30 via the communication bus I2C. It should be noted that the communication bus may be configured according to a microprocessor and a processor, which is not limited herein.

With continued reference to FIG. 2, during operation, microprocessor 30 may also send system status to processor 10 via communication bus I2C. The system state includes running, hanging, abnormal state, etc. of the system, and the processor 10 can reset or restart the microprocessor 30, so as to ensure the normal operation of the microprocessor 30.

With continued reference to FIG. 2, the microprocessor 30 includes a URAT interface through which the processor 10 is connected. When an error occurs in the microprocessor 30, the processor 10 may obtain log data within the microprocessor 30 via the URAT interface to locate a problem with the microprocessor 30. After the problem is located, the processor 10 may solve the problem by resetting, restarting, etc., to restore the microprocessor 30 to normal operation.

With continued reference to fig. 2, OIS controllers are coupled to the processor 10 and may send an exception status of the microprocessor 30 to the processor 10 to cause the processor 10 to reset the microprocessor 30.

With continued reference to FIG. 2, microprocessor 30 also includes a reset terminal RST through which processor 10 is coupled to microprocessor 30. When the processor 10 determines that the microprocessor 30 is in an abnormal state, such as running, hanging, abnormal state of the system, or sending error data to the OIS controller, the processor 10 may reset the microprocessor 30 through the reset terminal RST when the microprocessor 30 is in the abnormal state, so that the microprocessor 30 works normally.

With continued reference to FIG. 2, microprocessor 30 also includes a designated port gpio through which processor 10 is coupled to microprocessor 30. Microprocessor 30 may send interrupt status information or other status information through a designated port, and processor 10 may control the microprocessor based on the status information.

It should be noted that, in this embodiment, only some common functions or interfaces required by the microprocessor when splitting the space state data are described, and the technician may also set according to a specific scenario, which is not described herein.

Considering that the sampling periods of the first OIS controller OIS1 and the second OIS controller OIS2 are different, for example, the sampling period (e.g. 2 ms) of OIS1 is smaller than the sampling period (e.g. 5 ms) of OIS2, and/or the sampling period (2 ms) of OIS1 is smaller than the reading period (e.g. 5 ms) of the data read by the microprocessor from the spatial attitude sensor, then the OIS1 is said to be under heavy load, the OIS2 or the data read by the microprocessor is said to be under light load, and then the heavy load always waits for light load after the data is read from the memory. In practical applications, when the OIS controller includes a plurality of OIS controllers, a reference period may be preset, OISn having a sampling period smaller than the reference period is divided into heavy loads, and OISn having a sampling period greater than or equal to the reference period is divided into light loads.

To solve the above problem, the microprocessor 30 of the present embodiment includes a first SPI bus interface SPI1, a second SPI interface SPI2, and a third SPI interface SPI3, referring to fig. 3. The first SPI interface SPI1 of the microprocessor 30 is connected to the first OIS controller OIS1 through an SPI bus; the second SPI interface SPI2 of the microprocessor 30 is connected with the second SPI interface SPI2 of the space attitude sensor 20 through an SPI bus; the third SPI interface SPI3 of the microprocessor 30 is connected to the second OIS controller OIS2 via an SPI bus.

With continued reference to fig. 3, the microprocessor 30 also includes a first APB bus APB1 and a second APB bus APB2. The first SPI bus interface of the microprocessor 30 is connected to the second APB bus APB2, and the second SPI bus interface and the third SPI bus SPI3 of the microprocessor 30 are connected to the first APB bus APB1, respectively. Wherein the priority of the first APB bus APB1 is higher than the priority of the second APB bus APB2. That is, when APB1 and APB2 send request data at the same time, the microprocessor will process the request data of APB1 preferentially because the priority of APB1 is higher than that of APB2, and process the request data of APB2 after the request data of APB1 is processed.

In this way, in this embodiment, the APB2 bus with high priority is matched with the OIS controller with heavy load, and the APB1 bus with low priority is matched with the OIS controller with light load, and after the request data with heavy load is processed, the request data with light load is processed, so that the problem that the request data with light load always waits for the sampling with light load when the request data with heavy load is sampled can be solved, thereby achieving the effect of balancing light load and heavy load.

With continued reference to FIG. 3, the microprocessor also includes an advanced high performance Bus (AHB), a first APB bridge B1, and a second APB bridge. The higher-level high-performance bus is connected to the first APB bus APB1 via a first APB bridge B1, and is connected to the second APB bus APB2 via a second APB bridge B2. Thus, the AHB bus may communicate with the APB1 bus through the first APB bridge B1 and with the APB2 bus through the second APB bridge B2.

The operation of the electronic device for multi-OIS control will be described with reference to the electronic device of fig. 1 and the microprocessor of fig. 3:

When the spatial pose sensor collects the spatial pose data, it communicates with the microprocessor 30. After determining that the microprocessor needs to request data, the microprocessor may store the spatial pose data in the second memory, where the data flow path is: a spatial attitude sensor, an SPI2 bus, an APB1 bus, an APB bridge 1, an AHB bus, a DMA, and a second memory of the memories. When the spatial gesture data in the second memory is detected to reach the specified length, that is, after the update operation of the spatial gesture data is completed, the spatial gesture data in the second memory can be transferred to the first memory.

After the updating of the space attitude data is completed, the microprocessor actively transmits a notification message to each OIS controller and receives the request data transmitted by each OIS controller or directly receives the request data transmitted by each OIS controller. The microprocessor may transmit the spatial pose data to the OIS controllers.

When request data of the APB1 bus and request data of the APB2 bus are received simultaneously, the request data of the APB2 bus are preferentially processed, and the path of the OIS1 controller for acquiring the space attitude data is as follows: a first memory, a DMA, an AHB bus, an APB bridge 2, an APB2 bus, an SPI1 bus, and an OIS1 controller. Then, request data of the APB1 bus are processed, and the path of acquiring the space attitude data by the OIS2 controller is as follows: a first memory, a DMA, an AHB bus, an APB bridge 1, an APB1 bus, an SPI3 bus, and an OIS2 controller.

Fig. 4 is a block diagram of an electronic device, according to an example embodiment. For example, electronic device 400 may be a smart phone, computer, digital broadcast terminal, tablet device, medical device, exercise device, personal digital assistant, or the like.

Referring to fig. 4, an electronic device 400 may include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input/output (I/O) interface 412, a sensor component 414, a communication component 416, and an image acquisition component 418.

The processing component 402 generally controls overall operation of the electronic device 400, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute computer programs. Further, the processing component 402 can include one or more modules that facilitate interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate interaction between the multimedia component 408 and the processing component 402.

The memory 404 is configured to store various types of data to support operations at the electronic device 400. Examples of such data include computer programs, contact data, phonebook data, messages, pictures, videos, etc., for any application or method operating on electronic device 400. The memory 404 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 406 provides power to the various components of the electronic device 400. The power components 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 400. The power supply assembly 406 may include a power chip and the controller may communicate with the power chip to control the power chip to turn on or off the switching device to power the motherboard circuit with or without the battery.

The multimedia component 408 includes a screen between the electronic device 400 and the target object that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a target object. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or sliding action, but also the duration and pressure associated with the touch or sliding operation.

The audio component 410 is configured to output and/or input audio signals. For example, the audio component 410 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 400 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, audio component 410 further includes a speaker for outputting audio signals.

The I/O interface 412 provides an interface between the processing component 402 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc.

The sensor assembly 414 includes one or more sensors for providing status assessment of various aspects of the electronic device 400. For example, the sensor assembly 414 may detect an on/off state of the electronic device 400, a relative positioning of the components, such as a display and keypad of the electronic device 400, the sensor assembly 414 may also detect a change in position of the electronic device 400 or one of the components, the presence or absence of a target object in contact with the electronic device 400, an orientation or acceleration/deceleration of the electronic device 400, and a change in temperature of the electronic device 400. In this example, the sensor assembly 414 may include a magnetic force sensor, a gyroscope, and a magnetic field sensor, wherein the magnetic field sensor includes at least one of: hall sensors, thin film magneto-resistive sensors, and magnetic liquid acceleration sensors.

The communication component 416 is configured to facilitate communication between the electronic device 400 and other devices, either wired or wireless. The electronic device 400 may access a wireless network based on a communication standard, such as WiFi,2G, 3G, 4G, 5G, or a combination thereof. In one exemplary embodiment, the communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 416 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, electronic device 400 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements.

In an exemplary embodiment, a non-transitory readable storage medium is also provided that includes an executable computer program, such as memory 404 including instructions, that is executable by a processor. The readable storage medium may be, among other things, ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An electronic device is characterized by comprising a space attitude sensor, a processor, a microprocessor and a camera module; the space attitude sensor comprises a first SPI interface and a second SPI interface; the camera module comprises at least two OIS controllers; the processor is connected with the space attitude sensor through the first SPI interface; the microprocessor is connected with the space attitude sensor through the second SPI interface;

The microprocessor is used for transmitting the spatial attitude data acquired from the second SPI interface to the at least two OIS controllers;

The microprocessor includes a first memory common to the at least two OIS controllers, the first memory for storing spatial pose data from the spatial pose sensor and each OIS controller for reading spatial pose data from the first memory;

the microprocessor also comprises a second memory, wherein the second memory is used for caching the space posture data from the space posture sensor and transferring the space posture data to the first memory after the cached space posture data meets the specified length.

2. The electronic device of claim 1, wherein the at least two OIS controllers comprise a first OIS controller and a second OIS controller; the microprocessor comprises a first SPI bus interface, a second SPI interface and a third SPI interface;

3. The electronic device of claim 2, wherein the microprocessor further comprises a first APB bus and a second APB bus;

4. The electronic device of claim 3, wherein the first APB bus has a higher priority than the second APB bus.

5. The electronic device of any of claims 2-4, wherein a sampling period of the first OIS controller is less than a sampling period of the second OIS controller, and wherein a sampling period of the first OIS controller is less than a reading period of the microprocessor reading data from the spatial attitude sensor.

6. The electronic device of claim 3, wherein the microprocessor further comprises an advanced high performance bus, a first APB bridge, and a second APB bridge; the high-level high-performance bus is connected with the first APB bus through the first APB bridge, and the high-level high-performance bus is connected with the second APB bus through the second APB bridge.

7. The electronic device of claim 1, wherein the microprocessor includes a memory in one-to-one correspondence with each OIS controller, each memory for storing spatial pose data from the spatial pose sensor and each OIS controller reading the spatial pose data from its corresponding memory.