CN114256159B - Array substrate, manufacturing method and display panel - Google Patents

Array substrate, manufacturing method and display panel Download PDF

Info

Publication number
CN114256159B
CN114256159B CN202111576526.0A CN202111576526A CN114256159B CN 114256159 B CN114256159 B CN 114256159B CN 202111576526 A CN202111576526 A CN 202111576526A CN 114256159 B CN114256159 B CN 114256159B
Authority
CN
China
Prior art keywords
layer
photoresist
electrode
substrate
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111576526.0A
Other languages
Chinese (zh)
Other versions
CN114256159A (en
Inventor
张盛东
周晓梁
廖聪维
林清平
杨欢
邹忠飞
钟德镇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
Original Assignee
Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University Shenzhen Graduate School, InfoVision Optoelectronics Kunshan Co Ltd filed Critical Peking University Shenzhen Graduate School
Priority to CN202111576526.0A priority Critical patent/CN114256159B/en
Publication of CN114256159A publication Critical patent/CN114256159A/en
Application granted granted Critical
Publication of CN114256159B publication Critical patent/CN114256159B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

An array substrate, a manufacturing method and a display panel, wherein the manufacturing method comprises the following steps: forming a scanning line and a grid electrode on a substrate, wherein the scanning line is provided with an overlapping part, the width of the overlapping part is smaller than or equal to twice of the photoresist indentation, and the width of the grid electrode is larger than twice of the photoresist indentation; forming a first insulating layer on a substrate; forming an active layer over the first insulating layer; coating a photoresist layer above the first insulating layer, carrying out photoetching treatment on the photoresist layer from one side of the substrate, which is far away from the photoresist layer, by using a first metal layer mask plate, and forming a photoresist pattern, wherein the grid electrode corresponds to the photoresist pattern, and the photoresist pattern is completely staggered with the overlapping part; and forming a second metal layer on the upper surface of the photoresist layer, etching the second metal layer and removing the photoresist pattern, wherein the second metal layer forms a data line, a source electrode and a drain electrode, and the projection of the data line on the substrate overlaps with the projection of the overlapping part on the substrate. The invention simplifies the manufacturing process, reduces the manufacturing cost and improves the manufacturing efficiency.

Description

Array substrate, manufacturing method and display panel
Technical Field
The invention relates to the technical field of displays, in particular to an array substrate, a manufacturing method and a display panel.
Background
With the development of display technology, light and thin display panels are popular with consumers, especially light and thin display panels (LCDs) CRYSTAL DISPLAY.
The conventional display device includes a thin film transistor array Substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), a color film Substrate (Color Filter Substrate, CF Substrate), and liquid crystal molecules filled between the thin film transistor array Substrate and the color film Substrate, and when the display device is in operation, a driving voltage is respectively applied to a pixel electrode of the thin film transistor array Substrate and a common electrode of the color film Substrate, or a driving voltage is respectively applied to the common electrode and the pixel electrode of the thin film transistor array Substrate, so as to control a rotation direction of the liquid crystal molecules between the two substrates, so as to refract backlight light provided by a backlight module of the display device, thereby displaying a picture.
The thin film transistor array substrate is provided with a plurality of Thin Film Transistors (TFTs), wherein the TFTs comprise a grid electrode, a source electrode, a drain electrode and an active layer, the alignment problem of the grid electrode and the source electrode/drain electrode needs to be considered, the grid electrode length cannot be short, the overlapping amount of the grid electrode and the source electrode/drain electrode is larger, and the parasitic capacitance of a TFT device is larger. In order to reduce the overlapping area of the grid electrode and the source electrode/drain electrode, the prior art uses a photoresist stripping process and a back exposure process to disconnect the source electrode from the drain electrode, namely, before the metal layer is covered, a layer of photoresist is covered, the grid electrode is used as shielding, the photoresist on the metal layer is exposed by adopting the back exposure process, the photoresist in the area corresponding to the grid electrode is reserved, then a layer of metal layer is covered, when the photoresist is stripped, the source electrode and the drain electrode are disconnected, and the self-alignment of the overlapping area of the grid electrode and the source electrode/drain electrode is realized, so that the overlapping area of the grid electrode and the source electrode/drain electrode can be reduced, the parasitic capacitance of the grid electrode and the source electrode/drain electrode is reduced, and the reliability of a grid electrode driving circuit is improved.
However, the scan line is usually made of the same metal layer as the gate electrode, and the data line is usually made of the same metal layer as the source electrode and the drain electrode, so that the data line is not disconnected at the overlapping position of the scan line any more, and therefore, a side-face exposure process is also required to remove the photoresist at the overlapping position of the data line and the scan line. Although the prior art uses a photoresist stripping process and a back exposure process to disconnect the source electrode from the drain electrode, the self-alignment of the overlapped area of the gate electrode and the source electrode/drain electrode can be realized, and the overlapped area and parasitic capacitance of the gate electrode and the source electrode/drain electrode can be reduced, but a front exposure process is added to ensure that the overlapped part of the data line is disconnected at the position where the scanning line is no longer overlapped, and the process is complex.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the invention aims to provide an array substrate, a manufacturing method and a display panel, so as to solve the problem that a self-alignment process is complex in the prior art.
The aim of the invention is achieved by the following technical scheme:
The invention provides a manufacturing method of an array substrate, which comprises the following steps:
Providing a substrate;
Forming a first metal layer above the substrate, etching the first metal layer, patterning the first metal layer to form a scanning line and a grid electrode, wherein the grid electrode is electrically connected with the scanning line, the scanning line is provided with an overlapping part which is overlapped with a data line up and down, the width of the overlapping part is less than or equal to twice of photoresist indentation, and the width of the grid electrode is greater than twice of photoresist indentation;
Forming a first insulating layer over the substrate to cover the scan lines and the gate electrodes;
Forming a semiconductor layer over the first insulating layer, etching the semiconductor layer, and patterning the semiconductor layer to form an active layer;
coating a photoresist layer above the first insulating layer, and carrying out photoetching treatment on the photoresist layer from one side of the substrate, which is far away from the photoresist layer, by using the first metal layer mask plate, wherein the photoresist layer is patterned to form a photoresist pattern, the grid electrode corresponds to the photoresist pattern, and the photoresist pattern is completely staggered with the overlapping part;
Forming a second metal layer on the upper surface of the photoresist layer, etching the second metal layer and removing the photoresist pattern, wherein the second metal layer is patterned to form the data line, the source electrode and the drain electrode, the projection of the data line on the substrate overlaps with the projection of the overlapping part on the substrate, the data line is in conductive connection with the source electrode, and the source electrode and the drain electrode are in conductive connection through the active layer;
And forming a pixel electrode above the first insulating layer, wherein the pixel electrode is in conductive connection with the drain electrode.
Further, the semiconductor layer is made of a material capable of reducing the light diffraction range, and the second metal layer is directly arranged on the upper surface of the semiconductor layer.
Further, a diffraction interference layer is formed above the first insulating layer, the diffraction interference layer can reduce the light diffraction range, the second metal layer is directly arranged on the upper surface of the diffraction interference layer, and the semiconductor layer is directly arranged on the upper surface of the second metal layer.
Further, the width of the scan line is the same as the width of the overlap portion, and the width of the scan line is less than or equal to twice the photoresist setback; or the width of the scan line is larger than the width of the overlapping portion.
Further, the overlapping portions are plural in number and are arranged in parallel with each other at intervals.
Further, a common electrode is formed over the first insulating layer, the common electrode being insulated from the pixel electrode.
The invention also provides an array substrate which is manufactured by adopting the manufacturing method, and the array substrate comprises the following components:
A substrate;
The first metal layer is arranged above the substrate and comprises a scanning line and a grid electrode, the grid electrode is electrically connected with the scanning line, the scanning line is provided with an overlapping part which is overlapped with the data line up and down, the width of the overlapping part is smaller than or equal to twice of the photoresist indentation, and the width of the grid electrode is larger than twice of the photoresist indentation;
The first insulating layer is arranged above the first metal layer and covers the scanning line and the grid electrode;
A semiconductor layer disposed over the first insulating layer, the semiconductor layer including an active layer;
The second metal layer is arranged above the first insulating layer and comprises the data line, a source electrode and a drain electrode, the projection of the data line on the substrate is overlapped with the projection of the overlapping part on the substrate, the data line is in conductive connection with the source electrode, and the source electrode and the drain electrode are in conductive connection through the active layer;
and the pixel electrode is arranged above the first insulating layer and is electrically connected with the drain electrode.
Further, the semiconductor layer is made of a material capable of reducing the light diffraction range, and the second metal layer is directly arranged on the upper surface of the semiconductor layer; or the array substrate further comprises a diffraction interference layer arranged above the first insulating layer, the diffraction interference layer can reduce the light diffraction range, the second metal layer is directly arranged on the upper surface of the diffraction interference layer, and the semiconductor layer is directly arranged on the upper surface of the second metal layer.
Further, the number of the overlapped parts is a plurality and the overlapped parts are arranged in parallel at intervals; or the array substrate further comprises a common electrode arranged above the first insulating layer, and the common electrode and the pixel electrode are mutually insulated.
The invention also provides a display panel which comprises the array substrate, a counter substrate arranged opposite to the array substrate and a liquid crystal layer arranged between the array substrate and the counter substrate.
The invention has the beneficial effects that: by setting the width of the overlapping part of the scanning line and the data line to be less than or equal to twice the photoresist indentation, and setting the width of the grid electrode to be greater than twice the photoresist indentation, when photoetching treatment is carried out on the photoresist layer from one side of the substrate far away from the photoresist layer, the area of the photoresist layer corresponding to the overlapping part is developed and removed, and the area corresponding to the grid electrode is reserved and forms a photoresist pattern, so that after the second metal layer is etched and the photoresist pattern is removed, the data line can be continuous at the overlapping part with the scanning line, and the source electrode and the drain electrode can be disconnected automatically, thereby simplifying the manufacturing process, reducing the manufacturing cost and improving the manufacturing efficiency; and the photoresist pattern is formed from the back of the substrate by photoetching by taking the first metal layer as a mask plate, and the width of the photoresist pattern reserved in the grid region is the same as the interval between the disconnection positions of the source electrode and the drain electrode, so that the overlapping area of the grid electrode and the source electrode and the drain electrode is smaller, the parasitic capacitance of the grid electrode and the source electrode and the drain electrode is reduced, and the reliability of the grid electrode driving circuit is improved.
Drawings
FIGS. 1 and 2 are schematic diagrams of a conventional exposure development process for a photoresist;
FIG. 3 is a schematic plan view of an array substrate according to a first embodiment of the invention;
FIG. 4 is a schematic cross-sectional view of the array substrate along A-A in FIG. 3 according to the first embodiment of the present invention;
FIGS. 5a-5k are schematic cross-sectional views of a method of making a first embodiment of the present invention taken along line A-A in FIG. 3;
FIG. 6 is a schematic cross-sectional view of the array substrate along B-B in FIG. 3 according to the first embodiment of the present invention;
FIGS. 7a-7e are schematic cross-sectional views of a method of manufacturing according to a first embodiment of the present invention along line B-B in FIG. 3;
FIGS. 8a-8f are schematic plan views of a method of manufacturing according to a first embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view of an array substrate along B-B in FIG. 3 according to a second embodiment of the present invention;
FIG. 11 is a schematic plan view of a first metal layer according to a second embodiment of the invention;
FIG. 12 is a schematic cross-sectional view of an array substrate along B-B in FIG. 3 according to a third embodiment of the present invention;
FIG. 13 is a schematic plan view of a first metal layer in a third embodiment of the invention;
FIG. 14 is a schematic cross-sectional view of the array substrate along A-A in FIG. 3 in a fourth embodiment of the present invention.
Detailed Description
In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the following detailed description is given of the specific implementation, structure, characteristics and effects of the array substrate, the manufacturing method, the display panel according to the invention by combining the accompanying drawings and the preferred embodiment, wherein:
Example one
Fig. 3 is a schematic plan view of an array substrate according to an embodiment of the present invention, fig. 4 is a schematic plan view of the array substrate according to the embodiment of the present invention along A-A in fig. 3, fig. 5a-5k are schematic plan views of a manufacturing method according to the embodiment of the present invention along A-A in fig. 3, fig. 6 is a schematic plan view of the array substrate according to the embodiment of the present invention along B-B in fig. 3, fig. 7a-7e are schematic plan views of the array substrate according to the embodiment of the present invention along B-B in fig. 3, fig. 8a-8f are schematic plan views of the manufacturing method according to the embodiment of the present invention, and fig. 9 is a schematic sectional structure of a display panel according to the embodiment of the present invention.
As shown in fig. 3, 4 and 6, an array substrate according to a first embodiment of the present invention includes:
The substrate 10, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, and the substrate 10 may also be a flexible substrate, with suitable materials for the flexible substrate including, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or combinations thereof.
The first metal layer 11 is disposed on the substrate 10, the first metal layer 11 includes a scan line 111 and a gate 112, and the gate 112 is electrically connected to the scan line 111. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.
In this embodiment, the scan line 111 has an overlapping portion 113 (fig. 6) overlapping the data line 131 up and down, the width a1 (fig. 8 a) of the scan line 111 is the same as the width of the overlapping portion 113, the width of the overlapping portion 113 is less than or equal to twice the photoresist setback, and the width a2 (fig. 8 a) of the gate electrode 112 is greater than twice the photoresist setback. The photoresist retraction amount of the photoresist is that when the mask plate is used for exposing the photoresist, certain diffraction action can occur when light passes through the mask plate, so that the width of the photoresist left after development is smaller than the width of the corresponding pattern on the mask plate, and the width difference between the photoresist left after development and the corresponding pattern on the mask plate is the photoresist retraction amount S.
As shown in fig. 1-2, when exposure is performed from the back surface of the substrate 1, using the metal pattern 2 on the substrate 1 as a mask, for example, when exposure is performed from the back surface of the substrate 1, a certain diffraction effect occurs on the edge of the metal pattern 2 by the light passing through the substrate 1, so that after development, the photoresist 3 left on the metal pattern 2 is retracted compared with the metal pattern 2, and the single-side photoresist retraction amount is shown as S in the figure. For example, if the width of the metal pattern 2 is 10 μm and the width of the photoresist 3 left on the metal pattern 2 after development is 9 μm, the photoresist setback is 0.5 μm.
The first insulating layer 101 is disposed over the first metal layer 11, and the first insulating layer 101 covers the scan lines 111 and the gate electrodes 112. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.
The semiconductor layer 12 is disposed over the first insulating layer 101, and the semiconductor layer 12 includes an active layer 121, the active layer 121 corresponding to the gate electrode 112. In this embodiment, the semiconductor layer 12 is made of a material capable of reducing the diffraction range of light, preferably a material having a certain absorption effect on ultraviolet light for exposure so as to reduce the amount of photoresist recession. After the light passes through the semiconductor layer 12, since the semiconductor layer 12 has a certain absorption to the ultraviolet light, the diffraction phenomenon is reduced, so that the light passes through the semiconductor layer 12 to expose, and the photoresist setback is reduced. The semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor layer such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO). So that the width of the remaining photoresist pattern 110 is closer to the width of the gate electrode 112 when the photoresist layer 100 is subjected to a photolithography process from the side of the substrate 10 (fig. 5 d) remote from the photoresist layer 100 (the back surface of the substrate 10). The overlapping area of the gate 112 and the source 132 and the drain 133 is smaller, so that parasitic capacitance between the gate 112 and the source 132/drain 133 is reduced, and the reliability of the gate driving circuit is improved.
The second metal layer 13 is disposed on the upper surface of the semiconductor layer 12, and the second metal layer 13 includes a data line 131, a source electrode 132, and a drain electrode 133. The projection of the data line 131 on the substrate 10 overlaps the projection of the overlapping portion 113 on the substrate 10, i.e., the area where the scan line 111 overlaps the data line 131 is the overlapping portion 113. The data line 131 is conductively connected to the source electrode 132, and the source electrode 132 and the drain electrode 133 are conductively connected through the active layer 121. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.
The second insulating layer 102 is disposed on the upper surface of the second metal layer 13, and the transparent conductive layer 14 is disposed on the upper surface of the second insulating layer 102. The second insulating layer 102 covers the second metal layer 13 and is provided with a contact hole 103 (fig. 5 j) in a region corresponding to the drain electrode 133, and the transparent conductive layer 14 includes a pixel electrode 141, and the pixel electrode 141 is conductively connected to the drain electrode 133 through the contact hole 103. The material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The material of the transparent conductive layer 14 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), cadmium Tin Oxide (CTO), aluminum Zinc Oxide (AZO), indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).
As shown in fig. 5a-5k, fig. 7 a-7 e, and fig. 8a-8f, the present embodiment further provides a method for manufacturing an array substrate, where the method is used for manufacturing the array substrate, and the method includes:
as shown in fig. 5a, 7a and 8a, a substrate 10 is provided. The substrate 10 may be made of glass, quartz, silicon, acrylic, or polycarbonate, and the substrate 10 may also be a flexible substrate, with suitable materials for the flexible substrate including, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or combinations thereof.
A first metal layer 11 is formed over the substrate 10, and the first metal layer 11 is etched, so that the first metal layer 11 is patterned to form a scan line 111 and a gate 112, and the gate 112 is electrically connected to the scan line 111. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.
In this embodiment, the scan line 111 has an overlapping portion 113 (fig. 6 and 8 a) overlapping the data line 131 up and down, that is, the overlapping portion 113 is a region where the scan line 111 overlaps the data line 131 up and down. The width a1 (fig. 8 a) of the scan line 111 is the same as the width of the overlap portion 113, the width of the overlap portion 113 is less than or equal to twice the photoresist setback S, and the width a2 (fig. 8 a) of the gate electrode 112 is greater than twice the photoresist setback S. When the mask plate is used for exposing the photoresist, certain diffraction action can be generated when light passes through the mask plate, so that the width of the photoresist left after development is smaller than the width of the corresponding pattern on the mask plate, and the width difference between the photoresist left after development and the corresponding pattern on the mask plate is the photoresist indentation S.
As shown in fig. 1-2, when exposure is performed from the back surface of the substrate 1, using the metal pattern 2 on the substrate 1 as a mask, for example, when exposure is performed from the back surface of the substrate 1, a certain diffraction effect occurs on the edge of the metal pattern 2 by the light passing through the substrate 1, so that after development, the photoresist 3 left on the metal pattern 2 is retracted compared with the metal pattern 2, and the single-side photoresist retraction amount is shown as S in the figure. For example, if the width of the metal pattern 2 is 10 μm and the width of the photoresist 3 left on the metal pattern 2 after development is 9 μm, the photoresist setback is 0.5 μm.
A first insulating layer 101 covering the scan lines 111 and the gate electrodes 112 is formed over the substrate 10. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.
As shown in fig. 5b and 8b, a semiconductor layer 12 is formed over the first insulating layer 101, the semiconductor layer 12 is etched, the semiconductor layer 12 is patterned to form an active layer 121, and the active layer 121 corresponds to the gate electrode 112. The semiconductor layer 12 is made of a material having a certain absorption effect on ultraviolet light for exposure so as to reduce the photoresist retraction amount, and after the light passes through the semiconductor layer 12, the diffraction phenomenon is reduced because the semiconductor layer 12 has a certain absorption on the ultraviolet light, so that the light passes through the semiconductor layer 12 for exposure, and the photoresist retraction amount is reduced. The semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor layer such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO).
As shown in fig. 5c-5d, fig. 7b-7c, and fig. 8c, a photoresist layer 100 is coated over the first insulating layer 101, the photoresist layer 100 being a positive photoresist. The photoresist layer 100 is exposed from the side of the substrate 10 away from the photoresist layer 100 (i.e., the back side of the substrate 10) using the first metal layer 11 as a mask, and the photoresist layer 100 remains after development to form a photoresist pattern 110. When exposure is performed from the back surface of the substrate 10, a certain diffraction effect occurs at the edge of the overlapping portion 113 by the light passing through the substrate 10, so that after development, the photoresist (if the photoresist is left) left on the overlapping portion 113 is retracted compared to the overlapping portion 113, assuming that the first photoresist retraction amount above the overlapping portion 113 and the scan line 111 is S1. In this embodiment, since the width a1 of the overlapping portion 113 is less than or equal to twice the first photoresist setback amount S1 (i.e. a1<2×s1), after development, the photoresist layer 100 directly above the overlapping portion 113 is completely removed by development (fig. 7b-7 c); the width a2 of the gate electrode 112 is greater than twice the first photoresist setback S1 (i.e. a2>2×s1), so that after development, the photoresist layer 100 directly above the gate electrode 112 remains and forms the photoresist pattern 110, i.e. after exposure and development from the back surface of the substrate 10, the photoresist pattern 110 remains only directly above the gate electrode 112 (fig. 8 c); further, since the semiconductor layer 12 is covered over the gate electrode 112, the semiconductor layer 12 has the effect of reducing the photoresist recession, so that the light passing through the substrate 10 is diffracted at the edge of the gate electrode 112 to a lower degree, and assuming that the photoresist pattern 110 left on the gate electrode 112 after development has S2< S1 (fig. 5c-5 d) compared with the second photoresist recession of the gate electrode 112, the width of the photoresist pattern 110 left directly over the gate electrode 112 is closer to the width of the gate electrode 112, so that the overlapping area between the gate electrode 112 and the source electrode 132 or the drain electrode 133 is smaller, thereby reducing the parasitic capacitance between the gate electrode 112 and the source electrode 132 or the drain electrode 133 and improving the driving reliability. Wherein the first photoresist setback amount S1 is equal to the photoresist setback amount S and greater than the second photoresist setback amount is S2, i.e., s1=s > S2.
As shown in fig. 5e to 5h, 7d and 8d, a second metal layer 13 is formed on the upper surface of the photoresist layer 100 (fig. 5 e), and the second metal layer 13 is etched (fig. 5f to 5 h) such that the second metal layer 13 is patterned to form a data line 131, a source electrode 132 and a drain electrode 133 (fig. 5h and 8 d). The extending direction of the data line 131 intersects with the extending direction of the scan line 111, and the overlapping area where the scan line 111 and the data line 131 intersect with each other is the overlapping portion 113. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.
The specific steps of etching the second metal layer 13 include:
as shown in fig. 5f, a photoresist 200 is coated on the upper surface of the second metal layer 13;
As shown in fig. 5g, the photoresist 200 is subjected to photolithography (exposure, development) using a mask plate, so that the photoresist 200 forms an etching stopper 210;
as shown in fig. 5h, 7d and 8d, the etching barrier layer 210 is used as a barrier to wet-etch the second metal layer 13, and the exposed area of the second metal layer 13 (i.e. the area not covered by the etching barrier layer 210) is removed, so that the second metal layer 13 is patterned to form the data line 131, the source electrode 132 and the drain electrode 133.
As shown in fig. 5i and 8e, the etch stopper 210 is removed, and the photoresist pattern 110 is also removed, and since the photoresist pattern 110 is raised relatively higher than other regions, the second metal layer 13 breaks at the edges of the photoresist pattern 110, and thus the second metal layer 13 directly above the photoresist pattern 110 is also removed when the photoresist pattern 110 is removed, so that after the photoresist pattern 110 is removed, the source electrode 132 and the drain electrode 133 are automatically disconnected, and a channel 134 is formed between the source electrode 132 and the drain electrode 133, the data line 131 is electrically connected to the source electrode 132, and the source electrode 132 and the drain electrode 133 are electrically connected through the active layer 121. The width of the channel 134 is close to the width of the gate 112, so that the overlapping area between the gate 112 and the source 132 or the drain 133 is smaller, thereby reducing parasitic capacitance between the gate 112 and the source 132 or the drain 133, realizing self-alignment of the overlapping area between the gate 112 and the source 132 or the drain 133, and improving the reliability of driving.
As shown in fig. 5j and 7e, a second insulating layer 102 is formed on the etched upper surface of the second metal layer 13, and the second insulating layer 102 covers the data line 131, the source electrode 132, and the drain electrode 133. The second insulating layer 102 is etched such that the second insulating layer 102 forms a contact hole 103 in a region corresponding to the drain electrode 133, and an upper surface of the drain electrode 133 is exposed through the contact hole 103. The material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.
As shown in fig. 5k and 8f, a transparent conductive layer 14 is formed on the upper surface of the second insulating layer 102, and the transparent conductive layer 14 is etched to form a pixel electrode 141, and the pixel electrode 141 is filled in the contact hole 103 and is electrically connected to the drain electrode 133. The material of the transparent conductive layer 14 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.
In this embodiment, by setting the width of the overlapping portion 113 where the scan line 111 overlaps the data line 131 to be less than or equal to twice the photoresist setback, and the width of the gate electrode 112 to be greater than twice the photoresist setback, when the photoresist layer 100 is subjected to the photolithography process from the side of the substrate 10 away from the photoresist layer 100, the region of the photoresist layer 100 corresponding to the overlapping portion 113 is developed and removed, and the region corresponding to the gate electrode 112 remains and forms the photoresist pattern, so that after the second metal layer 13 is etched and the photoresist pattern 110 is removed, the data line 131 can be continuous at the overlapping portion with the scan line 111, and the source electrode 132 and the drain electrode 133 can be disconnected by themselves, thereby simplifying the manufacturing process, reducing the manufacturing cost and improving the manufacturing efficiency; the photoresist pattern 110 is formed by using the first metal layer 11 as a mask plate from the back of the substrate 10, and the width of the photoresist pattern 110 remained in the gate 112 region is the same as the distance between the source 132 and the drain 133, so that the overlapping area of the gate 112 and the source 132 and the drain 133 is smaller, thereby reducing the parasitic capacitance between the gate 112 and the source 132 and the drain 133 and improving the reliability of the gate driving circuit.
As shown in fig. 9, the present embodiment also provides a display panel, which includes the above-mentioned array substrate, a counter substrate 20 disposed opposite to the array substrate, and a liquid crystal layer 30 disposed between the array substrate and the counter substrate 20. An upper polaroid 41 is arranged on the opposite substrate 20, a lower polaroid 42 is arranged on the array substrate, and the transmission axis of the upper polaroid 41 is mutually perpendicular to the transmission axis of the lower polaroid 42. The liquid crystal molecules in the liquid crystal layer 30 are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy), and in an initial state, the positive liquid crystal molecules are in a flat lying posture, and an alignment direction of the positive liquid crystal molecules near the opposite substrate 20 is perpendicular to an alignment direction of the positive liquid crystal molecules 131 near the array substrate, so as to form a TN display mode. It is understood that the array substrate and the counter substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.
In this embodiment, the opposite substrate 20 is a color film substrate, and the opposite substrate 20 is provided with a black matrix 21 and a color resist layer 22, wherein the black matrix 21 corresponds to the scan lines 111, the data lines 141, the thin film transistors and the peripheral non-display area, and the black matrix 21 separates the plurality of color resist layers 22. The color resist layer 22 includes red (R), green (G), and blue (B) color resist materials, and corresponds to the sub-pixels forming the three colors red (R), green (G), and blue (B). The counter substrate 20 is further provided with a common electrode 23 cooperating with the pixel electrode 141, and the pixel electrode 141 and the common electrode 23 are used to form a driving electric field to drive the positive liquid crystal molecules in the liquid crystal layer 30 to deflect, thereby controlling gray scale brightness.
Example two
Fig. 10 is a schematic cross-sectional view of the array substrate along the line B-B in fig. 3 in the second embodiment of the present invention, and fig. 11 is a schematic plan view of the first metal layer in the second embodiment of the present invention. As shown in fig. 10 and 11, the array substrate and the manufacturing method thereof and the display panel provided in the second embodiment of the present invention are substantially the same as those in the first embodiment (fig. 3 to 9), and are different in that in the present embodiment, the number of overlapping portions 113 is plural and are arranged in parallel with each other at intervals, that is, the scan lines 111 are provided with openings 104 in the regions overlapping the data lines 131, so that overlapping portions 113 are formed on the upper and lower sides of the openings 104, respectively. The width a3 of each overlapping portion 113 is less than or equal to twice the first photoresist setback amount S1, so that the photoresist layer 100 is not remained in the area where the scan line 111 and the data line 131 overlap up and down when the photoresist layer 100 is subjected to photolithography, so that the data line 131 may be continuous in the area of the corresponding overlapping portion 113. Meanwhile, the plurality of overlapping portions 113 may also reduce the resistance of the scan line 111 to increase the conductive performance of the scan line 111.
In the present embodiment, the width a3 of each overlapping portion 113 is smaller than the width a1 of the scan line 111, i.e., the width a1 of the scan line 111 is greater than twice the first photoresist setback amount S1 to reduce the resistance of the scan line 111.
Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first embodiment, and will not be described herein.
Example III
Fig. 12 is a schematic cross-sectional view of the array substrate along B-B in fig. 3 in the third embodiment of the present invention, and fig. 13 is a schematic plan view of the first metal layer in the third embodiment of the present invention. As shown in fig. 12 and 13, the array substrate and the manufacturing method and the display panel provided in the third embodiment of the present invention are substantially the same as those in the first embodiment (fig. 3 to 9), and the difference is that in the present embodiment, the width a1 of the scan line 111 is greater than the width a3 of the overlapping portion 113, that is, the width a1 of the scan line 111 is greater than twice the first photoresist setback S1, the scan line 111 forms the notch 105 at both sides of the overlapping portion 113, so that the data line 131 can be ensured to be continuous in the area corresponding to the overlapping portion 113, and meanwhile, the resistance of the scan line 111 can be reduced, and the conductivity of the scan line 111 can be increased.
Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first embodiment, and will not be described herein.
Example IV
FIG. 14 is a schematic cross-sectional view of the array substrate along A-A in FIG. 3 in a fourth embodiment of the present invention. As shown in fig. 14, the array substrate provided in the fourth embodiment of the present invention is substantially the same as the array substrate in the first embodiment (fig. 3 to 9), and is different in that, in the present embodiment, the array substrate further includes a diffraction interference layer 151 disposed above the first insulating layer 101, the diffraction interference layer 151 can reduce the diffraction range of light, and after the light passes through the diffraction interference layer 151, the diffraction range is reduced, that is, the light passes through the diffraction interference layer 151 to perform photolithography, so as to reduce the photoresist retraction amount. The diffraction interference layer 151 is made of a light-transmitting material capable of reducing the diffraction range of light, and preferably made of a material having a certain absorption effect on ultraviolet light for exposure so as to reduce the retraction amount of photoresist.
The second metal layer 13 is directly disposed on the upper surface of the diffraction interference layer 151, and the second metal layer 13 includes a data line 131, a source electrode 132, and a drain electrode 133. The semiconductor layer 12 is directly disposed on the upper surface of the second metal layer 13, the semiconductor layer 12 includes an active layer 121, and the semiconductor layer 12 may be made of monocrystalline silicon or doped monocrystalline silicon.
Further, the array substrate further includes a common electrode 23 disposed above the first insulating layer 101, and the common electrode 23 is insulated from the pixel electrode 141 by a third insulating layer 106. The common electrode 23 has a slit structure and is located above the pixel electrode 141, however, the common electrode 23 may be located below the pixel electrode 141, and the pixel electrode 141 has a slit structure to form a fringe field switching pattern (FRINGE FIELD SWITCHING, FFS). Or the common electrode 23 and the pixel electrode 141 may be located at the same layer to form an In-plane switching mode (In-PLANE SWITCHING, IPS).
The present embodiment also provides a method for manufacturing an array substrate, which is substantially the same as that of the first embodiment (fig. 3 to 9), except that in the present embodiment, reference may be made to fig. 5a to 5k, fig. 7a to 7e, and fig. 8a to 8f, after the first insulating layer 101 is formed;
Forming a diffraction interference layer 151 above a first insulating layer 101, coating a photoresist layer 100 on the upper surface of the diffraction interference layer 151, performing photoetching treatment on the photoresist layer 100 from one side (the back surface of the substrate 10) of the substrate 10 away from the photoresist layer 100 by taking the first metal layer 11 as a mask plate, patterning the photoresist layer 100 to form a photoresist pattern 110, wherein a grid 112 corresponds to the photoresist pattern 110, and the photoresist pattern 110 is completely staggered with an overlapping part 113;
a second metal layer 13 is formed on the upper surface of the photoresist layer 100, the second metal layer 13 covers the photoresist pattern 110 and the diffraction interference layer 151, the photoresist pattern 110 is etched and removed from the second metal layer 13, and the second metal layer 13 is patterned to form a data line 131, a source electrode 132 and a drain electrode 133.
A semiconductor layer 12 is formed on the upper surface of the second metal layer 13, the semiconductor layer 12 is etched, the semiconductor layer 12 is patterned to form an active layer 121, and the active layer 121 corresponds to the gate electrode 112. In this embodiment, the semiconductor layer 12 is not required to be made of a material capable of narrowing the diffraction range of light, and the semiconductor layer 12 may be made of a common semiconductor material such as single crystal silicon or doped single crystal silicon.
A second insulating layer 102 is formed on the upper surface of the semiconductor layer 12, and the second insulating layer 102 covers the data line 131, the source electrode 132, the drain electrode 133, and the active layer 121. The second insulating layer 102 is etched such that the second insulating layer 102 is provided with a contact hole 103 in a region corresponding to the drain electrode 133, and an upper surface of the drain electrode 133 is exposed through the contact hole 103.
A transparent conductive layer 14 is formed on the upper surface of the second insulating layer 102, the transparent conductive layer 14 is etched to form a pixel electrode 141, and the pixel electrode 141 covers the contact hole 103 and is electrically connected to the drain electrode 133.
The third insulating layer 106 is formed on the upper surface of the transparent conductive layer 14 and the common electrode 23 is formed on the upper surface of the third insulating layer 106, with the common electrode 23 and the pixel electrode 141 being insulated apart by the third insulating layer 106.
The present embodiment also provides a display panel which is substantially the same as that in the first embodiment (fig. 9), except that in the present embodiment, the counter substrate 20 is not required to be provided with the common electrode 23.
Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first embodiment, and will not be described herein.
In this document, terms such as up, down, left, right, front, rear, etc. are defined by the positions of the structures in the drawings and the positions of the structures with respect to each other, for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the claimed application. It should also be understood that the terms "first" and "second," etc., as used herein, are used merely for distinguishing between names and not for limiting the number and order.
The present invention is not limited to the preferred embodiments, but is capable of modification and variation in detail, and other modifications and variations can be made by those skilled in the art without departing from the scope of the present invention.

Claims (10)

1. The manufacturing method of the array substrate is characterized by comprising the following steps of:
providing a substrate (10);
Forming a first metal layer (11) above the substrate (10), etching the first metal layer (11), patterning the first metal layer (11) to form a scanning line (111) and a grid electrode (112), wherein the grid electrode (112) is electrically connected with the scanning line (111), the scanning line (111) is provided with an overlapping part (113) overlapped with a data line (131) up and down, the width of the overlapping part (113) is less than or equal to twice photoresist indentation, and the width of the grid electrode (112) is greater than twice photoresist indentation;
forming a first insulating layer (101) over the substrate (10) covering the scan lines (111) and the gate electrodes (112);
forming a semiconductor layer (12) above the first insulating layer (101), etching the semiconductor layer (12), and patterning the semiconductor layer (12) to form an active layer (121);
Coating a photoresist layer (100) above the first insulating layer (101), and carrying out photoetching treatment on the photoresist layer (100) from one side of the substrate (10) away from the photoresist layer (100) by using the first metal layer (11) mask plate, wherein the photoresist layer (100) is patterned to form a photoresist pattern (110), the grid electrode (112) corresponds to the photoresist pattern (110), and the photoresist pattern (110) is completely staggered with the overlapped part (113);
Forming a second metal layer (13) on the upper surface of the photoresist layer (100), etching the second metal layer (13) and removing the photoresist pattern (110), wherein the second metal layer (13) is patterned to form the data line (131), a source electrode (132) and a drain electrode (133), the projection of the data line (131) on the substrate (10) overlaps with the projection of the overlapping part (113) on the substrate (10), the data line (131) is electrically connected with the source electrode (132), and the source electrode (132) and the drain electrode (133) are electrically connected through the active layer (121);
A pixel electrode (141) is formed over the first insulating layer (101), and the pixel electrode (141) is electrically connected to the drain electrode (133).
2. The method for manufacturing an array substrate according to claim 1, wherein the semiconductor layer (12) is made of a material capable of reducing a light diffraction range, and the second metal layer (13) is directly disposed on an upper surface of the semiconductor layer (12).
3. The method of manufacturing an array substrate according to claim 1, wherein a diffraction interference layer (151) is formed above the first insulating layer (101), the diffraction interference layer (151) is capable of reducing a light diffraction range, the second metal layer (13) is directly provided on an upper surface of the diffraction interference layer (151), and the semiconductor layer (12) is directly provided on an upper surface of the second metal layer (13).
4. A method of manufacturing an array substrate according to any one of claims 1 to 3, wherein the width of the scan line (111) is the same as the width of the overlap portion (113), and the width of the scan line (111) is less than or equal to twice the photoresist setback; or the width of the scan line (111) is larger than the width of the overlap portion (113).
5. A method of manufacturing an array substrate according to any one of claims 1 to 3, wherein the number of overlapping portions (113) is plural and arranged in parallel with each other at intervals.
6. A method of manufacturing an array substrate according to any one of claims 1 to 3, wherein a common electrode (23) is formed over the first insulating layer (101), the common electrode (23) being insulated from the pixel electrode (141).
7. An array substrate, wherein the array substrate is manufactured by the manufacturing method according to any one of claims 1 to 6, and the array substrate comprises:
a substrate (10);
A first metal layer (11) disposed above the substrate (10), the first metal layer (11) including a scan line (111) and a gate electrode (112), the gate electrode (112) being electrically connected to the scan line (111), the scan line (111) having an overlapping portion (113) overlapping up and down with a data line (131), a width of the overlapping portion (113) being less than or equal to twice a photoresist setback, the width of the gate electrode (112) being greater than twice the photoresist setback;
A first insulating layer (101) provided above the first metal layer (11), the first insulating layer (101) covering the scanning line (111) and the gate electrode (112);
A semiconductor layer (12) provided above the first insulating layer (101), the semiconductor layer (12) including an active layer (121);
A second metal layer (13) disposed above the first insulating layer (101), the second metal layer (13) including the data line (131), a source electrode (132), and a drain electrode (133), a projection of the data line (131) on the substrate (10) overlapping a projection of the overlapping portion (113) on the substrate (10), the data line (131) being electrically connected to the source electrode (132), the source electrode (132) and the drain electrode (133) being electrically connected through the active layer (121);
And a pixel electrode (141) disposed above the first insulating layer (101), the pixel electrode (141) being electrically connected to the drain electrode (133).
8. The array substrate according to claim 7, wherein the semiconductor layer (12) is made of a material capable of reducing a light diffraction range, and the second metal layer (13) is directly provided on an upper surface of the semiconductor layer (12); or the array substrate further comprises a diffraction interference layer (151) arranged above the first insulating layer (101), the diffraction interference layer (151) can reduce the light diffraction range, the second metal layer (13) is directly arranged on the upper surface of the diffraction interference layer (151), and the semiconductor layer (12) is directly arranged on the upper surface of the second metal layer (13).
9. The array substrate according to claim 7, wherein the number of the overlapping portions (113) is plural and arranged in parallel with each other at intervals; or the array substrate further comprises a common electrode (23) arranged above the first insulating layer (101), and the common electrode (23) and the pixel electrode (141) are mutually insulated.
10. A display panel comprising an array substrate according to any one of claims 7 to 9, a counter substrate (20) arranged opposite to the array substrate, and a liquid crystal layer (30) arranged between the array substrate and the counter substrate (20).
CN202111576526.0A 2021-12-21 2021-12-21 Array substrate, manufacturing method and display panel Active CN114256159B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111576526.0A CN114256159B (en) 2021-12-21 2021-12-21 Array substrate, manufacturing method and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111576526.0A CN114256159B (en) 2021-12-21 2021-12-21 Array substrate, manufacturing method and display panel

Publications (2)

Publication Number Publication Date
CN114256159A CN114256159A (en) 2022-03-29
CN114256159B true CN114256159B (en) 2024-04-30

Family

ID=80793984

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111576526.0A Active CN114256159B (en) 2021-12-21 2021-12-21 Array substrate, manufacturing method and display panel

Country Status (1)

Country Link
CN (1) CN114256159B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101892A (en) * 2007-07-05 2008-01-09 上海广电光电子有限公司 Making method for thin film transistor array base plate
CN106711159A (en) * 2017-03-28 2017-05-24 上海天马微电子有限公司 Array substrate and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI262470B (en) * 2004-12-24 2006-09-21 Quanta Display Inc Method of fabricating a pixel structure of a thin film transistor liquid crystal display

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101892A (en) * 2007-07-05 2008-01-09 上海广电光电子有限公司 Making method for thin film transistor array base plate
CN106711159A (en) * 2017-03-28 2017-05-24 上海天马微电子有限公司 Array substrate and manufacturing method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究;马群刚;周刘飞;喻;马国永;张盛东;;物理学报;20190523(第10期);全文 *
基于金属电极和有机半导体层的制备工艺对有机薄膜晶体管性能的研究;朱大龙;谢应涛;许鑫;欧阳世宏;方汉铿;;半导体光电;20150215(第01期);全文 *

Also Published As

Publication number Publication date
CN114256159A (en) 2022-03-29

Similar Documents

Publication Publication Date Title
US11003012B2 (en) Liquid crystal display device and manufacturing method thereof
KR101497425B1 (en) Liquid crystal display and method of manufacturing the same
US10608052B2 (en) Display substrate and method of manufacturing the same
KR101942982B1 (en) Array substrate for liquid crystal display device and method of fabricating the same
KR20130054780A (en) Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same
JP2012256890A (en) Oxide thin film transistor and manufacturing method of the same
US9696602B2 (en) Manufacturing method of liquid crystal display
KR20100088017A (en) Thin film transistor array panel and method for manufacturing the same
KR101955992B1 (en) Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same
CN113467145B (en) Array substrate, manufacturing method and display panel
CN114660862B (en) Array substrate, manufacturing method and display panel
CN114256159B (en) Array substrate, manufacturing method and display panel
CN114402430A (en) Array substrate, manufacturing method and display panel
KR101266396B1 (en) Color filter substrate, display panel having the same and method or making the same
KR102315527B1 (en) Thin film transistor substrate and method of manufacturing a thin film transistor substrate
US9018623B2 (en) Array substrate, display panel having the same and method of manufacturing the array substrate
CN114787703B (en) Array substrate and manufacturing method thereof
CN114236931B (en) Array substrate, manufacturing method and display panel
CN113589612B (en) Array substrate, manufacturing method and display panel
TWI632671B (en) Liquid crystal display and manufacturing method thereof
CN114594639A (en) Array substrate and manufacturing method
CN117894805A (en) Array substrate, manufacturing method and display device
CN116941028A (en) Manufacturing method of array substrate and array substrate
CN117991552A (en) Array substrate, manufacturing method thereof and display panel
KR20120008382A (en) Liquid crystal display and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant